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    74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ

Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
Part No. 74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ
OCR Text ...ctive Rising Edge) Asynchronous master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0...
Description Synchronous Presettable Binary Counter F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16

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    74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN

NXP Semiconductors
http://
PHILIPS[Philips Semiconductors]
Part No. 74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN
OCR Text ...-triggered clock * Asynchronous master Reset (74F161A) * Synchronous Reset (74F163A) * High speed synchronous expansion * Typical count rate of 130MHz * Industrial range (-40C to +85C) available DESCRIPTION 4-bit binary counters feature a...
Description 4-bit binary counter

File Size 111.89K  /  14 Page

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    74HC273 74HCT273 74HC273D 74HCT273D 74HC273PW 74HC273DB 74HC273N 74HCT273DB 74HCT273N 74HCT273PW 74HC273BQ 74HC273U

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74HC273 74HCT273 74HC273D 74HCT273D 74HC273PW 74HC273DB 74HC273N 74HCT273DB 74HCT273N 74HCT273PW 74HC273BQ 74HC273U
OCR Text ...or or memory * Common clock and master reset * Eight positive edge-triggered D-type flip-flops * See "377" for clock enable version * See "373" for transparent latch version * See "374" for 3-state version * Output capability; standard * IC...
Description Octal D-type flip-flop with reset positive-edge trigger
74HC/HCT273; Octal D-type flip-flop with reset; positive-edge trigger

File Size 58.30K  /  8 Page

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    74HC40102 74HCT401 74HCT40102

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74HC40102 74HCT401 74HCT40102
OCR Text ...t two 4-bit BCD words. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 99) regardless of the state of any other input. The precedence relationship between control inputs is indica...
Description 8-bit synchronous BCD down counter

File Size 80.70K  /  11 Page

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    74HC40103 74HC40103D 74HC40103DB 74HC40103N 74HC40103PW 74HCT40103 74HCT40103D 74HCT40103DB 74HCT40103N 74HCT40103PW 74H

NXP Semiconductors N.V.
ICST[Integrated Circuit Systems]
PHILIPS[Philips Semiconductors]
Part No. 74HC40103 74HC40103D 74HC40103DB 74HC40103N 74HC40103PW 74HCT40103 74HCT40103D 74HCT40103DB 74HCT40103N 74HCT40103PW 74HCT40103U 74HC40103U
OCR Text ...gle 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. The precedence relationship between control inputs is indic...
Description 8-Bit Parallel-Load Shift Registers 16-SOIC -40 to 85 HCT SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN BINARY COUNTER, PDSO16
8-bit synchronous binary down counter 8位同步二进制计数器下

File Size 136.57K  /  17 Page

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    74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74H

PHILIPS[Philips Semiconductors]
Part No. 74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74HCT40105U 74HC40105U
OCR Text ...nputs ground (0 V) asynchronous master reset input (active HIGH) 3-state data outputs data-out ready output shift-out input (HIGH-to-LOW, edge-triggered) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IE...
Description 4-bit x 16-word FIFO register

File Size 199.99K  /  25 Page

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    74HC4015 74HCT4015 HCT4015 74HC4015D 74HC4015N 74HCT4015D 74HCT4015N 74HC4015U

PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
Part No. 74HC4015 74HCT4015 HCT4015 74HC4015D 74HC4015N 74HCT4015D 74HCT4015N 74HC4015U
OCR Text ... and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH ...
Description 74HC/HCT4015; Dual 4-bit serial-in/parallel-out shift register
8-Bit Parallel-Load Shift Registers 16-SO -40 to 85

File Size 50.66K  /  8 Page

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    74HC4020 74HCT4020 74HC4020PW 74HC4020D 74HC4020DB 74HC4020N 74HCT4020D 74HCT4020DB 74HCT4020N 74HCT4020PW 74HC4020U 74H

PHILIPS[Philips Semiconductors]
NXP Semiconductors
Part No. 74HC4020 74HCT4020 74HC4020PW 74HC4020D 74HC4020DB 74HC4020N 74HCT4020D 74HCT4020DB 74HCT4020N 74HCT4020PW 74HC4020U 74HCT4020U
OCR Text ...CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0, Q3 to Q13). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs L...
Description 74HC/HCT4020; 14-stage binary ripple counter

File Size 49.84K  /  7 Page

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    IDT
Part No. IDT5962-9221505M2A IDT5962-9221505MRA
OCR Text master reset 1 june 2002 military and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-2568/2 features: ? std., a, and c grades ? low ...
Description Octal D Flip-Flop with master Reset

File Size 72.72K  /  7 Page

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