...Circuit
+9V VHF in UHF in 0.5p(sl)
51k
1T363
2T
2T
51k
1n
1n
1n
1n
1n
27p 20 1T363
8p(UJ) L1
27p
Vc...a varicap diode to Pin 11 through a coupling capacitor. The positive feedback from the resonance cir...
...ISB1 -- (L version) ISB1 (L-L/L-sl version) --
Output voltage
VOL VOH
-- 2.4
-- --
0.4 --
V V
IOL = 2.1 ma IOH = -1.0 m...a given device and from device to device. 3. This parameter is sampled and not 100% tested. 4. WE is...
Description
131,072-word X 8-bit High Speed CMOS Static RaM 131,072字8位高速CMOS静态RaM Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-CFP -55 to 125 Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-CDIP -55 to 125
...istics is guaranteed only for L-sl version. This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = +25C, f = 1 MHz)
...a given device and from device to device. 4. a write occurs during the overlap (tWP) of a low CS1, a...
...ristic is guaranteed only for L-sl version.
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance No...a given device and from device to device. 4. a write occures during the overlap of a low CS1, a high...
...ristic is guaranteed only for L-sl version.
6
HM62V16256C Series
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance In...a) (VCC = 2.2 V to 2.7 V)
Output load (B) (VCC = 2.7 V to 3.6 V)
8
HM62V16256C Series
Read...
Description
4 M SRaM (256-kword x 16-bit) 四米的SRaM56 - KWord的x 16位)
...ll Time SYMBOL tPLH1 tPHL1 DC t sl(I) tcyc -tcyc t(phase error) tskew t r, t f
4
CONDITION CLK_IN to any output CLK_IN to any output
...a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, F...
...en tdis tjit (per) tjit(hper) t sl(I) t sl(o) tcyc -tcyc t(phase error)4 t skew t r, t f CONDITION CLK_IN to any output CLK_IN to any output...a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, F...
Description
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz) 2.5V的宽量程频率时钟驱动器(33MHz 233MHz
...N tdis Tjit (per) t(jit_hper) t sl(i) t sl(o) Tcyc -Tcyc CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any ou...a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX # YX
YX, FB_OUTC YX, ...
Description
16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)