|
|
|
|
Part No. |
K7A403600M-TC11
|
OCR Text |
...zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enabled signals. wait states... |
Description |
128K X 36 CACHE SRAM, 4 ns, PQFP100
|
File Size |
406.29K /
15 Page |
View
it Online |
Download Datasheet |
|
|
|
|
Part No. |
HYMD512G726L4M
|
OCR Text |
...nced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data st robes and write data masks inputs are sampled on both ris- ing and falli... |
Description |
128Mx72|2.5V|K/H/L|x18|DDR SDRAM - Low Profile Registered DIMM 1GB
|
File Size |
230.79K /
16 Page |
View
it Online |
Download Datasheet |
|
|
|
|
Part No. |
HYMD212G726S4
|
OCR Text |
...nced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data st robes and write data masks inputs are sampled on both ris- ing and fallin... |
Description |
128Mx72|2.5V|K/H/L|x36|DDR SDRAM - Registered DIMM 1GB
|
File Size |
231.41K /
16 Page |
View
it Online |
Download Datasheet |
|
|
|
FREESCALE SEMICONDUCTOR INC
|
Part No. |
MPC9990FA
|
OCR Text |
...s asserted at coincident rising edges of cpu (bank b and qfb signal) and slower system clock (bank a) outputs (see ?qsync phase relation diagram? on page 290), providing baseline timing in systems with fractional clocks. the qsync output is... |
Description |
9990 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
|
File Size |
363.86K /
10 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|