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Melexis
http://
Electronic Theatre Controls, Inc.
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| Part No. |
MLX90110
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| OCR Text |
...nvelope. this is anticipated by delaying each falling edge by a fixed number of rf clock pulses. the modulator is hence driven asymmetrical. each on state is reduced by 8 (4) clocks in 2 (4) kbaud mode, and each off state is prolonged by t... |
| Description |
128-bit OTP/RW transponder
128bit OTP/RW Transponder
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| File Size |
150.08K /
10 Page |
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WHITE ELECTRONIC DESIGNS CORP
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| Part No. |
7P080ATA2003C25 TA2003I25
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| OCR Text |
...ts low level for the purpose of delaying memory access cycle or i/o access cycle. in true ide mode this output signal may be used as iordy. as for this controller, this output is high impedance state constantly. input acknowledge (-inpack: ... |
| Description |
Flash Memory Card(80M位闪速存储器
4M X 16 FLASH 3.3V PROM CARD, 250 ns, XMA68
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| File Size |
580.13K /
66 Page |
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Xilinx, Inc.
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| Part No. |
XC3S400AN-4FG484C XC3S400AN-4FG676C XC3S400AN-4FGG676C XC3S400AN-4FG676I XC3S400AN-4FGG484C XC3S400AN-4TQ144I XC3S400AN-4TQ144C XC3S400AN-4FGG676I XC3S400AN-4TQG144C XC3S400AN-4TQG144I
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| OCR Text |
...al solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a dual ring of staggered iobs surrounds a regular array of clbs. each device has two ... |
| Description |
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA484 FBGA-484
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA676 FBGA-676
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA676 ROHS COMPLIANT, FBGA-676
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA484 ROHS COMPLIANT, FBGA-484
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PQFP144 TQFP-144
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PQFP144 ROHS COMPLIANT, TQFP-144
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| File Size |
1,691.31K /
112 Page |
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Xilinx, Inc.
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| Part No. |
XC3S400AN-4FGG400C XC3S400AN-4FG400C XC3S400AN-4FGG400I XC3S400AN-4FT256I XC3S400AN-4FG400I XC3S400AN-4FTG256C XC3S400AN-4FTG256I
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| OCR Text |
...al solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a dual ring of staggered iobs surrounds a regular array of clbs. each device has two ... |
| Description |
Extended Spartan-3A FPGAs, Package: 4FGG400C FPGA, 896 CLBS, 400000 GATES, 280 MHz, PBGA400
FPGA, 896 CLBS, 400000 GATES, 280 MHz, PBGA400 21 X 21 MM, FBGA-400
FPGA, 896 CLBS, 400000 GATES, 280 MHz, PBGA400 21 X 21 MM, ROHS COMPLIANT, FBGA-400
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA256 FTBGA-256
FPGA, 896 CLBS, 400000 GATES, 667 MHz, PBGA256 ROHS COMPLIANT, FTBGA-256
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| File Size |
3,503.31K /
123 Page |
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it Online |
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Xilinx, Inc.
XILINX INC
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| Part No. |
XC3SD3400A-4CSG484LI XC3SD3400A-4FGG676C
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| OCR Text |
...al solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a dual ring of staggered iobs surrounds a regular array of clbs. the xc3sd1800a has f... |
| Description |
Extended Spartan-3A FPGAs, Package: 4CSG484LI FPGA, 5968 CLBS, 3400000 GATES, 250 MHz, PBGA484
Extended Spartan-3A FPGAs, Package: 4FGG676C FPGA, 5968 CLBS, 3400000 GATES, 250 MHz, PBGA676
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| File Size |
1,352.75K /
99 Page |
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it Online |
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Intersil, Corp.
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| Part No. |
HSP43891GC-25
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| OCR Text |
...l is latched inside the device, delaying its effect by one clock internal to the device. therefore it must be low during the clock cycle immediately preceding presentation of the desired data on the din0-8 inputs. de- tailed operation is sh... |
| Description |
Digital Filter 9-BIT, DSP-DIGITAL FILTER, CPGA85
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| File Size |
145.57K /
18 Page |
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it Online |
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ST Microelectronics
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| Part No. |
AN556
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| OCR Text |
...ting the clamp-prog pin to com. delaying the monitor function fig.12 shows the characteristics of a typical voltage controlled switch. to reach the gate voltage needed for a full conduction of the switch, a certain amount of charge (de- pen... |
| Description |
THE L6353: A SMART GATE DRIVER
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| File Size |
230.84K /
16 Page |
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it Online |
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Xilinx, Inc.
XILINX INC
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| Part No. |
XC3S200-4VQ100I XC3S1000-4FTG256I XC3S200-4PQ208C XC3S200-4PQ208I XC3S200-4VQG100I XC3S200-5VQG100C XC3S200-4PQG208I XC3S50-4CPG132I XC3S5000-4FG900C XC3S1500-4FGG320I XILINXINC-XC3S2000-4FG456I
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| OCR Text |
...a l solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. the xc3s50 has a single column of bloc... |
| Description |
200000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 480 CLBS, 200000 GATES, 630 MHz, PQFP100
1000000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 1920 CLBS, 1000000 GATES, 630 MHz, PBGA256
200000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 480 CLBS, 200000 GATES, 630 MHz, PQFP208
200000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 480 CLBS, 200000 GATES, 725 MHz, PQFP100
XC3S50-4CPG132I FPGA, 192 CLBS, 50000 GATES, 630 MHz, PBGA132
5000000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 8320 CLBS, 5000000 GATES, 630 MHz, PBGA900
1500000 SYSTEM GATE 1.2 VOLT FPGA FPGA, 3328 CLBS, 1500000 GATES, 630 MHz, PBGA320
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| File Size |
2,193.63K /
217 Page |
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it Online |
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Price and Availability
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