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				http:// Vitesse Semiconductor Corporation.
Part No.	VSC9118
OCR Text	...y Adjustment Scheme (LCAS) with hitless Adds and Removes and Fault Isolation External DDR 64 bit SDRAM for Diverse Routing Applications. Differential Delays of up to 108 ms Flexible Payload Processing for Generic Framing Procedure (GFP). Su...
Description	10 Gb/s / Quad 2.5 Gb/s Multi-Service SONET/SDH Mapper Device with Virtual Concatenation Telecomm / Datacomm
File Size	188.00K / 2 Page	View it Online	Download Datasheet

				Connor-Winfield Corporation Connor-Winfield Corpora...
Part No.	STL-S3E
OCR Text	...eatures * 6 Input References * hitless Switch Over * CMOS output up to 77.76 MHz * 8 kHz Output * 12 ppb Composite Hold Over Mode * Fast Acquisition Mode * Manual/ Autonomous Operation * Master/Slave Configuration * Revertive/Nonrevertive ...
Description	Stratum 3E Timing Module Stratum 3E Timing Module
File Size	976.77K / 24 Page	View it Online	Download Datasheet

				Connor-Winfield Corporation Connor-Winfield Corpora...
Part No.	STL-S3
OCR Text	...eatures * 6 Input References * hitless Switch Over * CMOS output up to 77.76 MHz * 8 kHz Output * Fast Acquisition Mode * Manual/ Autonomous Operation * Master/Slave Configuration * Revertive/Nonrevertive Modes Application The Connor-W...
Description	Stratum 3 Timing Module Stratum 3 Timing Module
File Size	1,074.29K / 24 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9547 AD9547_PCBZ AD9547BCPZ AD9547BCPZ-REEL7
OCR Text	...r with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inpu...
Description	Dual/Quad Input Network Clock Generator/Synchronizer
File Size	1,071.49K / 104 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9548 AD9548_PCBZ AD9548BCPZ AD9548BCPZ-REEL7
OCR Text	...r with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs Inp...
Description	Quad/Octal Input Network Clock Generator/Synchronizer
File Size	1,042.25K / 112 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT82V2044BB IDT82V2044BBG IDT82V2044DAG
OCR Text	... Inband Loopback test functions hitless Protection Switching (HPS) for 1 + 1 protection without relays JTAG boundary scan for board test 3.3 V supply with 5 V tolerant I/O Low power consumption Operating temperature range: -40C to +85C Avai...
Description	QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
File Size	664.41K / 61 Page	View it Online	Download Datasheet

				IDT
Part No.	IDT82V2048 IDT82V2048_DS_96859
OCR Text	... inband loopback test functions hitless Protection Switching (HPS) for 1 to 1 protection without relays JTAG boundary scan for board test 3.3V supply with 5V tolerant I/O Low power consumption Operating Temperature Range: -40C to +85C Avail...
Description	OCTAL E1 Short Haul LINE INTERFACE UNIT From old datasheet system
File Size	670.13K / 61 Page	View it Online	Download Datasheet

				ZARLINK[Zarlink Semiconductor Inc]
Part No.	ZL30119 ZL30119GGG ZL30119GGG2
OCR Text	...iant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth * * * * * * * * * * trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en...
Description	SONET/SDH Low Jitter Line Card Synchronizer
File Size	279.80K / 27 Page	View it Online	Download Datasheet

				Zarlink
Part No.	ZL30117
OCR Text	...iant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth * * * * * * * * trst_b tck tdi tms tdo dpll_lock dpll_holdover d...
Description	SONET/SDH Low Jitter Line Card Synchronizer
File Size	250.13K / 23 Page	View it Online	Download Datasheet

				Zarlink Semiconductor
Part No.	ZL30116
OCR Text	...iant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range DPLL2 provides a comprehensive set of features necessary for generating derived ...
Description	SONET/SDH Low Jitter System Synchronizer
File Size	294.27K / 30 Page	View it Online	Download Datasheet

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