...L stabilization time f CLK(a) t sl t STaB
MHz See figure 9 MHz See figure 9 V/ns See figure 9 ms See figure 9
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this frequency modulation can b...
... QH0 QH0 QGn QGn H L h
Clock sl SR a/Qa B/QB C/QC D/QD E/QE F/QF G/Q G H/QH Qa' X X X X X X H L X X X X X H L X X X L L Qa0 Qa0 H L QBn QBn a L L QB0 QB0 Qan Qan QCn QCn b L L QC0 QC0 QBn QBn QDn QDn c L L QD0 QD0 QCn QCn QEn QEn d L L Q...
...X X (323) INPUTS/OUTPUTS SERIaL sl X X X X X X H L X SR X X X X H L X X X Z L L Qa0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L Qa0 H L QBn QBn a L L L QH0 QGn QGn H L h a/Qa H/QH OUTPUTS Qa' QH'
* When one or both output controls are hi...
Description
HC323 8 BIT PIPOSHIFT REGISTER WITH SYNCHRONOUS CLEaR HC299 8 BIT PIPO SHIFT REGISTER WITH aSYNCHRONOUS CLEaR CLEaR HC299 /HC323 8BITPIPOSHIFTREGISTERWITHSYNCHRONOUS HC323 8BITPIPOSHIFTREGISTERWITHSYNCHRONOUS CLEaR HC299 8BITPIPOSHIFTREGISTERWITHaSYNCHRONOUS CLEaR HC299 8 BIT PIPO SHIFT REGISTER WITH aSYNCHRONOUS CLEaR HC323 8 BIT PIPOSHIFT REGISTER WITHSYNCHRONOUS CLEaR 12-Bit, 2.5 us Dual DaC, Serial Input, Pgrmable Settling Time, Q temp available 8-SOIC -40 to 125
...V RW RX RY RZ SD SE SF SG SH SK sl SM SN SP SQ SR BI RHP RKP RLP RMP RNP RPP RQP RRP RSP RTP RUP RVP RWP RXP RYP RZP SDP SEP SFP SGP SHP SKP slP SMP SNP SPP SQP SRP
257
...d with "Z86C9540 aSC/FSC/VSC or sl 1636." 1. ICC1 at HaLT Mode will show a current of 17-18 ma, then will jump to 40-70 ma, and will settle between 1724 ma. Settling time is about 10-15 seconds.
DC-4067-13
(5-17-94)
1
Z86C95 DSP...
... t RST Reset to output time 5 t sl Output slew rate 1 4 0.75 Setup time, fast slew rate 2, 4 Data before CK , CK# t SU 0.9 Setup time, slow...a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (ac voltage...
...tors with K tolerance (10%) and sl characteristics must be used for C1 and C2. * Since this circuit is influenced by the length of the circu...a falling edge on LN21.)
High impedance The previous data is output. (Sixteen bits of caption dat...
Description
Closed Caption Signal Extraction IC Closed Caption Signal Extraction IC(从重叠视频信号中提取接近字符信号的芯 字幕信号提取集成电路(从重叠视频信号中提取接近字符信号的芯片
...cles/16 ms, 1024 cycles/128 ms (sl version) * Fast page mode, read modify write capability * CaS before RaS refresh, hidden refresh, RaS-onl...a start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization ...
Description
1,048,576-Word x 16-Bit DYNaMIC RaM : FaST PaGE MODE TYPE