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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
9DB833AGLF
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| OCR Text |
..._in in 0.7 v d ifferential sr c true input 5 src_in# in 0.7 v differential src complementary input 6oe0# in active low input for enabling dif pair 0. 1 =disable outputs, 0 = enable outputs 7oe3# in active low input for enabling dif pair 3... |
| Description |
9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
224.39K /
18 Page |
 View
it Online |
Download Datasheet
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Integrated Device Techn...
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| Part No. |
932SQ420D
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| OCR Text |
...al outputs w ill result in both true and complement being low due to the termination network
932sq420d pcie gen 2/3 & qpi clock for roml...differential 96mhz output. these are current mode outputs. these are current mode outputs and e... |
| Description |
64-pin TSSOP and MLF packages
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| File Size |
431.75K /
28 Page |
View
it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
IDT5V41067A
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| OCR Text |
...3 dif_in1 in 0.7 v differential true in p ut 4 dif_in1# in 0.7 v differential complementary input 5^pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal osc... |
| Description |
20-pin TSSOP package
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| File Size |
187.52K /
13 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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