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ICS
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| Part No. |
ICS853111-02
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| OCR Text |
...ial input levels: lvpecl, LVDS, cml, SSTL * Maximum output frequency: 3.2GHz * Translates any single ended input signal to 3.3V lvpecl levels with resistor bias on nPCLK input * Output skew: 25ps (typical) * Part-to-part skew: 85ps (typical... |
| Description |
Low Skew, 1-to-10, Differential-to-lvpecl Fanout Buffer. Industrial Temperature.
From old datasheet system
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| File Size |
198.59K /
17 Page |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS853111B ICS853111BYT ICS853111BY ICS853111BYLF ICS853111BYLFT
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| OCR Text |
...ial input levels: lvpecl, LVDS, cml, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V lvpecl levels with resistor bias on nPCLK input * Output skew: 20ps (typical) * Part-to-part skew: 85ps (typical)... |
| Description |
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V lvpecl/ECL FANOUT BUFFER
From old datasheet system
Low Skew, 1-to-10, Differential-to-lvpecl Fanout Buffer. Improved Performance
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| File Size |
204.37K /
18 Page |
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it Online |
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Zarlink
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| Part No. |
ZL30414
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| OCR Text |
...clocks at 622.08 MHz Provides a cml differential clock at 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Lock Indicator Provides...lvpecl differential output clocks at 622.08 MHz, a cml differential clock at 155.52 MHz and a single... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
220.94K /
23 Page |
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it Online |
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zarlink
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| Part No. |
ZL30416
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| OCR Text |
... a differential LVDS, lvpecl or cml reference at 19.44 or 77.76 MHz Provides a LOCK indication 8 mm x 8 mm CABGA package 3.3 V supply Ordering Information ZL30416GGG 64 Ball CABGA
June 2004
*
-40C to +85C
*
Description
The ZL3... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
330.43K /
22 Page |
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it Online |
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ICS
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| Part No. |
ICS8737-11
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| OCR Text |
... following input types: lvpecl, cml, SSTL * Maximum output frequency: 650MHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to lvpecl levels with resistor bias on nCLK input * Output skew: 60ps (maximum) * Part-to-part skew... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator
From old datasheet system
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| File Size |
203.80K /
16 Page |
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it Online |
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ICS
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| Part No. |
ICS8737I-11 ICS8737-11I
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| OCR Text |
... following input types: lvpecl, cml, SSTL * Maximum output frequency: 650MHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to lvpecl levels with resistor bias on nCLK input * Output skew: 75ps (maximum) * Part-to-part skew... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature.
From old datasheet system
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| File Size |
98.98K /
14 Page |
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it Online |
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