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cml lvpecl Datasheet PDF File

For cml lvpecl Found Datasheets File :: 1029 Search Time::1.016ms
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				Cypress
Part No.	CY7B9532V
OCR Text	...t and receive PLLs Differential cml serial input -- Internal termination and DC-restoration Differential cml serial output -- Source matched...lvpecl signaling levels. This can all be done externally by changing VDDQ, VREF, and creating a simp...
Description	SONET OC-48 Transceiver From old datasheet system
File Size	178.35K / 13 Page	View it Online	Download Datasheet

				Micrel Semiconductor
Part No.	SY58021U10 SY58021UMG SY58021UMGTR SY58021UMI SY58021UMITR
OCR Text	...erfaces to differential lvpecl, cml, and LVDS signals (AC- or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output refe...
Description	4GHz, 1:4 lvpecl Fanout Buffer/Translator with Internal Termination Precision Edge
File Size	693.96K / 13 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB6LQ572M NB6LQ572MMNG NB6LQ572MMNR4G
OCR Text	...:1 mux w/input equalizer to 1:2 cml clock/data fanout / translator multi ? level inputs w/ internal termination description the nb6lq572m is...lvpecl, cml, or lvds logic levels. the nb6lq572m incorporates a pair of select pins that will choose...
Description	2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 cml Clock/Data Fanout / Translator
File Size	810.67K / 10 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB4L52
OCR Text	...l accept lvpecl, LVCMOS, LVTTL, cml, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential lvpecl outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative ed...
Description	2.5 to 5.5V ECL D-Flip-flop w/Diff Reset & Input Terms From old datasheet system
File Size	66.58K / 8 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NB6L11 NB6L11DTR2 NB6L11D NB6L11DR2 NB6L11DT
OCR Text	... LVNECL, lvpecl, LVTTL, LVCMOS, cml, or LVDS. The outputs are 800 mV ECL signals. * Maximum Input Clock Frequency w 6 GHz Typical * Maximum Input Data Rate w 6 Gb/s Typical * Low 14 mA Typical Power Supply Current * 150 ps Typical Propagati...
Description	2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL lvpecl/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 6GHz 2.5V/3.3V Multilevel Input to Differential LVNECL/lvpecl 1:2 Clock or Data Fanout Buffer/Transl From old datasheet system
File Size	112.11K / 12 Page	View it Online	Download Datasheet

				on
Part No.	NB6L16
OCR Text	... (Positive ECL), LVTTL, LVCMOS, cml, or LVDS. Outputs are 800 mV ECL signals. The VBB pin, an internally generated voltage supply, is availa...lvpecl, LVNECL, LVCMOS, LVTTL and cml Input Compatible 8 1 SOIC-8 D SUFFIX CASE 751 6L16 ALYW 1 ...
Description	6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential LVECL Clock or Data Translator/Receiver/Drive From old datasheet system
File Size	112.87K / 12 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NB6L239 NB6L239MN NB6L239MNR2
OCR Text	... Compatibility with LVDS/lvpecl/cml/HSTL * Rise/Fall Time 70 ps Typical * < 10 ps Typical Output-to-Output Skew * Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs * Internal 50 W Termination Provided * Random Clock Jitter < 1 ps RMS ...
Description	2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT 1/2/4/8, 2/4/8/16 Clock Divider From old datasheet system 2.5 V / 3.3V Any Differential Clock IN to Differential lvpecl OUT Dual Bank 1/2/4/8 and 2/4/8/16 Div 2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT ±1/2/4/8, ±2/4/8/16 Clock Divider 2.5 V / 3.3 V Any Differential Clock IN to Differential lvpecl OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider
File Size	90.71K / 12 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB6LQ572MNG NB6LQ572MNR4G
OCR Text	...ill accept differential lvpecl, cml, or lvds logic levels. the nb6lq572 incorporates a pair of select pins that will choose one of four differential inputs and will produce two identical lvpecl output copies of clock or data. as such, the n...
Description	2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 lvpecl Clock/Data Fanout / Translator
File Size	179.89K / 10 Page	View it Online	Download Datasheet

				MICREL[Micrel Semiconductor]
Part No.	SY89112U SY89113UMGTR SY89113U SY89113UMG
OCR Text	...(AC- or DC-coupled) LVDS, HSTL, cml, and lvpecl logic levels as small as 200mV (400mVPP). CLK1 input requires external termination. LVDS output swing 325mV into 100 with extremely fast rise/fall time guaranteed to be less than 250ps. The SY...
Description	2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Intermal Termination From old datasheet system
File Size	620.73K / 14 Page	View it Online	Download Datasheet

For cml lvpecl Found Datasheets File :: 1029 Search Time::1.016ms
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