| PART |
Description |
Maker |
| SN74LS107D SN74LS107N SN54LS107J SN54LS107A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
Motorola Inc
MOTOROLA[Motorola Inc]
|
| SN74LS112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola, Inc
|
| N74F114D N74F114N 74F114 |
Dual J-K negative edge-triggered flip-flop with common clock and reset
|
NXP Semiconductors
|
| IDT74LVC112A 74LVC112A_DS_87847 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
From old datasheet system
|
IDT
|
| 74F113 I74F113D I74F113N N74F113D N74F113N 74F113_ |
From old datasheet system
Dual J-K negative edge-triggered flip-flops without reset
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| 54LS76A/BDAJC |
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14
|
MOTOROLA INC
|
| 74HC73 74HC73PW 74HC73D |
Dual JK flip-flop with reset; negative-edge trigger
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors
|
| CD74ACT112E |
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
|
HARRIS SEMICONDUCTOR
|
| 74LVX112SJ 74LVX112 74LVX112M 74LVX112MTC 74LVX112 |
LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
Low Voltage Dual J-K Flip-Flops with Preset and Clear
|
FAIRCHILD SEMICONDUCTOR CORP
FAIRCHILD[Fairchild Semiconductor]
|
