| PART |
Description |
Maker |
| 5962-8978501YA 5962-8978501PC 5962-8978501YC 5962- |
5962-8978501YA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501PC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501YC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-89785022A · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501ZA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KPC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KYA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KPA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KZA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501PA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-9800201KFC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8981001PA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
6N140A/883B · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
8302401FC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
|
Agilent (Hewlett-Packard)
|
| SIL15E-05S1V8-VJ SIL15E-05W3V3-VJ SIL15E SIL15E-05 |
3.0 Vin to 5.5 Vin Single output
|
ARTESYN[Artesyn Technologies]
|
| SMT10E-05S1V2J |
3.0 Vin to 5.5 Vin Single output
|
Artesyn Technologies
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| LTC2900 LTM4600HVMP LTM4601 LT3837 LT3825 LTM4601A |
Low VIN, 8A DC/DC Module Regulator with Tracking, Margining, and Frequency Synchronization
8A, Low VIN DC/DC µModule with Tracking, Margining, Multiphase and Frequency Synchronization
|
Linear Technology
LINEAR TECHNOLOGY CORP
|
| KM416C1004CJ-5 KM416C1004CJ-6 KM416C1004CJL-6 KM41 |
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, self-refresh
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 45ns, VCC=5.0V, self-refresh
|
Samsung Electronic
|
| 5962-05238 5962-05240 5962-05241 5962-05242 5962-0 |
30W Total Output Power 28 Vin 1.5 Vout Single DC-DC Radiation Hardened Converter in a LS Package. DLA Number 5962-05238
30W Total Output Power 28 Vin 5 Vout Single DC-DC Radiation Hardened Converter in a LS Package. DLA Number 5962-05240
30W Total Output Power 28 Vin /-12 Vout Dual DC-DC Radiation Hardened Converter in a LS Package. DLA Number 5962-05241
30W Total Output Power 28 Vin /-15 Vout Dual DC-DC Radiation Hardened Converter in a LS Package. DLA Number 5962-05242
30W Total Output Power 28 Vin 12 Vout Single DC-DC Radiation Hardened Converter in a LS Package. DLA Number 5962-06241
30W Total Output Power 28 Vin 2.5 Vout Single DC-DC Radiation Hardened Converter in a LS Package.
|
International Rectifier
|
| LTM8020 LTM8021 LTM8022 LTM8023 LTM4608AEVPBF LTM4 |
Low VIN, 8A DC/DC Module Regulator with Tracking, Margining, and Frequency Synchronization
8A, Low VIN DC/DC µModule with Tracking, Margining, Multiphase and Frequency Synchronization; Package: LGA; No of Pins: 68; Temperature Range: -40°C to 125°C 10 A SWITCHING REGULATOR, 1750 kHz SWITCHING FREQ-MAX, BGA68
|
http://
Linear Technology, Corp.
|
| IS62LV1024 IS62LV1024LL IS62LV1024L IS62LV1024L-45 |
128K x 8 LOW POWER AND LOW Vcc 128K的8低功耗和低成本吓
128K*8 LOW POWER AND LOW Vcc CMOS STATIC RAM
ASYNCHRONOUS STATIC RAM
|
Samsung Semiconductor Co., Ltd.
Glenair, Inc.
N.A.
ICSI[Integrated Circuit Solution Inc]
|
| MIC5325-1.2YMT MIC5325-1.5YMT MIC5325-1.8YMT |
Low VIN/VOUT 400mA ULDO with Ultra-Low IQ
Low VIN/VOUT 400mA ULDO⑩ with Ultra-Low IQ
|
Micrel Semiconductor
|
| LP28019-00 |
Vin Over Voltage Protection:6.5V
|
Lowpower Semiconductor ...
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