| PART |
Description |
Maker |
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74LCX112SJ 74LCX112 74LCX112M 74LCX112MTC 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
Fairchild Semiconductor, Corp.
http://
FAIRCHILD[Fairchild Semiconductor]
|
| 74HC73 74HC73D 74HC73DB 74HC73N 74HC73PW 74HCT73 |
Dual JK flip-flop with reset; negative-edge trigger
|
PHILIPS[Philips Semiconductors]
|
| SN54LS113A SN74LS113A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP JK负边沿触发器
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| M74LS73AP |
Dual J-K Negative Edge-Triggered Flip Flop with Reset
|
MITSUBISHI[Mitsubishi Electric Semiconductor]
|
| 74HC73 74HC73D 74HC73N 74HC73DB 74HCT73 |
Dual JK flip-flop with reset; negative-edge trigger
|
http://
NXP Semiconductors
|
| PO74G112ATR PO74G112ATU PO74G112ASU PO74G112ASR |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
|
Potato Semiconductor Corporation
|
| IDT74LVC112A 74LVC112A_DS_87847 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
From old datasheet system
|
IDT
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
| CD74HCT73E |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
