PART |
Description |
Maker |
CY7C1302DV25-167BZC CY7C1302DV25-167BZI CY7C1302DV |
9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR垄芒 Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture
|
Cypress Semiconductor
|
CY7C1302CV25-167 CY7C1302CV25 CY7C1302CV25-133 CY7 |
9-Mbit Burst of Two Pipelined SRAMs with QDR(TM) Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
|
CYPRESS[Cypress Semiconductor]
|
CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR-II SRAM 4-Word Burst Architecture 36-Mbit QDR-II SRAM 2-Word Burst Architecture 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Flow-through SRAM with NoBL Architecture 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture SPI Serial EEPROM SPI串行EEPROM 36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM 256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc. Electronic Theatre Controls, Inc.
|
CY7C1302DV25-167BZC |
9-Mbit Burst of Two Pipelined SRAMs with QDRArchitecture
|
Cypress
|
CY7C1302CV25-167BZC |
9-Mbit Burst of Two Pipelined SRAMs with QDR(TM) Architecture
|
CYPRESS
|
CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV |
Memory : Sync SRAMs 18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
|
Cypress Semiconductor
|
M36L0R7060T1 M36L0R7060B1 M36L0R7060B1ZAQE M36L0R7 |
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
|
STMicroelectronics ST Microelectronics, Inc.
|
CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR-II SRAM 4-Word Burst Architecture 18-Mbit DDR-II SRAM 2-Word Burst Architecture 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
M36L0R8060T1ZAQE M36L0R8060T1ZAQF M36L0R8060T1ZAQT |
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
|
STMICROELECTRONICS[STMicroelectronics]
|
M36P0R9060E0 M36P0R9060E0ZACE M36P0R9060E0ZACF |
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
|
Numonyx B.V
|
M36P0R9060N0ZANE M36P0R9060N0ZANF M36P0R9060N0 |
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package
|
Numonyx B.V
|