PART |
Description |
Maker |
HMCAB120G HMCAB112G HMCAB132G HMCAB182G HMCAB184G |
HIGH DENSITY CARD EDGE .050 [1.27] VESA MICRO CHANNEL ARCHITECTURE (MCA)
|
Adam Technologies, Inc.
|
M5-128/120-5YI M5-128/120-5YC M5-128/160-5YI M5-19 |
Fifth Generation MACH Architecture 第五代马赫架 Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 12 ns, PBGA256 Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 15 ns, PBGA352
|
Lattice Semiconductor Corporation Lattice Semiconductor, Corp. Air Cost Control
|
CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR-II SRAM 4-Word Burst Architecture 36-Mbit QDR-II SRAM 2-Word Burst Architecture 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Flow-through SRAM with NoBL Architecture 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture SPI Serial EEPROM SPI串行EEPROM 36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM 256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc. Electronic Theatre Controls, Inc.
|
PRESENTATION |
Presentation - AMDNext Generation Microprocessor Architecture AMDs Next Generation Microprocessor Architecture
|
Advanced Micro Devices
|
CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 18兆位(为512k × 36/1M × 18)流体系结构,通过与NoBLTM的SRAM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
|
Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
|
CY7C1514KV18 CY7C1514KV18-300BZXC CY7C1512KV18-300 |
72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
CY7C1550KV18-450BZC CY7C1550KV18-400BZC CY7C1548KV |
Sync SRAM; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165 72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress Semiconductor, Corp.
|
89177-6030 89177-6011 |
Edge Connector,PCB Mnt,RECEPT,120 Contacts,0.05 Pitch,PC TAIL Terminal 120 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SOLDER ASSY 1.27 EDGE CONN CARD 120 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SOLDER
|
Molex, Inc.
|
50-10A-20 50-12B-10 |
Card Edge Connector; Contact Termination:Solder; Leaded Process Compatible:Yes RoHS Compliant: Yes SINGLE PART CARD EDGE CONN
|
Cinch Connectors
|
CY7C1568KV18-500BZXC CY7C1568KV18-500BZC CY7C1570K |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp. CYPRESS SEMICONDUCTOR CORP
|
CY7C1315AV18-250BZC CY7C1311AV18 CY7C1311AV18-167B |
18-Mb QDR(TM)-II SRAM 4-Word Burst Architecture 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
CY7C1305BV25 CY7C1305BV25-100BZC CY7C1305BV25-167B |
18-Mbit Burst of 4 Pipelined SRAM with QD(TM) Architecture 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture From old datasheet system
|
CYPRESS[Cypress Semiconductor]
|