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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16347
192-BIT AC-PDP DRIVER
DESCRIPTION
The PD16347 is a high-withstanding-voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 192-bit bi-directional shift register, 192-bit latch and high-withstanding-voltage CMOS driver. The logic block operates with a 5.0 V power supply and 3.3 V interface so that it can be directly connected to a gate array and microcomputer. The driver block provides a high-withstanding-voltage output: 80 V. The logic and driver blocks are made of CMOS circuits, consuming lower power.
FEATURES
* 3-ch, 4-ch, 6-ch and 6-ch (3-ch + 3-ch) input port switching is possible using the IBS1 and IBS2 pins * Many outputs: 192-bit output * Clock transfer is switchable via the SDS pin between single edge and double edge * Data control with transfer clock (external) and latch * High-speed data transfer: fCLK = 60 MHz MAX. (at loading of data) * On-chip chip temperature detection circuit * High withstanding voltage and high drive output: 80 V MAX., +15/-30 mA MAX. * 3.3 V input interface (VDD1 = 5.0 V) * High-withstanding-voltage CMOS structure
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16347N-xxx
Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S16472EJ1V0DS00 (1st edition) Date Published June 2003 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
2002
PD16347
1. BLOCK DIAGRAM
(1) IBS1 = L, IBS2 = H: 3-bit input
HZ
/LBLK /HBLK VDD2 /LE
SR1 A1 CLK R,/L A1 CLK R,/L S190 CLR S1 S4 S1 S2 S3
LE /L1 O1
VSS2
/CLR SR2 A2 A2 CLK R,/L S191 CLR S2 S5
SR3 A3 A3 CLK R,/L S192 CLR S190 S191 S192 S3 S6 VDD2
/L192
O192
64-bit shift register VDD3 VSS2
DET
Temperature detection
VSS3
Remark /xxx indicates active low signal.
2
Data Sheet S16472EJ1V0DS
PD16347
(2) IBS1 = L, IBS2 = L: 4-bit input
HZ
/LBLK /HBLK VDD2 /LE SR1 A1 S1 S5 CLK R,/L S189 CLR SR2 A2 S2 S6 CLK R,/L S190 CLR SR3 A3 S3 S7 CLK R,/L S191 CLR SR4 A4 S4 S8 CLK R,/L S192 CLR 48-bit shift register VDD3 S189 S190 S191 S192 /L192 VSS3 O192
A1 CLK R,/L /CLR A2
S1 LE S2 /L1 S3 S4
O1
VSS2
A3
A4
VDD2
DET
Temperature detection
VSS2
Data Sheet S16472EJ1V0DS
3
PD16347
(3) IBS1 = H, IBS2 = L: 6-bit input
HZ
/LBLK /HBLK VDD2 /LE SR1 A1 S1 S7 CLK R,/L S187 CLR SR2 A2 S2 S8 CLK R,/L S188 CLR SR3 A3 S3 S9 CLK R,/L S189 CLR SR4 A4 S4 S10 CLK R,/L S190 CLR SR5 A5 S5 S11 CLK R,/L S191 CLR SR6 A6 S6 S12 CLK R,/L S192 CLR 32-bit shift register VDD3 VSS2
A1 CLK R,/L
A2
S1 LE S2 /L1 S3 S4 S5 S6 VSS2
O1
/CLR A3
A4
A5
VDD2 S187 S188 S189 S190 S191 S192
A6
/L192
O192
DET
Temperature detection
VSS3
4
Data Sheet S16472EJ1V0DS
PD16347
(4) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input
HZ
/LBLK /HBLK VDD2 /LE SR1 S1 A1 S4 CLK R,/L S94 CLR SR2 S2 A2 S5 CLK R,/L S95 CLR SR3 S3 A3 S6 CLK R,/L S96 CLR SR4 S97 A4 CLK S187 R,/L S190 CLR SR5 S98 A5 CLK S188 R,/L S191 CLR SR6 S99 A6 CLK S189 R,/L S192 CLR 32-bit shift register VDD3 VSS2 S94 S95 S96 S97 S98 S99
A1 CLK R,/L
S1 LE S2 /L1 S3 S4
O1
A2
VSS2
/CLR A3
A4
A5
VDD2 S187 S188 S189 S190 S191 S192
A6
/L192
O192
DET
Temperature detection
VSS3
Data Sheet S16472EJ1V0DS
5
PD16347
2. PIN CONFIGURATION (IC pad surface)
PD16347N-xxx: TCP (TAB package)
O192 VSS2 VDD2 VSS2 A6 A5 A4 A3 A2 A1 SDS /LE /CLR CLK /LBLK VDD3 DET VSS3 /HBLK VDD1 HZ IBS1 IBS2 VSS1 R,/L VSS2 VDD2 VSS2 O4 O3 O2 O1 O191 O190 O189
IC pad surface
Remark This figure does not specify the TCP package.
6
Data Sheet S16472EJ1V0DS
PD16347
3. PIN FUNCTIONS
Symbol /LBLK /HBLK /LE HZ /CLR A1 to A3 (6) Pin Name Low blanking High blanking Latch enable Output high impedance Register clear Data I/O Input Input Input Input Input Input /LBLK = L: All output = L /HBLK = L: All output = H Latch operation performed at the falling edge. HZ = H: All output set to the high-impedance state /CLR = L: All shift register data cleared to the low level The A1 to A3 (6) are Data input pins. The data shift direction is switched inside the R,/L pin. CLK Clock Input SDS = H: Shift operation is executed at the rising and falling edges SDS = L: Shift operation is executed at the rising edge R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the shift register are as follows. R,/L = H (right shift): SR1: A1 S1...S190 (SR2 to SR6 also shift in the same direction.) R,/L = L (left shift): SR1: A1 S190...S1 (SR2 to SR6 also shift in the same direction.) Refer to 5. INTERNAL REGISTER. IBS1, IBS2 Input mode switch Input IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, Length of shift register: 32-bit IBS1 = H, IBS2 = L: 6-bit input, Length of shift register: 32-bit IBS1 = L, IBS2 = H: 3-bit input, Length of shift register: 64-bit IBS1 = L, IBS2 = L: 4-bit input, Length of shift register: 48-bit DET Temperature detection Output The DET is N-ch open-drain output. Low level is output (N-ch transistor: ON) via temperature detection. SDS Clock edge switch Input SDS = H: Shift operation is executed at the rising and falling edges of CLK (double edge) SDS = L: Shift operation is executed at the rising edge of CLK (single edge) O1 to O192 VDD1 VDD2 VDD3 High withstanding voltage Logic power supply Driver power supply Temperature detection power supply VSS1 VSS2 VSS3 Logic ground Driver ground Temperature detection ground - - - Connect to system ground Connect to system ground Connect to system ground Output - - - 70 V 5 V 5% 15 to 70 V 5 V 10% Description
Caution In 3-bit and 4-bit input mode, unused input pins must be held at the low level or high level.
Data Sheet S16472EJ1V0DS
7
PD16347
4. TRUTH TABLE
Shift Register Block
Input R,/L H H H H L L L L SDS H H L L H H L L CLK or H or L H or L or H or L H or L Right shift operation is executed. Hold Right shift operation is executed. Hold Left shift operation is executed. Hold Left shift operation is executed. Hold Shift Register
Latch Block
/LE H or L Latch Sn data Hold latch (output) data Output State of Latch Section (/Ln)
Driver Block
A /HBLK /LBLK HZ Output State of Driver Block O1 to O192 x x x L H L x x H H H L x H H L L H L L All driver output: H All driver output: L All driver output: High-impedance L H
Remark x: H or L
8
Data Sheet S16472EJ1V0DS
PD16347
5. INTERNAL REGISTER
Shift Direction (R,/L = H, right shift)
3-bit input SR1 (A1 input register) SR2 (A2 input register) SR3 (A3 input register) SR4 (A4 input register) SR5 (A5 input register) SR6 (A6 input register) A1 S1, S4 ... S190 A2 S2, S5 ... S191 A3 S3, S6 ... S192 4-bit input A1 S1, S5 ... S189 A2 S2, S6 ... S190 A3 S3, S7 ... S191 A4 S4, S8 ... S192 6-bit input A1 S1, S7 ... S187 A2 S2, S8 ... S188 A3 S3, S9 ... S189 A4 S4, S10 ... S190 A5 S5, S11 ... S191 A6 S6, S12 ... S192 6-bit (3-bit + 3-bit) input A1 S1, S4 ... S94 A2 S2, S5 ... S95 A3 S3, S6 ... S96 A4 S97, S100 ... S190 A5 S98, S101 ... S191 A6 S99, S102 ... S192
Shift Direction (R,/L = L, left shift)
3-bit input SR1 (A1 input register) SR2 (A2 input register) SR3 (A3 input register) SR4 (A4 input register) SR5 (A5 input register) SR6 (A6 input register) A1 S190, S187 ... S1 A2 S191, S188 ... S2 A3 S192, S189 ... S3 4-bit input A1 S189, S185 ... S1 A2 S190, S186 ... S2 A3 S191, S187 ... S3 A4 S192, S188 ... S4 6-bit input A1 S187, S181 ... S1 A2 S188, S182 ... S2 A3 S189, S183 ... S3 A4 S190, S184 ... S4 A5 S191, S185 ... S5 A6 S192, S186 ... S6 6-bit (3-bit + 3-bit) input A1 S94, S91 ... S1 A2 S95, S92 ... S2 A3 S96, S93 ... S3 A4 S190, S187 ... S97 A5 S191, S188 ... S98 A6 S192, S189 ... S99
Data Sheet S16472EJ1V0DS
9
PD16347
6. TIMING CHART
(1) IBS1 = L, IBS2 = H: 3-bit input, SDS = L: single edge
CLK /CLR A1 (A3) A2 (A2) A3 (A1)
S1 (S192) S2 (S191) S3 (S190) S4 (S189)
/LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189)
Remark Values in parentheses are when R,/L = L.
10
Data Sheet S16472EJ1V0DS
PD16347
(2) IBS1 = L, IBS2 = H: 3-bit input, SDS = H: double edge
Loading of data starts at first falling edge or at first rising edge CLK
/CLR A1 (A3) A2 (A2) A3 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189)
/LE /LBLK /HBLK HZ
(Latch at the falling edge)
High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189)
Remark Values in parentheses are when R,/L = L.
Data Sheet S16472EJ1V0DS
11
PD16347
(3) IBS1 = L, IBS2 = L: 4-bit input, SDS = L: single edge
CLK /CLR A1 (A4) A2 (A3) A3 (A2)
A4 (A1)
S1 (S192) S2 (S191) S3 (S190) S4 (S189)
/LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190)
O4 (O189)
Remark Values in parentheses are when R,/L = L.
12
Data Sheet S16472EJ1V0DS
PD16347
(4) IBS1 = L, IBS2 = L: 4-bit input, SDS = H: double edge
Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A4) A2 (A3) A3 (A2)
A4 (A1)
S1 (S192) S2 (S191) S3 (S190) S4 (S189)
/LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190)
O4 (O189)
Remark Values in parentheses are when R,/L = L.
Data Sheet S16472EJ1V0DS
13
PD16347
(5) IBS1 = H, IBS2 = L: 6-bit input, SDS = L: single edge
CLK /CLR A1 (A6) A2 (A5) A3 (A4) A4 (A3) A5 (A2) A6 (A1)
S1 (S192) S2 (S191) S3 (S190) S4 (S189) S5 (S188) S6 (S187) /LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190)
O4 (O189) O5 (O188)
O6 (O187)
Remark Values in parentheses are when R,/L = L.
14
Data Sheet S16472EJ1V0DS
PD16347
(6) IBS1 = H, IBS2 = L: 6-bit input, SDS = H: double edge
Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A6) A2 (A5) A3 (A4) A4 (A3) A5 (A2) A6 (A1)
S1 (S192) S2 (S191) S3 (S190) S4 (S189) S5 (S188) S6 (S187) /LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190)
O4 (O189) O5 (O188)
O6 (O187)
Remark Values in parentheses are when R,/L = L.
Data Sheet S16472EJ1V0DS
15
PD16347
(7) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, SDS = L: single edge
CLK /CLR A1 (A3) A2 (A2) A3 (A1) A4 (A6) A5 (A5) A6 (A4)
S1 (S96) S2 (S95) S3 (S94) S97 (S192) S98 (S191) S99 (S190) /LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94)
O97 (O192) O98 (O191)
O99 (O190)
Remark Values in parentheses are when R,/L = L.
16
Data Sheet S16472EJ1V0DS
PD16347
(8) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, SDS = H: double edge
Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A3) A2 (A2) A3 (A1) A4 (A6) A5 (A5) A6 (A4)
S1 (S96) S2 (S95) S3 (S94) S97 (S192) S98 (S191) S99 (S190) /LE
(Latch at the falling edge)
/LBLK /HBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94)
O97 (O192) O98 (O191)
O99 (O190)
Remark Values in parentheses are when R,/L = L.
Data Sheet S16472EJ1V0DS
17
PD16347
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = VSS3 = 0 V)
Parameter Logic and temperature detection supply voltage Driver supply voltage Logic input voltage Temperature detection input voltage Operating junction temperature Storage temperature Symbol VDD1, VDD3 VDD2 VI1 VI3 Tj Tstg Ratings -0.5 to +6.0 -0.5 to +80 -0.5 to VDD1 + 0.5 -0.5 to VDD3 + 0.5 +125 -65 to +125 Unit V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = -40 to +85C, VSS1 = VSS2 = VSS3 = 0 V)
Parameter Logic supply voltage Driver supply voltage Temperature detection supply voltage Logic high level input voltage Logic low level input voltage IBS and R,/L high level input voltage IBS and R,/L low level input voltage Driver output current Symbol VDD1 VDD2 VDD3 VIH11 VIL11 VIH12 VIL12 IOH2 IOL2 MIN. 4.75 15 4.5 2.7 0 0.7 VDD1 0 5.0 TYP. 5.0 MAX. 5.25 70 5.5 VDD1 0.6 VDD1 0.2 VDD1 -24 +13 Unit V V V V V V V mA mA
18
Data Sheet S16472EJ1V0DS
PD16347
5 Electrical Characteristics (TA = 25C, VDD1 = VDD3 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = VSS3 = 0 V)
Parameter High level output voltage Symbol VOH21 VOH22 Low level output voltage VOL21 VOL22 Input leakage current II Conditions IOH2 = -0.52 mA IOH2 = -5.2 mA IOL2 = 1.6 mA IOL2 = 13 mA VI1 = VDD1 or VSS1, VI3 = VDD3 or VSS3 Logic high level input voltage Logic low level input voltage IBS and R,/L high level input voltage IBS and R,/L low level input voltage Detection temperature Detection temperature hysteresis width Temperature detection output (N-ch) characteristic Static current dissipation IDD11 VIH11 VIL11 VIH12 VIL12 TDET Thys RDET VSS3 to DET voltage, IO = 1 mA Logic, TA = -40 to +85C Logic, TA = 25C IDD12 Logic, TA = -40 to +85C Logic, TA = 25C IDD3 Temperature detection, TA = -40 to +85C Temperature detection, TA = 25C IDD2 Driver, TA = -40 to +85C Driver, TA = 25C 1000 100 800 1000 600 10 10
Note Note
MIN. 69 65
TYP.
MAX.
Unit V V
1.0 10 1.0
V V
A
VDD1 = 4.75 to 5.25 V VDD1 = 4.75 to 5.25 V
2.7 0 0.7 VDD1 0 110 10
VDD1 0.6 VDD1 0.2 VDD1 135 15 0.1 VDD3
V V V V C C V
A A
mA mA
1000
A A A A
Note When input all input high level (VIH = 2.7 V to VDD1, but both the R,/L and IBS pins are fixed to VI = VSS1 or VDD1)
Data Sheet S16472EJ1V0DS
19
PD16347
Switching Characteristics (TA = 25C, VDD1 = VDD3 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = VSS3 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 3.0 ns)
Parameter Propagation delay time Symbol tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ tPZH tPLZ tPZL Rise time tTLH tTLZ tTZH Fall time tTHL tTHZ tTZL Maximum clock frequency Input capacitance fMAX. CI O1 to O192 O1 to O192, RL = 10 k O1 to O192 O1 to O192, RL = 10 k Loading of data, duty = 50% 60 15 HZ O1 to O192, RL = 10 k /LBLK O1 to O192 /HBLK O1 to O192 Conditions /LE O1 to O192 MIN. TYP. MAX. 220 220 205 205 200 200 340 220 340 220 220 3 220 350 3 350 Unit ns ns ns ns ns ns ns ns ns ns ns
s
ns ns
s
ns MHz pF
20
Data Sheet S16472EJ1V0DS
PD16347
Timing Requirement (TA = 25C, VDD1 = 4.75 to 5.25 V, VSS1 = VSS2 = VSS3 = 0 V, tr = tf = 3.0 ns)
Parameter Clock pulse width Latch enable pulse width Blank pulse width HZ pulse width /CLR pulse width /CLR timing Data setup time Data hold time Latch enable Time Symbol PWCLK PW/LE PW/BLK PWHZ PW/CLR t/CLR tSETUP tHOLD t/LE11, t/LE21 t/LE12, t/LE22 /HBLK, /LBLK RL = 10 k Conditions MIN. 8 8 600 3.3 12 6 3 3 8 8 TYP. MAX. Unit ns ns ns
s
ns ns ns ns ns ns
5 Detection Temperature Hysteresis Width and Detection Output
VDD (Microcomputer side) 10 k "H" DET output to Thys MIN. Note Thys MAX.Note DET To a microcomputer
"L" TDET MIN. TDET MAX.
Tj (C) VSS3
Note Change of Thys linked with TDET's.
Data Sheet S16472EJ1V0DS
21
PD16347
Switching Characteristics Waveform (1/3)
1/fMAX. PWCLK PWCLK 3.3 V CLK 50% 50% 50% 0V tSETUP tHOLD 3.3 V An (Input) 50% 50% 0V
Remark The falling timing of CLK is at SDS = H (double edge).
3.3 V /LE 50% 50% 0V PW/LE t/LE11 t/LE21 PW/LE
3.3 V CLK (SDS = L) 50% t/LE12 CLK (SDS = H) t/LE22 3.3 V 50% 50% 0V 50% 0V
tPHL2
tTHL VOH2 10% VOL2
90% On
tPLH2 On 10%
tTLH VOH2 90% VOL2
22
Data Sheet S16472EJ1V0DS
PD16347
Switching Characteristics Waveform (2/3)
PW/BLK 3.3 V /LBLK 50% 50% 0V tPHL4 tPLH4 VOH2 10%
90% On
VOL2
PW/BLK 3.3 V /HBLK 50% 50% 0V tPHL3 tPLH3 90% 10% VOH2
On
VOL2
PW/CLR 3.3 V /CLR 50% 50% 0V t/CLR 3.3 V CLK (SDS = L) 50% 0V The rising (falling) edge of CLK for valid data 3.3 V 50% 0V
CLK (SDS = H)
Data Sheet S16472EJ1V0DS
23
PD16347
Switching Characteristics Waveform (3/3)
PWHZ
3.3 V
HZ
50%
50% 0V
tPLZ
tTLZ
tPZL
tTZL VO (H)
90% On 10%
90%
10% VOL2
VOH2 90% 90%
On 10% tPHZ tTHZ 10% tPZH tTZH VO (L)
24
Data Sheet S16472EJ1V0DS
PD16347
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S16472EJ1V0DS
25
PD16347
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E)
* The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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