 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MC54/74F175 QUAD D FLIP-FLOP The MC54/74F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where both true and complementary outputs are required and clock and clear inputs are common to all flip-flops. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs when LOW. * Four Edge-triggered D-type Inputs * Buffered Positive Edge-triggered Common Clock * Buffered Asynchronous Common Reset * True and Complementary Outputs * ESD > 4000 Volts 16 QUAD D FLIP-FLOP FASTTM SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 16 N SUFFIX PLASTIC CASE 648-08 1 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE Inputs @ tn, MR = H Dn L H Qn L H Outputs @ tn + 1 Qn H L ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 1 9 tn = Bit time before clock positive-going transition tn + 1 = Bit time after clock positive-going transition H = HIGH Voltage Level L = LOW Voltage Level 3 2 6 7 11 10 14 15 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 CP D0 D1 D2 D3 4 5 12 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-89 MC54/74F175 LOGIC DIAGRAM MR CP D3 D2 D1 D0 D CP CD Q Q D Q D Q D Q CP Q CD CP Q CD CP Q CD Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FUNCTIONAL DESCRIPTION The F175 consists of four edge-triggered D flop-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs, one setup time before, on the LOW-to-HIGH clock (CP) transition, causing individual Q and GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54, 74 54 74 IOH IOL Output Current -- High Output Current -- Low 54, 74 54, 74 Min 4.5 -55 0 Typ 5.0 25 25 Max 5.5 125 70 -1.0 20 mA mA Unit V C Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54, 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 3.4 3.4 0.35 0.5 20 100 IIL IOS ICC Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current -60 22.5 -0.6 -150 34 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A A mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = - 1.0 mA IOH = - 1.0 mA IOL = 20 mA VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V VOUT = 0 V Dn = MR = 4.5 V CP = VCC = MIN VCC = 4.50 V VCC = 4.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-90 MC54/74F175 AC CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL tPLH Parameter Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay MR to Qn Propagation Delay MR to Qn 4.0 6.5 8.5 4.0 10 4.0 9.0 ns Min 100 3.5 4.0 4.5 Typ 140 5.0 6.5 9.0 6.5 8.5 11.5 Max 54F TA = -55C to +125C VCC = 5.0 V 10% CL = 50 pF Min 100 3.5 4.0 4.5 8.5 10.5 15 Max 74F TA = 0C to +70C VCC = 5.0 V 10% CL = 50 pF Min 100 3.5 4.0 4.5 7.5 9.5 13 ns Max Unit MHz ns AC OPERATING REQUIREMENTS 54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP Min 3.0 3.0 1.0 1.0 4.0 5.0 5.0 5.0 Typ Max 54F TA = -55C to +125C VCC = 5.0 V 10% Min 3.0 3.0 1.0 1.0 4.0 5.0 5.0 5.0 Max 74F TA = 0C to +70C VCC = 5.0 V 10% Min 3.0 3.0 1.0 1.0 4.0 5.0 5.0 5.0 ns ns ns ns Max Unit FAST AND LS TTL DATA 4-91 |
Price & Availability of MC74F175D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |