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CXA2096N
Digital CCD Camera Head Amplifier
Description The CXA2096N is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, A/D sample and hold, blanking, A/D reference voltage, and an output driver. Features * High sensitivity made possible by a high-gain AGC amplifier * Blanking function provided for the purpose of calibrating the CCD output signal black level * Regulator output pin provided for A/D converter reference voltage * Built-in sample-and-hold circuits for camera signals required by external A/D converters Absolute Maximum Ratings * Supply voltage * Operating temperature * Storage temperature * Allowable power dissipation Operating Conditions Supply voltage 24 pin SSOP (Plastic)
VCC Topr Tstg PD
11 -20 to +75 -65 to +150 417
V C C mW
VCC1, 2, 3 3.0 to 3.6
V
Applications DVC/still cameras for consumer use Structure Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97449B8Y
CXA2096N
Block Diagram and Pin Configuration
CCDLEVEL
AGCCONT
ICONT
CLPDM
GND1
VCC2
VCC1
SHD
PIN
24
23
22
21
20
19
18
17
16
15
14
13
BUF
SH1
SH2 AGC DC SHIFT OB SW AGC CLP VREF CAM SH OFFSET VRT DRV VRT BLK SW VRB DRV VRB
CDS CLP2 DMSW2
SH3
DMSW1 CDS CLP1
POWER SAVE CONT
DRV
1
2
3
4
5
6
7
8
9
10
11
12
GND3
VRT
DRVOUT
-2-
OFFSET
CLPOB
PS
VCC3
VRB
N.C.
GND2
PBLK
XRS
AGCCLP
DIN
SHP
CXA2096N
Pin Description Pin No. 1 3 19 Symbol GND2 GND3 GND1 Pin voltage Equivalent circuit
(VCC1, 2, 3 = 3V) Description
GND
Ground.
60k 1.5V 30k 145
2
PS
VTH = 1.5V
2
Power saving mode.
10A 5k
IOFFSET 25A 0 to 50A
200A
25A
2k VRB = 1.35V 50A 50A
4
DRVOUT
VRB to VRB + 100mV
Driver output for A/D converter capable of DC coupling. Dynamic range = 1Vp-p.
145 4
ICONT 3.2 to 6.4mA
CAM signal 48
5 16 23
VCC3 VCC1 VCC2
VCC
Power supply.
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CXA2096N
Pin No. 6
Symbol N.C.
Pin voltage
Equivalent circuit
Description No connection; normally ground. 1.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F) 2.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7F)
200 16.5k 145
7
VRB
1.35V
1.35V
7
13.5k 110A 30k
30k 6.5k 145 2.35V 8 23.5k 55 55 220 200
8
VRT
2.35V
50k
50k
30k
2k
Controls the output offset. When 3V: VRB When 1.5V: VRB + 100mV When 0V (preset mode): VRB + 35mV
9
OFFSET
1.5 to 3V & 0V
1.85V 1.5k 3k 25k 30k VRB
50A 145 50A 50A 9
30k
Camera signal preblanking pulse input.
145
VTH = 1.85V 10 PBLK
Active: Low 1.85V
30k 10 30k 50A
Active when Low. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB.
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CXA2096N
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
40A
770A 145
VTH = 0.68V 11 XRS
0.68V
24k 11
Camera signal sample-and-hold pulse input.
7k Sampling 97
30k
VTH = 1.5V 12 CLPOB
1.5V
30k 145 12 30k
Active: Low
50A
Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier.
5k
5k
3k
145
13
AGCCLP
Approx. 1.3V
145 50k 3k
13
AGC clamp capacitor. (Recommended value: 0.1F)
3.3k 3.3k 145
AGC gain control.
14
14
AGCCONT
1.5 to 3.0V
3.4k 2.14V 3.4k
3.4k 2.29V
3.4k
When 1.5V: -1dB (Minimum gain) When 3.0V: 31.5dB (Maximum gain)
ICONT 300A 100A 300A 100A
200A
200A
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CXA2096N
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
100A
15
CCD signal black level of CCDLEVEL DIN input approx. 2.2V
15 500
Enables monitoring of the SH3 output camera signal.
340
17
SHP VTH = 0.65V
20A 36k
365A 145 17
Preset level sampleand-hold pulse input.
0.65V
18 10k
18
SHD
Sampling
Data level sampleand-hold pulse input.
VTH = 1.5V 20 CLPDM
1.5V
30k 145 20 30k
Clamp pulse used to clamp the dummy pixel portion of the input CCD signal.
Active: Low
50A
145 21
15A 15A 23k 14k 7k
2k
21 22
PIN DIN
Black level approx. 2.1V
22
145
CCD signal input.
2k
200A 50A
15k 145 2.25V 24 6k 45k 100A 6k
DRVOUT output waveform rise time control. When 1.5V: Maximum rise time When 3V: Minimum rise time
24
ICONT
1.5 to 3V
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CXA2096N
Electrical Characteristics Item Symbol Conditions AGCCONT = 1.5V, open between VRT and VRB PS = 3V, ICONT = 3V PS = 0V DIN = 1s, 20mVp-p pulse AGCCONT = 3V, ICONT = 3V DIN = 1s, 500mVp-p pulse AGCCONT = 1.5V, ICONT = 3V A CON max. - A CON min.
(Ta = 25C, VCC1, 2, 3 = 3V) Min. 25.1 0 28.5 -- 27.1 Typ. 37.1 1.8 31.3 -0.8 32.1 Max. Unit 49.0 4.2 -- 1.4 -- dB
PS = OFF Current (PS indicates IDC consump Power Save) -tion PS = ON IDP Maximum gain Minimum gain A CONT max. A CONT min.
mA
AGC
Range of gain AGC G variance Dynamic range maximum Dynamic range typical Offset high
AGCmax. AGCCONT = 3V D DRVOUT output signal at saturation level AGCTYP. D CAOF high CAOF low CAOF pre VRTO VRBO VR BLKOF SH3 D AGCCONT = 2V DRVOUT output signal at saturation level OFFSET = 1.5V OFFSET = 3.0V OFFSET = 0V With a 400 load With a 400 load With a 400 load BLKOF (PBLK = 3V) - BLKOF (PBLK = 0V) DIN = 1s, 1Vp-p pulse
800
970
-- mV
900
960
--
80 -- 25 2300 1300 950 -15 600
98 2 34 2340 1353 988 9 790
-- 5 40 2400 1400 1050 30 -- mV mV mV mV
DRV
Offset low Offset preset VRT DC level
REF
VRB DC level VRT - VRG
BLK SH3
Offset Dynamic range
-7-
CXA2096N
Electrical Characteristics Measurement Circuit
AC V2 V1 1.5 to 3V VCC2 3V C1 1F C2 1F
PL1
PL2
PL3 VCC1 3V
V3 1.5 to 3V
CCDLEVEL
AGCCONT
C3 0.1F
VCC2
PIN
24
23
22
21
20
19
18
17
16
15
14
13
BUF
SH1
SH2 AGC DC SHIFT OB SW AGC CLP VREF CAM SH OFFSET VRT DRV VRT BLK SW VRB DRV VRB
CDS CLP2 DMSW2
SH3
DMSW1 CDS CLP1
POWER SAVE CONT
DRV
1
2
3
4
5
6
7
8
9
10
11
12
VRT
OFFSET
L
SW1 H V6 3V
DRVOUT
R2 22 R3 10k V5 1.85V
VCC3 3V
R1 400
SW2
C5 4.7 C6 40pF
C4 4.7
V4 0 to 3V
CLPOB
VRB
PBLK
GND2
VCC3
GND3
XRS
N.C.
PS
AGCCLP
ICONT
CLPDM
GND1
VCC1
SHD
DIN
SHP
PL6
PL5
PL4
GND
SW1 H L
POWER SAVE OFF ON
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CXA2096N
Measurement Timing Chart
2s
1H
2.5V PL4 (CLPOB) 2s 1H GND
2.5V PL1 (CLPDM) GND
2.5V PL6 (PBLK) GND 1H V2 (DIN)
Different for each test
Equivalent to CCD signal black level PL2 (SHD) PL3 (SHP) PL5 (XRS) 2.5V GND
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CXA2096N
Application Circuit
CCD CLPDM VICONT 1.5 to 3V VCC SHD SHP VCC VAGCCONT 1.5 to 3V
CCDLEVEL
0.1F
VCC2
PIN
24
23
22
21
20
19
18
17
16
15
14
13
BUF
SH1
SH2 AGC DC SHIFT OB SW AGC CLP VREF CAM SH OFFSET VRT DRV VRT BLK SW VRB DRV VRB
CDS CLP2 DMSW2
SH3
DMSW1 CDS CLP1
POWER SAVE CONT
DRV
1
2
3
4
5
6
7
8
9
10
11
12
OFFSET
DRVOUT
22 3V
VCC 4.7 A/D IN VRB A/D VRT 4.7F GND VOFFSET PBLK 0 to 3V XRS CLPOB
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CLPOB
VRB
PBLK
GND2
VCC3
GND3
VRT
XRS
N.C.
PS
AGCCLP
ICONT
CLPDM
1F
1F
VCC1
DIN
AGCCONT
GND1
SHD
SHP
CXA2096N
Description of Operation Refer to the Block Diagram. Operating Conditions The camera signal processing system operates when PS is High. Timing Chart (when VCC = 3V)
Idle transfer interval
Signal interval Precharge level CCD output
OPB interval
Signal interval
Signal level SHP SHD SH1 output SH2 output SH3 output CLPDM (2 dummy bit portion during the idle transfer interval) AGC output SH3 output -SH2 output Basic black level [3] XRS CLPOB (2 during the OPB interval) 2s 2.1V [1] [2] 2.1V
2s Black level 0.65V
x (-N)
CAMSH output 0.65V PBLK (10 during the idle transfer interval)
10s
BLK SW output 1.35V [4]
DRVOUT output [5]
Approx. VRB + 35mV when OFFSET = 0V Approx. VRB + 100mV when OFFSET = 1.5V Applox. VRB when OFFSET = 3V
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CXA2096N
CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([1], [2]) of SH2 and SH3 in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from -1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to 3.0V. CAM SH: CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with VRB. ([4]) The signal is blanked when PBLK is Low. OFFSET: OFFSET controls the DRV output waveform black level offset. The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([5]) The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH and BLKSW. When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB. In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV. - 12 -
CXA2096N
DRV: DRV drives the external A/D. The current that flows to the last-stage amplifier in DRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. VRTDRV, VRBDRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB, supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltage. (VRB, VB and VCENT) POWER SAVE CONTROL: The PS pin is the power save pin; the operating state is enabled when this pin is High, while the power saving function operates when it is Low.
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CXA2096N
Characteristics Graphs
AGCCONT control supply voltage characteristics VAGCCONT vs. Gain
35 30 Tc = 27C VCC = 3V VCC = 3.15V VCC = 3.6V
OFFSET control supply voltage characteristics VOFFSET vs. OFFSET
140 Tc = 27C
120
100
Gain [dB] OFFSET [mV]
20
80
10
60
0 -4 1.5 2.0 2.5 VAGCCONT [V] 3.0 3.5
40
20 VCC = 3.6V VCC = 3V (VRB =) 0 0 1.0 2.0 VOFFSET [V] 3.0 3.5
AGCCONT control temperature characteristics AGCCONT vs. Gain
35 30 VCC = 3.0V Tc = -20C Tc = +27C Tc = +75C
OFFSET control temperature characteristics VOFFSET vs. OFFSET
VCC = 3.0V Tc = -20C Tc = +27C Tc = +75C 150
OFFSET [mV]
Gain [dB]
20
100
10 50 0 -4 1.5 2.0 2.5 3.0 AGCCONT [V] (VRB =) 0 0 1.0 2.0 3.0 VOFFSET [V]
- 14 -
CXA2096N
Maximum signal amplitude temperature characteristics (Max. gain) Tc vs. Vout
VCC = 3.0V, AGCCONT = 3.0V Input amplitude DIN = 28mVp-p Input amplitude DIN = 24mVp-p Input amplitude DIN = 21mVp-p
Maximum signal amplitude temperature characteristics (Min. gain) Tc vs. Vout
VCC = 3.0V, AGCCONT = 1.5V Input amplitude DIN = 870mVp-p Input amplitude DIN = 800mVp-p Input amplitude DIN = 750mVp-p Input amplitude DIN = 700mVp-p Input amplitude DIN = 600mVp-p
0.9 Gain temperature characteristics from -20 to +100C DIN = 28mVp-p +0 30.99 -0.23 dB 0.8
Vout [Vp-p]
1.0 30.99dB 30.99dB DIN = 24mVp-p +0 31.41 -0.38 dB 0.9 31.41dB 31.41dB DIN = 21mVp-p +0 31.45 -0.33 dB 0.8 31.45dB 31.45dB 31.12dB 30.76dB
Vout [Vp-p]
DIN = 870mVp-p
DIN = 800mVp-p 0.7 DIN = 750mVp-p DIN = 700mVp-p
31.03dB 0.6 DIN = 600mVp-p 0.53 -20
0.75 -20
0
50 Tc [C]
100
0
50 Tc [C]
100
VRT, VRB, VRT - VRB temperature characteristics Tc vs. VRT, VRB, VRT - VRB
2.4 VRT 2.2
VRT, VRB, VRT - VRB [V]
2.0 VCC = 3.0V 1.8 1.6 1.4 1.2 1.0 0.8 -20 VRT - VRB VRB
0
20 Tc [C]
40
60
80
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CXA2096N
Package Outline
Unit: mm
24PIN SSOP(PLASTIC)
+ 0.2 1.25 - 0.1 7.8 0.1 0.1 13
24
A
1 b
12
0.13 M B 0.65
5.6 0.1
+ 0.05 0.15 - 0.02
0.5 0.2
DETAIL B : SOLDER 0 to 10
(0.15)
0.1 0.1
(0.22)
b=0.22 0.03
DETAIL B : PALLADIUM
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
SSOP-24P-L01 SSOP024-P-0056
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 16 -
+ 0.03 0.15 - 0.01
+ 0.1 b=0.22 - 0.05
7.6 0.2

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