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LH5164ASH
FEATURES * 8,192 x 8 bit organization * Access time: 500 ns (MAX.) * Power consumption: Operating: 60 mW (MAX.) @ 3 V Standby: 3 W (MAX.) @ 70C @ 3 V 9 W (MAX.) @ 85C @ 3 V * Fully-static operation * Three-state outputs * Wide operating voltage range: 2.5 V to 5.5 V * TTL compatible I/O * Wide temp. range tOPR: -40 to +85C * Packages: 28-pin, 450-mil SOP 28-pin, 8 x 13 mm2 TSOP (Type I) DESCRIPTION
The LH5164ASH is a static RAM organized as 8,192 x 8 bits. It is fabricated using silicon-gate CMOS process technology. It is designed for 2.5 to 5.5 V low voltage operation and wide temperature range from -40 to +85C.
CMOS 64K (8K x 8) Static RAM
PIN CONNECTIONS
28-PIN SOP TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
5164ASH-1
Figure 1. Pin Connections for SOP Package
28-PIN TSOP (Type I)
TOP VIEW
OE A11 A9 A8 CE2 WE VCC NC A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2
5164ASH-8
Figure 2. Pin Connections for TSOP Package
1
LH5164ASH
CMOS 64K (8K x 8) Static RAM
A3
ROW DECODERS
ROW ADDRESS BUFFERS
7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A12 2
MEMORY ARRAY (256 x 256)
28 VCC 14 GND
I/O1 11 I/O2 12 I/O3 13 I/O4 15 I/O5 16 I/O6 17 I/O7 18 I/O8 19
I/O CIRCUITS DATA CONTROL COLUMN DECODERS
COLUMN ADDRESS BUFFERS
WE 27
OE 22 CE2 26 CE1 20 10 A0 9 A1 8 A2 21 A10 23 A11
5164ASH-2
Figure 3. LH5164ASH Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A12 CE1 - CE2 WE OE
Address inputs Chip Enable input Write Enable input Output Enable input
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
2
CMOS 64K (8K x 8) Static RAM
LH5164ASH
TRUTH TABLE
CE1 CE2 WE OE MODE I/O 1 - I/O8 SUPPLY CURRENT NOTE
H X L L L
NOTE: 1. X = H or L
X L H H H
X X L H H
X X X L H
Deselect Deselect Write Read Output disable
High-Z High-Z DIN DOUT High-Z
Standby (ISB ) Standby (ISB ) Operating (ICC) Operating (ICC) Operating (ICC)
1 1 1
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to V CC +0.3 -40 to +85 -65 to +150
V V C C
1 1, 2
NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width 50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = -40 to +85C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage (VCC = 2.5 to 4.5 V) Input voltage (VCC = 4.5 to 5.5 V)
VCC VIH VIL VIH VIL
2.5 VCC - 0.5 -0.3 2.2 -0.3
3.0
5.5 VCC + 0.3 0.2 VCC + 0.3 0.8
V V V V V
1
NOTE: 1. VIN (MIN.) = -3.0 V for pulse width 50 ns.
DC CHARACTERISTICS (TA = -40 to +85C, VCC = 2.5 to 5.5 V)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input leakage current Output leakage current
ILI ILO
Operating supply current
ICC
Standby current Output Low voltage Output High voltage
ISB ISB1 VOL VOH
VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 to VCC CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V tCYCLE = CE2 = VCC - 0.2 V, 500 ns Output open CE1 = 0.2 V, VIN = 0.2 V or tCYCLE = VCC - 0.2 V CE2 = VCC - 0.2 V, 1.0 s Output open CE1 = 0.2 V, VIN = 0.2 V or tCYCLE = VCC - 0.2 V CE2 = VCC - 0.2 V, 1.0 s Output open, VCC = 3.3 V TA +70C CE2 0.2 V or CE1 VCC - 0.2 V TA +85C CE1 = VIH or CE2 = VIL IOL = 500 A IOH = -500 A
-1.0 -1.0
1.0 1.0
A A
20
10
mA
8 1.0 3.0 5 0.5 VCC - 0.5
A mA V V
1
2
NOTES: 1. CE2 should be VCC - 0.2 V or 0.2 V when CE1 VCC - 0.2 V.
2. VOH is 4.5 V (Min.) at VCC > 5 V.
3
LH5164ASH
CMOS 64K (8K x 8) Static RAM
AC CHARACTERISTICS (1) READ CYCLE (TA = -40 to +85C, VCC = 2.5 to 5.5 V)
PARAMETER SYMBOL MIN. MAX. UNIT
Read cycle time Address access time Chip enable access time (CE1) (CE2)
tRC tAA tACE1 tACE2 tOE tOH (CE1) (CE2) (CE1) (CE2) tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
500 500 500 500 200 10 20 20 10 0 0 0 60 60 40
ns ns ns ns ns ns ns ns ns ns ns ns
Output enable access time Output hold time Chip enable to output in Low-Z
Output enable to output in Low-Z Chip enable to output in High-Z
Output disable to output in High-Z
(2) WRITE CYCLE (TA = -40 to +85C, VCC = 2.5 to 5.5 V)
PARAMETER SYMBOL MIN. MAX. UNIT
Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Output active from end of write WE to output in High-Z OE to output in High-Z
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ
500 250 250 100 150 50 100 0 20 0 0 60 40
ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude Input rise/fall time Timing reference level Output load conditions
NOTE: 1. Includes scope and jig capacitance.
0 to VCC 10 ns 1.5 V CL (100 pF) 1
CAPACITANCE (TA = 25C, f = 1MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance Input/output capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: This parameter is sampled and not production tested.
4
CMOS 64K (8K x 8) Static RAM
LH5164ASH
DATA RETENTION CHARACTERISTICS (TA = -40 to +85C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Data retention supply voltage
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3 V, CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 40C
2.0
5.5 0.2 0.4 0.6
V A A A ns ns
1
Data retention supply current
ICCDR tCDR tR
1
Chip disable to data retention Recovery time
0 tRC
2
NOTES: 1. CE2 should be VCCDR - 0.2 V or 0.2 V when CE1 VCCDR - 0.2 V. 2. t RC = Read cycle time
CE1 CONTROL (NOTE) VCC 2.5 V tCDR
DATA RETENTION MODE tR
VCC - 0.5 V VCCDR CE1 0V CE1 VCCDR - 0.2 V
CE2 CONTROL DATA RETENTION MODE VCC 2.5 V CE2 tCDR tR
VCCDR 0.2 V 0V CE2 0.2 V NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data retention.
5164ASH-6
Figure 4. Low Voltage Data Retention
5
LH5164ASH
CMOS 64K (8K x 8) Static RAM
tRC
A0 - A12 tAA tACE1 CE1 tLZ1 tACE2 CE2 tLZ2 tOE tOLZ OE tOHZ I/O1 - I/O8 NOTE: WE = 'HIGH.'
5164ASH-3
tHZ1
tHZ2
DATA VALID
tOH
Figure 5. Read Cycle
6
CMOS 64K (8K x 8) Static RAM
LH5164ASH
tWC
A0 - A12
OE tAW tCW (NOTE 2) CE1 tCW tWR (NOTE 4) tWR
CE2 tAS (NOTE 3) WE tOHZ (NOTE 5) DOUT HIGH-Z tDW DIN (NOTE 6)
DATA VALID
tWP (NOTE 1)
tWR
tDH
NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the output will remain high-impedance. 6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164ASH-4
Figure 6. Write Cycle 1 (OE Controlled)
7
LH5164ASH
CMOS 64K (8K x 8) Static RAM
tWC
A0 - A12 tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4)
CE2 tAS (NOTE 3) WE (NOTE 5) DOUT tWZ HIGH-Z tDW DIN (NOTE 7) tOW (NOTE 6) tDH
DATA VALID
tWP (NOTE 1)
tWR
OE = 'LOW' NOTES: 1. The writing occurs during an overlapping of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the output will remain high-impedance. 6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the output will remain high-impedance. 7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164ASH-5
Figure 7. Write Cycle 2 (OE Low Fixed)
8
CMOS 64K (8K x 8) Static RAM
LH5164ASH
PACKAGE DIAGRAMS
28SOP (SOP028-P-0450)
1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457]
0.50 [0.020] 0.30 [0.012]
28
10.60 [0.417]
1 18.20 [0.717] 17.80 [0.701]
14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28SOP
28-pin, 450-mil SOP
9
LH5164ASH
CMOS 64K (8K x 8) Static RAM
28TSOP (TSOP028-P-0813)
0.28 [0.011] 0.12 [0.005] 28 0.55 [0.022] TYP. 15
12.00 [0.472] 11.60 [0.457]
13.70 [0.539] 13.10 [0.516]
12.60 [0.496] 12.20 [0.480]
1 8.20 [0.323] 7.80 [0.307]
14 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000]
28TSOP
DETAIL
0 - 10
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28-pin, 8 x 13 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5164ASH Device Type X Package
N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 64K (8K x 8) Static RAM H = -40C to +85C Operation S = 3 V Operation
Example: LH5164ASHN (CMOS 64K (8K x 8) Static RAM, 28-pin, 450-mil SOP)
5164ASH-7
10

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