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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
DESCRIPTION
The Philips Semiconductors SCN2651 PCI is a universal synchronous/asynchronous data communications controller chip designed for microcomputer systems. It interfaces directly to the Philips Semiconductors SCN2650 microprocessor and may be used in a polled or interrupt driven system environment. The SCN2651 accepts programmed instructions from the microprocessor and supports many serial data communication disciplines, synchronous and asynchronous, in the full or half-duplex mode. The PCI serializes parallel data characters received from the microprocessor for transmission. Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer. The SCN2651 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode. The PCI is constructed using Philips Semiconductors n-channel silicon gate depletion load technology and is packaged in a 28-pin DIP.
PIN CONFIGURATIONS
D2 D3 RxD GND D4 D5 D6 D7 TxC A1 CE
1 2 3 4 5 6 7 DIP 8 9 10 11
28 D1 27 D0 26 VCC 25 RxC 24 DTR 23 RTS 22 DSR 21 RESET 20 BRCLK 19 TxD 18 TxEMT/DSCHG 17 CTS 16 DCD 15 TxRDY TOP VIEW
A0 12 R/W 13
RxRDY 14
FEATURES
* Synchronous operation
- 5- to 8-bit characters - Single or double SYN operation - Internal character synchronization - Transparent or non-transparent mode - Automatic SYN or DLE-SYN insertion - SYN or DLE stripping - Odd, even, or no parity - Local or remote maintenance loopback mode - Baud rate: DC to 1Mbps (1X clock)
SD00049
OTHER FEATURES
* Asynchronous operation
- 5- to 8-bit characters - 1, 1-1/2 or 2 stop bits - Odd, even, or no parity - Parity, overrun and framing error detection - Line break detection and generation - False start bit detection - Automatic serial echo mode - Local or remote maintenance loopback mode - Baud rate: DC to 1Mbps (1X clock) DC to 62.5kbps (16X clock) DC to 15.625kbps (64X clock)
* Internal or external baud rate clock * 16 internal rates - 50 to 19,200 baud * Double buffered transmitter and receiver * Full or half duplex operation * TTL compatible inputs and outputs * Single 5V power supply * No system clock required * 28-pin dual in-line package
APPLICATIONS
* Intelligent terminals * Network processors * Front-end processors * Remote data concentrators * Computer to computer links * Serial peripherals
ORDERING CODE
VCC = 5V +5% PACKAGES Commercial 0C to +70C 28-Pin Plastic Dual In-Line Package (DIP) SCN2651CC1N28 Industrial -40C to +85C Not available SOT117-2 DWG #
1994 Apr 27
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853-1067 12793
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
BLOCK DIAGRAM
DATA BUS D0-D7 (27, 28, 1, 2, 5, 6, 7, 8)
DATA BUS BUFFER
SYN/DLE CONTROL SYN 1 REGISTER SYN 2 REGISTER DLE REGISTER
RESET A0 A1 R/W CE
(21) (12) (10) (13) (11)
OPERATION CONTROL MODE REGISTER 1 MODE REGISTER 2 COMMAND REGISTER STATUS REGISTER TRANSMITTER TRANSMIT DATA HOLDING REGISTER TRANSMIT SHIFT REGISTER (19) TxD (15) TxRDY
BRCLK
(20) BAUD RATE GENERATOR AND CLOCK CONTROL
TxC
(9)
RECEIVER RECEIVE SHIFT REGISTER
(14)
RxRDY
RxC
(25)
DSR DCD CTS RTS DTR TxEMT/* DSCHG
(22) (16) (17) (23) (24) (18) MODEM CONTROL
RECEIVE DATA HOLDING REGISTER
(3)
RxD
SD00050
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG Storage temperature All voltages with respect to ground3 PARAMETER Operating ambient temperature2 RATING Note 4 -65 to +150 -0.5 to +6.0 UNIT C C V
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.
CAPACITANCE
TA = 25C, VCC = 0V SYMBOL Capacitance CIN COUT CI/O Input Output Input/Output fC = 1MHz Unmeasured pins tied to ground 20 20 20 pF pF pF PARAMETER TEST CONDITIONS LIMITS Min Typ Max UNIT
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
DC ELECTRICAL CHARACTERISTICS1, 2, 3
SYMBOL Input voltage VIL VIH VOL VOH IIL ILH ILL Low High Low High Input leakage current Data bus high Data bus low IOL = 1.6mA IOH = -100A VIN = 0 to 5.25V VO = 4.0V VO = 0.45V 2.0 0.8 V V V V A A A PARAMETER TEST CONDITIONS LIMITS Min Typ Max UNIT
Output voltage 2.4 -10 -10 -10 0.4 10 10 10
3-State output leakage current
ICC Power supply current 150 mA NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBRL) and at 0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V. 3. Typical values are at +25C, typical supply voltages and typical processing parameters.
AC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS SYMBOL Pulse width tRES tCE tAS tAH tCS tCH tDS tDH tRXS tRXH tDD tDF tCED fBRG fR/T6 Clock width tBRH5 tBRL5 tR/TH tR/TL6 tTXD tTCS Baud rate high Baud rate low TxC or RxC high TxC or RxC low TxD delay from falling edge of TxC Skew between TxD changing and falling edge of TxC output4 CL = 100pF CL = 100pF 70 70 500 500 650 0 ns ns ns ns ns ns Reset Chip enable Address setup Address hold R/W control setup R/W control hold Data setup for write Data hold for write RX data setup RX data hold Data delay time for read Data bus floating time for read CE to CE delay CL = 100pF CL = 100pF 1000 300 20 20 20 20 225 0 300 350 250 150 700 ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER TEST CONDITIONS Min Typ Max UNIT
Set-up and hold time
Input clock frequency Baud rate generator TxC or RxC 1.0 dc 5.0688 5.0738 1.0 MHz MHz
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBRL) and at 0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V. 3. Typical values are at +25C, typical supply voltages and typical processing parameters. 4. Parameter applies when internal transmitter clock is used. 5. Under test conditions of 5.0688MHz, fBRG, tBRH, and tBRL measured at VIH and VIL respectively. 6. tR/T and tR/TL shown for all modes except local loopback. For local loopback mode fR/T = 0.7MHz and tR/TL = 700ns min.
1994 Apr 27
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
PIN DESCRIPTION
Pin No. 27, 28, 1, 2, 5-8 21 12, 10 13 11 22 24 23 17 16 18 9 25 19 3 15 14 20 26 4 Symbol D0 - D7 RESET A0-A1 R/W CE DSR DTR RTS CTS DCD TxEMT/DSCHG TxC RxC TxD RxD TxRDY RxRDY BRCLK VCC GND 8-Bit data bus Reset Internal register select lines Read or write command Chip enable input Data set ready Data terminal ready Request to send Clear to send Data carrier detected Transmitter empty or data set change Transmitter clock Receiver clock Transmitter data Receiver data Transmitter ready Receiver ready Baud rate generator clock +5V supply Ground Name and Function Type I/O I I I I I O O I I O I/O I/O O I O O I I I the data bus and contains mode registers 1 and 2, the command register, and the status register. Details of register addressing and protocol are presented in the PCI programming section of this data sheet.
Table 1.
Baud Rate
Baud Rate Generator Characteristics Crystal Frequency = 5.0688MHz
Theoretical Frequency 16X Clock Actual Frequency 16X Clock Percent Error Divisor
Timing
The PCI contains a baud rate generator (BRG) which is programmable to accept external transmit or receive clocks or to divide an external clock to perform data communications. The unit can generate 16 commonly used baud rates, any one of which can be selected for full-duplex operation. See Table 1.
50 0.8kHz 0.8kHz - 6336 75 1.2 1.2 - 4224 110 1.76 1.76 - 2880 134.5 2.152 2.1523 0.016 2355 150 2.4 2.4 - 2112 300 4.8 4.8 - 1056 600 9.6 9.6 - 528 1200 19.2 19.2 - 264 1800 28.8 28.8 - 176 2000 32.0 32.081 0.253 158 2400 38.4 38.4 - 132 NOTE: *Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz. 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X.
Receiver
The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an "assembled" character to the CPU.
Transmitter
The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of data on the TxD output pin.
BLOCK DIAGRAM
The PCI consists of six major sections. These are the transmitter, receiver, timing, operation control, modem control and SYN/DLE control. These sections communicate with each other via an internal data bus and an internal control bus. The internal data bus interfaces to the microprocessor data bus via a data bus buffer.
Modem Control
The modem control section provides interfacing for three input signals and three output signals used for "handshaking" and status indication between the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the CPU. These registers are used in the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency.
Operation Control
This functional block stores configuration and operation commands from the CPU and generates appropriate signals to various internal sections to control the overall device operation. It contains read and write circuits to permit communications with the microprocessor via
1994 Apr 27
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
INTERFACE SIGNALS
The PCI interface signals can be grouped into two types: the CPU-related signals (shown in Table 2), which interface the SCN2651 to the microprocessor system, and the device-related signals (shown in Table 3), which are used to interface to the communications device or system.
OPERATION
The functional operation of the SCN2651 is programmed by a set of control words supplied by the CPU. These control words specify items such as synchronous or asynchronous mode, baud rate, number of bits per character, etc. The programming procedure is described in the PCI programming section of the data sheet. After programming, the PCI is ready to perform the desired communications functions. The receiver performs serial to parallel conversion of data received from a modem or equivalent device. The transmitter converts parallel data received from the CPU to a serial bit stream. These actions are accomplished within the framework specified by the control words.
been assembled. The data is then transferred to the receive data holding register, the RxRDY bit in the status register is set, and the RxRDY output is asserted. If the character length is less than 8 bits, the high order unused bits in the holding register are set to zero. The parity error, framing error, and overrun error status bits are strobed into the status register on the positive going edge of RxC corresponding to the received character boundary. If a break condition is detected (RxD is low for the entire character as well as the stop bit[s]), only one character consisting of all zeros (with the FE status bit set) will be transferred to the holding register. The RxD input must return to a high condition before a search for the next start bit begins. When the PCI is initialized into the synchronous mode, the receiver first enters the hunt mode on a 0 to 1 transition of RxEN (CR2). In this mode, as data is shifted into the receiver shift register a bit at a time, the contents of the register are compared to the contents of the SYN1 register. If the two are not equal, the next bit is shifted in and the comparison is repeated. When the two registers match, the hunt mode is terminated and character assembly mode begins. If single SYN operation is programmed, the SYN detect status bit is set. If double SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN detect bit to be set. Otherwise, the PCI returns to the hunt mode. (Note that the sequence SYN1-SYN1-SYN2 will not achieve synchronization.) When synchronization has been achieved, the PCI continues to assemble characters and transfer them to the holding register, setting the RxRDY status bit and asserting the RxRDY output each time a character is transferred. The PE and OE status bits are set as appropriate. Further receipt of the appropriate SYN sequence sets the SYN detect status bit. If the SYN stripping mode is
Receiver
The SCN2651 is conditioned to receive data when the DCD input is low and the RxEN bit in the command register is true. In the asynchronous mode, the receiver looks for a high to low transition of the start bit on the RxD input line. If a transition is detected, the state of the RxD line is sampled again after a delay of one-half of a bit-time. If RxD is now high, the search for a valid start bit is begun again. If RxD is still low, a valid start bit is assumed and the receiver continues to sample the input line at one bit time intervals until the proper number of data bits, the parity bit, and one stop bit(s) have
Table 2.
PIN NAME VCC GND RESET A1 - A0 R/W CE
CPU-Related Signals
PIN NO. 26 4 21 10, 12 13 11 8, 7, 6, 5, 2, 1, 28, 27 15 INPUT/ OUTPUT I I I I I I +5V supply input Ground A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any device activity and clears the mode, command and status registers. The device assumes the idle state and remains there until initialized with the appropriate control words. Address lines used to select internal PCI registers. Read command when low, write command when high. Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the operation specified by the RW, A1 and A0 inputs should be performed. When high, places the D0-D7 lines in the 3-State condition. 8-bit, three-state data bus used to transfer commands, data and status between PCI and the CPU. D0 is the least significant bit, D7 the most significant bit. This output is the complement of status register bit SR0. When low, it indicates that the transmit data holding register (THR) is ready to accept a data character from the CPU. It goes high when the data character is loaded. This output is valid only when the transmitter is enabled. It is an open drain output which can be used as an interrupt to the CPU. This output is the complement of status register bit SR1. When low, it indicates that the receive data holding register (RHR) has a character ready for input to the CPU. It goes high when the RHR is read by the CPU, and also when the receiver is disabled. It is an open drain output which can be used as an interrupt to the CPU. This output is the complement of status register bit SR2. When low, it indicates that the transmitter has completed serialization of the last character loaded by the CPU, or that a change of state of the DSR or DCD inputs has occurred. This output goes high when the status register is read by the CPU, if the TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high. It is an open drain output which can be used as an interrupt to the CPU. FUNCTION
D7 - D0
I/O
TxRDY
O
RxRDY
14
O
TxEMT/DS CHG
18
O
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
Table 3.
PIN NAME BRCLK
Device-Related Signals
PIN NO. 20 INPUT/O UTPUT I FUNCTION 5.0688MHz clock input to the internal baud rate generator. Not required if external receiver and transmitter clocks are used. Receiver clock. If external receiver clock is programmed, this input controls the rate at which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode register 1. Data are sampled on the rising edge of the clock. If internal receiver clock is programmed, this pin becomes an output at 1X the programmed baud rate.* Transmitter clock. If external transmitter clock is programmed, this input controls the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode register 1. The transmitted data changes on the falling edge of the clock. If internal transmitter clock is programmed, the pin becomes an output at 1X the programmed baud rate.* Serial data input to the receiver. "Mark" is high, "Space" is low. Serial data output from the transmitter. "Mark" is high, "space" is low. Held in mark condition when the transmitter is disabled. General purpose input which can be used for data set ready or ring indicator condition. Its complement appears as status register bit SR7. Causes a low output on TxEMT/DSCHG when its state changes. Data carrier detect input. Must be low in order for the receiver to operate. Its complement appears as status register bit SR6. Causes a low output on TxEMT/DSCHG when its state changes. Clear to send input. Must be low in order for the transmitter to operate. If it goes high during transmission, the character in the transmit shift register will be transmitted before termination. General purpose output which is the complement of command register bit CR1. Normally used to indicate data terminal ready. General purpose output which is the complement of command register bit CR5. Normally used to indicate request to send.
RxC
25
I/O
TxC RxD TxD DSR DCD CTS DTR RTS
9 3 19 22 16 17 24 23
I/O I O I I I O O
NOTE: *RxC and TxC outputs have short circuit protection max. CL = 100pF commanded, SYN characters are not transferred to the Holding Register. Note that the SYN characters used to establish initial synchronization are not transferred to the holding register in any case. send a new character to the PCI by the time the transmitter has completed sending the previous character. Since synchronous communication does not allow gaps between characters, the PCI asserts TxEMT and automatically "fills" the gap by transmitting SYN1s, SYN1-SYN2 doublets, or DLE-SYN1 doublets, depending on the state of MR16 and MR17. Normal transmission of the message resumes when a new character is available in the transmit data holding register. If the send DLE bit in the command register is true, the DLE character is automatically transmitted prior to transmission of the message character in the THR.
Transmitter
The PCI is conditioned to transmit data when the CTS input is Low and the TxEN command register bit is set. The SCN2651 indicates to the CPU that it can accept a character for transmission by setting the TxRDY status bit and asserting the TxRDY output. When the CPU writes a character into the transmit data holding register, these conditions are negated. Data is transferred from the holding register to the transmit shift register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again. Thus, one full character time of buffering is provided. In the asynchronous mode, the transmitter automatically sends a start bit followed by the programmed number of data bits, the least significant bit being sent first. It then appends an optional odd or even parity bit and the programmed number of stop bits. If, following transmission of the data bits, a new character is not available in the transmit holding register, the TxD output remains in the marking (high) condition and the TxEMT/DSCHG output and its corresponding status bit are asserted. Transmission resumes when the CPU loads a new character into the holding register. The transmitter can be forced to output a continuous low (BREAK) condition by setting the send break command bit high. In the synchronous mode, when the SCN2651 is initially conditioned to transmit, the TxD output remains high and the TxRDY condition is asserted until the first character to be transmitted (usually a SYN character) is loaded by the CPU. Subsequent to this, a continuous stream of characters is transmitted. No extra bits (other than parity, if commanded) are generated by the PCI unless the CPU fails to
PCI PROGRAMMING
Prior to initiating data communications, the SCN2651 operational mode must be programmed by performing write operations to the mode and command registers. In addition, if synchronous operation is programmed, the appropriate SYN/DLE registers must be loaded. The PCI can be reconfigured at any time during program execution. However, if the change has an effect on the reception of a character the receiver should be disabled. Alternatively if the change is made 1 1/2 RxC periods after RxRDY goes active it will affect the next character assembly. A flowchart of the initialization process appears in Figure 1. The internal registers of the PCI are accessed by applying specific signals to the CE, R/W, A1 and A0 inputs. The conditions necessary to address each register are shown in Table 4. The SYN1, SYN2, and DLE registers are accessed by performing write operations with the conditions A1 = 0, A0 = 1, and R/W = 1. The first operation loads the SYN1 register. The next loads the SYN2 register, and the third loads the DLE register. Reading or loading the mode registers is done in a similar manner. The first write (or read) operation addresses mode register 1, and a subsequent operation addresses mode register 2. If more than the 6
1994 Apr 27
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
required number of accesses are made, the internal sequencer recycles to point at the first register. The pointers are reset to SYN1 register and mode register 1 by a RESET input or by performing a "read command register" operation, but are unaffected by any other read or write operation. The SCN2651 register formats are summarized in Tables 5, 6, 7 and 8. Mode registers 1 and 2 define the general operational characteristics of the PCI, while the command register controls the operation within this basic framework. The PCI indicates its status in the status register. These registers are cleared when a RESET input is applied.
0
1
1
1
Write command register
NOTE: See AC Characteristics section for timing requirements. MR25 and MR24 select either the BRG or the external inputs TxC and RxC as the clock source for the transmitter and receiver, respectively. If the BRG clock is selected, the baud rate factor in asynchronous mode is 16X regardless of the factor selected by MR11 and MR10. In addition, the corresponding clock pin provides an output at 1X the baud rate.
INITIAL RESET
Mode Register 1 (MR1)
Table 5 illustrates mode register 1. Bits MR11 and MR10 select the communication format and baud rate multiplier. 00 specifies synchronous mode and 1X multiplier. 1X, 16X, and 64X multipliers are programmable for asynchronous format. However, the multiplier in asynchronous format applies only if the external clock input option is selected by MR24 or MR25. MR13 and MR12 select a character length of 5, 6, 7, or 8 bits. The character length does not include the parity bit, if programmed, and does not include the start and stop bits in asynchronous mode. MR14 controls parity generation. If enabled, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. MR15 selects odd or even parity when parity is enabled by MR14. In asynchronous mode, MR17 and MR16 select character framing of 1, 1.5, or 2 stop bits. (If 1X baud rate is programmed, 1.5 stop bits default to 1 stop bit on transmit.) In synchronous mode, MR17 controls the number of SYN characters used to establish synchronization and for character fill when the transmitter is idle. SYN1 alone is used if MR17 = 1, and SYN1-SYN2 is used when MR17 = 0. If the transparent mode is specified by MR16, DLE-SYN1 is used for character fill and SYN detect, but he normal synchronization sequence is used. Also DLE stripping and DLE detect (with MR14 = 0) are enabled.
N LOAD MODE REGISTER 1 NOTE: Mode Register 1 must be written before 2 can be written. Mode Register 2 need not be programmed if external clocks are used.
LOAD MODE REGISTER 2
SYNCHRONOUS? Y LOAD SYN 1 REGISTER
NOTE: SYN1 Register must be written before SYN2 can be written, and SYN2 before DLE can be written.
DOUBLE SYNC? Y LOAD SYN 2 REGISTER
N
Y
TRANSPARENT MODE? N
TRANSPARENT MODE? Y LOAD DLE REGISTER
N
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23, MR22, MR21, and MR20 control the frequency of the internal baud rate generator (BRG). Sixteen rates are selectable. When driven by a 5.0688MHz input at the BRCLK input (Pin 20), the BRG output has zero error except at 134.5 2000, and 19,200 baud, which have errors of +0.016%, +0.235%, and +3.125% respectively.
LOAD COMMAND REGISTER
Table 4. SCN2651 Register Addressing
CE 1 0 0 0 0 0 0 0 A1 X 0 0 0 0 1 1 1 A0 X 0 0 1 1 0 0 1 R/W X 0 1 0 1 0 1 0 FUNCTION 3-State data bus Read receive holding register Write transmit holding register Read status register Write SYN1/SYN2/DLE registers Read mode registers 1/2 Write mode registers 1/2 Read command register
N
OPERATE
RECONFIGURE? Y DISABLE RCVR AND XMTR
SD00051
Figure 1. SCN2651 Initialization Flowchart
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
Table 5.
MR17
Mode Register 1 (MR1)
MR16 MR15 Parity Type MR14 Parity Control 0 = Disabled 1 = Enabled MR13 MR12 MR11 MR10 Character Length 00 = 5 Bits 01 = 6 Bits 10 = 7 Bits 11 = 8 Bits Mode and Baud Rate Factor 00 = Synchronous 1X rate 01 = Asynchronous 1X rate 10 = Asynchronous 16X rate 11 = Asynchronous 64X rate
Async: Stop bit length 00 = Invalid 01 = 1 Stop bit 10 = 1 1/2 Stop bits 11 = 2 Stop bits Sync: Number of SYN char 0 = Double SYN 1 = Single SYN Sync: Transparency control 0 = Normal 1 = Transparent
0 = Odd 1 = Even
NOTE: Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be selected (MR11, MR10) in any case.
Table 6.
MR27
Mode Register 2 (MR2)
MR26 MR25 Transmitter Clock Not used 0 = External 1 = Internal MR24 Receiver Clock 0= External 1 = Internal 0000 = 50 Baud 0001 = 75 0010 = 110 0011 = 134.5 0100 = 150 0101 = 300 0110 = 600 0111 = 1200 MR23 MR22 MR21 MR20 Baud Rate Selection 1000 = 1800 Baud 1001 = 2000 1010 = 2400 1011 = 3600 1100 = 4800 1101 = 7200 1110 = 9600 1111 = 19,200
Table 7.
CR7
Command Register (CR)
CR6 CR5 Request to Send 0 = Force RTS output high 1 = Force RTS output low CR4 Reset Error 0 = Normal 1 = Reset error flag in status reg (FE, OE, PE/DLE DETECT) Async: Force Break 0 = Normal 1 = Force break Sync Send DLE 0 = Normal 1 = Send DLE Bits CR1 (DTR) and CR5 (RTS) control the DTR and RTS outputs. Data at the outputs is the logical complement of the register data. In asynchronous mode, setting CR3 will force and hold the TxD output low (spacing condition) at the end of the current transmitted character. Normal operation resumes when CR3 is cleared. The TxD line will go high for at least one bit time before beginning transmission of the next character in the transmit data holding register. In synchronous mode, setting CR3 causes the transmission of the DLE register contents prior to sending the character in the transmit data holding register. CR3 should be reset in response to the next TxRDY. CR3 CR2 Receive Control (RxEN) 0 = Disable 1 = Enable CR1 Data Terminal Ready 0 = Force DTR output high 1 = Force DTR output low CR0 Transmit Control (TxEN) 0 = Disable 1 = Enable
Operating Mode 00 = Normal operation 01 = Async: automatic echo mode Sync: SYN and/or DLE stripping mode 10 = Local Loopback 11 = Remote Loopback
Command Register (CR)
Table 7 illustrates the command register. Bits CR0 (TxEN) and CR2 (RxEN) enable or disable the transmitter and receiver respectively. A 0 to 1 transition of CR2 forces start bit search (async mode) or hunt mode (sync mode) on the second RxC rising edge. Disabling the receiver causes RxRDY to go high (inactive). If the transmitter is disabled, it will complete the transmission of the character in the transmit shift register (if any) prior to terminating operation. The TxD output will then remain in the marking state (high) while TxRDY and TxEMT will go high (inactive). If the receiver is disabled, it will terminate operation immediately. Any character being assembled will be neglected.
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Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
Table 8.
SR7 Data Set Ready
Status Register (SR)
SR6 Data Carrier Detect 0 = DCD input is high 1 = DCD input is low SR5 FE/SYN Detect Async: 0 = Normal 1 = Framing ERROR Sync: 0 = Normal 1 = SYN char detected SR4 Overrun 0 = Normal 1 = Overrun error SR3 PE/DLE Detect Async: 0 = Normal 1 = Parity error Sync: 0 = Normal 1 = Parity error or DLE char received SR2 TxEMT/ DSCHG 0 = Normal 1 = Change in DSR or DCD, or transmit shift register is empty SR1 RxRDY 0 = Receive holding register empty 1 = Receive holding register has data SR0 TxRDY 0 = Transmit holding register busy 1 = Transmit holding register empty
0 = DSR input is high 1 = DSR input is low
Setting CR4 causes the error flags in the status register (SR3, SR4, and SR5) to be cleared. This is a one time command. There is no internal latch for this bit. The PCI can operate in one of four submodes within each major mode (synchronous or asynchronous). The operational submode is determined by CR7 and CR6. CR7 - CR6 = 00 is the normal mode, with the transmitter and receiver operating independently in accordance with the mode and status register instructions. In asynchronous mode, CR7 - CR6 = 01 places the PCI in the automatic echo mode. Clocked, regenerated received data are automatically directed to the TxD line while normal receiver operation continues. The receiver must be enabled (CR2 = 1), but the transmitter need not be enabled. CPU to receiver communications continues normally, but the CPU to transmitter link is disabled. Only the first character of a break condition is echoed. The TxD output will go high until the next valid start is detected. The following conditions are true while in automatic echo mode: 1. Data assembled by the receiver are automatically placed in the transmit holding register and retransmitted by the transmitter on the TxD output. 2. The transmitter is clocked by the receive clock. 3. TxRDY output = 1. 4. The TxEMT/DSCHG pin will reflect only the data set change condition. 5. The TxEN command (CR0) is ignored. In synchronous mode, CR7 - CR6 = 01 places the PCI in the automatic SYN/DLE stripping mode. The exact action taken depends on the setting of bits MR17 and MR16: 1. In the non-transparent, single SYN mode (MR17 - MR16 = 10), characters in the data stream matching SYN1 are not transferred to the receive data holding register (RHR). 2. In the non-transparent, double SYN mode (MR17 - MR16 = 00), characters in the data stream matching SYN1, or SYN2 if immediately preceded by SYN1, are not transferred the RHR. However, only the first SYN1 of an SYN1 - SYN1 pair is stripped. 3. In transparent mode (MR16 = 1), character in the data stream matching DLE, or SYN1 if immediately preceded by DLE, are not transferred to the RHR. However, only the first DLE of a DLE- DLE pair is stripped. Note that automatic stripping mode does not affect the setting of the DLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic submodes can also be configured. In local loopback mode (CR7 - CR6 = 10), the following loops are connected internally: 1. The transmitter output is connected to the receiver input. 2. DTR is connected to DCD and RTS is connected to CTS. 3. The receiver is clocked by the transmit clock. 4. The DTR, RTS and TxD outputs are held high. 5. The CTS, DCD, DSR and RxD inputs are ignored. Additional requirements to operate in the local loopback mode are that CR0 (TxEN), CR1 (DTR), and CR5 (RTS) must be set to 1. CR2 (RxEN) is ignored by the PCI. The second diagnostic mode is the remote loopback mode (CR7 - CR6 = 11). In this mode: 1. Data assembled by the receiver are automatically placed in the transmit holding register and retransmitted by the transmitter on the TxD output. 2. The transmitter is clocked by the receive clock. 3. No data is sent to the local CPU, but he error status conditions (PE, OE, FE) are set. 4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held high. 5. CR0 (TxEN) is ignored. 6. All other signals operate normally.
Status Register
The data contained in the status register (as shown in Table 8) indicate receiver and transmitter conditions and modem/data set status. SR0 is the transmitter ready (TxRDY) status bit. It, and its corresponding output, are valid only when the transmitter is enabled. If equal to 0, it indicates that the transmit data holding register has been loaded by the CPU and the data has not been transferred to the transmit shift register. If set equal to 1, it indicates that the Holding Register is ready to accept data from the CPU. This bit is initially set when the transmitter is enabled by CR0, unless a character has previously been loaded into the holding register. It is not set when the automatic echo or remote loopback modes are programmed. When this bit is set, the TxRDY output pin is low. In the automatic echo and remote loopback modes, the output is held high. SR1, the receiver ready (RxRDY) status bit, indicates the condition of the receive data holding register. If set, it indicates that a 9
1994 Apr 27
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
character has been loaded into the holding register from the receive shift register and is ready to be read by the CPU. If equal to zero, there is no new character in the holding register. This bit is cleared when the CPU reads the receive data holding register or when the receiver is disabled by CR2. When set, the RxRDY output is low. The TxEMT/DSCHG bit, SR2, when set, indicates either a change of state of the DSR or DCD inputs or that the transmit shift register has completed transmission of a character and no new character has been loaded into the transmit data holding register. Note that in synchronous mode this bit will be set even though the appropriate "fill" character is transmitted. TxEMT will not go active until at least one character has been transmitted. It is cleared by loading the transmit data holding register. The DSCHG condition is enabled when TxEN = 1 or RxEN = 1. If the status register is read twice and SR2 = 1 while SR6 and SR7 remain unchanged, then a TxEMT condition exists. It is cleared when the status register is read by the CPU. When SR2 is set, the TxEMT/DSCHG output is low. SR3, when set, indicates a received parity error when parity is enabled by MR14. In synchronous transparent mode (MR16 = 1), with parity disabled, it indicates that a character matching the DLE register has been received. However, only the first DLE of two successive DLEs will set SR3. This bit is cleared when the receiver is disabled and by the reset error command, CR4.
The overrun error status bit, SR4, indicates that the previous character loaded into the receive holding register was not read by the CPU at the time a new received character was transferred into it. This bit is cleared when the receiver is disabled and by the reset error command, CR4. In asynchronous mode, bit SR5 signifies that the received character was not framed by the programmed number of stop bits. (If 1.5 stop bits are programmed, only the first stop bit is checked.) If RHR = 0 when SR5 = 1, a break condition is present. In synchronous non-transparent mode (MR16 = 0), it indicates receipt of the SYN1 character in single SYN mode or the SYN1 - SYN2 pair in double SYN mode. In synchronous transparent mode (MR16 = 1), this bit is set upon detection of the initial synchronizing characters (SYN1 or SYN1 - SYN2) and, after synchronization has been achieved, when a DLE-SYN1 pair is received. The bit is reset when the receiver is disabled, when the reset error command is given in asynchronous mode, and when the status register is read by the CPU in the synchronous mode. SR6 and SR7 reflect the conditions of the DCD and DSR inputs respectively. A low input sets its corresponding status bit and a high input clears it.
1994 Apr 27
10
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
TIMING DIAGRAMS
CLOCK RESET
tBRH tR/TH RESET tRES BRCLK, TxC, RxC 1/fBRG 1/fR/T tBRL tR/TL
TRANSMIT
1 BIT TIME (1, 16, OR 64 CLOCK PERIODS) TxC (INPUT) RxD TxD tTxD tTCS TxC (OUTPUT) tTxD RxC (IX) tRXS tRXH
RECEIVE
CE
READ AND WRITE
tCE A0, A1 tAS R/W tCS D0-D7 (WRITE) tDS D0-D7 (READ) BUS FLOATING NOT VALID tDD tCH tAH
tCED
tDH BUS FLOATING tDF
DATA VALID
SD00052
1994 Apr 27
11
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
TIMING DIAGRAMS (Continued)
TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
TxC (1X) 1 TxD 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 SYN 1 4 5 1 2 3 4 5
DATA 1
DATA 2
DATA 3
DATA 4
SYNCHRONOUS MODE
TxEN
TxRDY
TxEMT
CE FOR WRITE OF THR DATA 1 D TxD A DATA 2 1 2 3 4 5 DATA 3 B C A 1 2 3 4 5 B C DATA 4 A 1 2 3 4 5 B C D A 1 2
DATA 1
DATA 2
DATA 3
DATA 4
ASYNCHRONOUS MODE
TxEN
TxRDY
TxEMT
CE FOR WRITE OF THR DATA 1 NOTES: A = Start bit B = Stop bit 1 C = Stop bit 2 D = TxD marking condition TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit. DATA 2 DATA 3 DATA 4
SD00053
1994 Apr 27
12
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
TIMING DIAGRAMS (Continued)
RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
RxC 1 SYNCHRONOUS MODE RxD 2 3 SYN 1 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5 IGNORED
RxEN SYNDET STATUS BIT
RxRDY
CE FOR READ READ STATUS READ STATUS READ RHR (DATA 1) READ RHR (DATA 2) READ RHR (DATA 3) READ RHR (DATA 3)
D A RxD ASYNCHRONOUS MODE 1 2 3 4 5 B C A 1 2 3 4 5 B C DATA 1 DATA 2
_
D
_A
1
2
3
4
5
B
C
A
1
2
3 DATA 4
DATA 3
RxEN RxRDY
OVERRUN STATUS BIT CE FOR READ READ RHR (DATA 1) READ RHR (DATA 3)
NOTES: A = Start bit B = Stop bit 1 C = Stop bit 2 D = TxD marking condition
SD00054
1994 Apr 27
13
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
8
RxD TxD SCN2651
EIA TO TTL CONVERT (OPT)
BRCLK
5.0688MHz OSCILLATOR
CRT TERMINAL
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
ADDRESS BUS
CONTROL BUS
DATA BUS
8
SCN2651
RxD TxD DSR DTR CTS RTS DCD ASYNC MODEM PHONE LINE INTERFACE
BRCLK
5.0688MHz OSCILLATOR TELEPHONE LINE
SD00055
1994 Apr 27
14
Philips Semiconductors
Product specification
Programmable communications interface (PCI)
SCN2651
TYPICAL APPLICATIONS (Continued)
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
ADDRESS BUS
CONTROL BUS
DATA BUS
RxD SCN2651 TxD RxC TxC SYNCHRONOUS TERMINAL OR PERIPHERAL DEVICE
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
ADDRESS BUS
CONTROL BUS
DATA BUS
SCN2651
RxD TxD RxC TxC DCD CTS RTS DSR DTR TELEPHONE LINE SYNC MODEM PHONE LINE INTERFACE
SD00056
1994 Apr 27
15

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