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1CY M18 40
CYM1840
256K x 32 Static RAM Module
Features
* High-density 8-megabit SRAM module * High-speed CMOS SRAMs
-- Access time of 20 ns
* Independent byte and word controls * Low active power
constructed from eight 256K x 4 SRAMs in SOJ packages mounted on an epoxy laminate substrate with pins. Four chip selects (CS0, CS1, CS2, and CS3) are used to independently enable the four bytes. Two write enables (WE0 and WE1) are used to independently write to either the upper or lower 16-bit word of RAM. Reading or writing can be executed on individual bytes or on any combination of multiple bytes through the proper use of selects and write enables. Writing to each byte is accomplished when the appropriate chip select (CS) and write enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking the chip selects (CS) LOW, while write enables (WE) remain HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O). The data input/output pins stay in the high-impedance state when write enables (WE) are LOW or the appropriate chip selects are HIGH.
-- 6.2W (max.)
* SMD technology * TTL-compatible inputs and outputs * Low profile
-- Max. height of .350 in.
* Small PCB footprint
-- 1.8 sq. in.
Functional Description
The CYM1840 is a high-performance 8-megabit static RAM module organized as 256K words by 32 bits. This module is
Pin Configuration DIP Logic Block Diagram
A0 - A17 WE 0
256K x 4 SRAM 18
Top View
VCC A0 I/O0 I/O1 I/O2 I/O3 CS0 A1 I/O4 I/O5 I/O6 I/O7 A2 A3 WE0 A4 A5 I/O8 I/O9 I/O10 I/O11 A6 A7 CS1 I/O12 I/O13 I/O14 I/O15 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
4
I/O0 - I/O3
256K x 4 SRAM
4
I/O4 - I/O7
CS0
256K x 4 SRAM
I/O8 - I/O11
4
256K x 4 SRAM
I/O12 - I/O15
4
CS1 WE1
256K x 4 SRAM
I/O16 - I/O19
4
256K x 4 SRAM
I/O20 - I/O23
4
CS2 I/O24 - I/O27 I/O26 - I/O31
256K x 4 SRAM
4
256K x 4 SRAM
4
CS3
1840-1
GND I/O31 I/O30 I/O29 I/O28 A17 A16 CS3 I/O27 I/O26 I/O25 I/O24 A15 A14 WE1 A13 A12 I/O23 I/O22 I/O21 I/O20 A11 A10 CS2 I/O19 I/O18 I/O17 I/O16 A9 VCC
1840-2
Selection Guide
1840-20 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Cypress Semiconductor Corporation * 20 1120 320 1840-25 25 1120 320 * 1840-30 30 1120 320 San Jose * 1840-35 35 1120 320 1840-45 45 1120 320 1840-55 55 1120 320
3901 North First Street
CA 95134 * 408-943-2600 October 1990 - Revised June 1993
CYM1840
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied (PD) ...................................... -10C to +85C DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-3.0V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
lectrical Characteristics Over the Operating Range
CYM1840 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CSX < VIL Max. VCC, CSX > VIH, Min. Duty Cycle = 100% Max. VCC, CSX > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -20 -50 Min. 2.4 0.4 VCC 0.8 +20 +50 1120 320 160 Max. Unit V V V V A A mA mA mA
Capacitance[2]
Parameter CINA CINB COUT Description Input Capacitance, Address Pins Input Capacitance, I/O Pins Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 100 30 30 Unit pF pF pF
Notes: 1. A pull-up resistor to V CC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1 481 3.0V GND < 5 ns
1838-3
ALL INPUT PULSES 90% 10% 90% 10% < 5 ns
1838-4
(a)
(b)
Equivalent to: OUTPUT
THE EVENIN EQUIVALENT 125 1.90V
2
CYM1840
Switching Characteristics Over the Operating Range[3]
1840-20 Parameter READ CYCLE tRC tAA tOHA tACS tLZCS tHZCS tPU tPD WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid CS LOW to Low Z
[4] [4, 5]
1840-25 Min. 25 Max.
1840-30 Min. 30 Max. Unit ns 30 5 30 5 20 0 30 30 25 25 2 2 25 15 2 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Description
Min. 20
Max.
20 5 20 5 20 0 20 20 18 18 2 2 15 13 2 0 0 15 25 20 20 2 2 20 15 2 0 0 0 5 5
25 25 20 25
CS HIGH to High Z
CS LOW to Power-Up CS HIGH to Power-Down CYCLE[6] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[5]
15
0
Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. 5. tHZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1840
Switching Characteristics Over the Operating Range[3] (continued)
1840-35 Parameter READ CYCLE tRC tAA tOHA tACS tLZCS tHZCS tPU tPD tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid CS LOW to Low Z[4] CS HIGH to High Z
[4,5]
1840-45 Min. 45 Max.
1840-55 Min. 55 Max. Unit ns 55 5 55 5 25 0 55 55 50 50 6 6 40 35 6 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 ns
Description
Min. 35
Max.
35 5 35 5 25 0 35 35 30 30 6 6 25 25 6 0 0 25 45 40 40 6 6 30 30 6 0 0 0 5 5
45 45 25 45
CS LOW to Power-Up CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[5]
WRITE CYCLE[6]
25
0
Switching Waveforms
Read Cycle No. 1 [7,8]
t RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1840-5
4
CYM1840
Switching Waveforms (continued)
Read Cycle No. 2
CS tACS tLZCS HIGH IMPEDANCE DATA OUT tPU V CC SUPPLY CURRENT 50% DATA VALID tPD ICC 50% ISB
1840-6
[7,8]
t RC
tHZCS HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled) [6]
tWC ADDRESS tSCS CS tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1840-7
tAW tPWE
tHA
tHD
tLZWE HIGH IMPEDANCE
5
CYM1840
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)
[6,9]
,
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1840-8
tSCS
tHA
tHD
Notes: 7. Device is continuously selected, CS = VIL. 8. WE is HIGH for read cycle. 9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS H L L WE X H L Input/Output High Z Data Out Data In Read Write Mode Deselect/Power-Down
Ordering Information
Speed 20 25 30 35 45 55 Ordering Code CYM1840PD-20C CYM1840PD-25C CYM1840PD-30C CYM1840PD-35C CYM1840PD-45C CYM1840PD-55C Package Name PD06 PD06 PD06 PD06 PD06 PD06 Package Type 60-Pin DIP Module 60-Pin DIP Module 60-Pin DIP Module 60-Pin DIP Module 60-Pin DIP Module 60-Pin DIP Module Operating Range Commercial Commercial Commercial Commercial Commercial Commercial
Document #: 38-M-00040-B
6
CYM1840
Package Diagram
60-Pin DIP Module PD06
2.990/3.010
.300/.350
.600TYP.
PIN 1
0.010 0.030 . .100 TYP
.125/.175
(c) Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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