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2 Megabit (256K x 8) Page Mode EEPROM
SST29EE020 / SST29LE020 / SST29VE020
Data Sheet
FEATURES: * Single Voltage Read and Write Operations - 5.0V-only for the SST29EE020 - 3.0-3.6V for the SST29LE020 - 2.7-3.6V for the SST29VE020 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V - Standby Current: 10 A (typical) * Fast Page Write Operation - 128 Bytes per Page, 2048 Pages - Page Write Cycle: 5 ms (typical) - Complete Memory Rewrite: 10 sec (typical) - Effective Byte Write Cycle Time: 39 s (typical)
* Fast Read Access Time: 120 and 150 ns - 5.0V-only operation: 120 and 150 ns - 3.0-3.6V operation: 200 and 250 ns - 2.7-3.6V operation: 200 and 250 ns * Latched Address and Data * Automatic Write Timing - Internal VPP Generation * End of Write Detection - Toggle Bit - Data# Polling * Hardware and Software Data Protection * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32 Pin PDIP - 32-Pin PLCC - 32-Pin TSOP (8mm x 20mm) The SST29EE020/29LE020/29VE020 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE020/29LE020/ 29VE020 significantly improve performance and reliability, while lowering power consumption. The SST29EE020/29LE020/29VE020 improve flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the SST29EE020/29LE020/29VE020 are offered in 32-pin TSOP and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST page mode EEPROM offers in-circuit electrical write capability. The SST29EE020/29LE020/29VE020 does not require separate Erase and Program operations. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE020/29LE020/29VE020 have industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE020/ 29LE020/29VE020 are compatible with industry standard EEPROM pinouts and functionality.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PRODUCT DESCRIPTION The SST29EE020/29LE020/29VE020 are 256K x 8 CMOS Page Write EEPROM manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE020/29LE020/29VE020 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE020/29LE020/29VE020 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance page write, the SST29EE020/29LE020/29VE020 provide a typical byte-write time of 39 sec. The entire memory, i.e., 256 KBytes, can be written page-by-page in as little as 10 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the SST29EE020/29LE020/29VE020 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE020/29LE020/29VE020 are offered with a guaranteed page write endurance of 104 cycles. Data retention is rated at greater than 100 years.
(c) 1999 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 307-04 2/99 1
2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Read The Read operations of the SST29EE020/29LE020/ 29VE020 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3). Write The Page Write to the SST29EE020/29LE020/29VE020 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE020/29LE020/29VE020 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, software data protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired page write, the entire device remains protected. For additional descriptions, please see the application notes on "The Proper Use of JEDEC Standard Software Data Protection" and "Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories" in this data book. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE020/29LE020/29VE020. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 14 and 16 for flowcharts. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load
(c) 1999 Silicon Storage Technology, Inc.
cycle, and the internal write cycle. The Software Data Protection consists of a specific three-byte load sequence that allows writing to the selected page and will leave the SST29EE020/29LE020/29VE020 protected at the end of the Page Write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Page Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE020/ 29LE020/29VE020 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the page write feature of SST29EE020/ 29LE020/29VE020 allow the entire memory to be written in as little as 10 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FF. See Figures 4 and 5 for the page write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byteload cycle time (TBLC) of 100 s, the SST29EE020/ 29LE020/29VE020 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. The page to be loaded is determined by the page address of the last byte loaded. Software Chip Erase The SST29EE020/29LE020/29VE020 provide a Chip Erase operation, which allows the user to simultaneously clear the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Software Chip Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Write Operation Status Detection The SST29EE020/29LE020/29VE020 provide two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST29EE020/29LE020/29VE020 are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. Toggle Bit (DQ6) During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e., toggling between 0 and 1. When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a "1". Data Protection The SST29EE020/29LE020/29VE020 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST29EE020/29LE020/29VE020 provide the JEDEC approved optional software data protection scheme for all data alteration operations, i.e., Write and Chip Erase. With this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or powerdown. The SST29EE020/29LE020/29VE020 are shipped with the software data protection disabled. The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 s. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts. The SST29EE020/29LE020/29VE020 Software Data Protection is a global command, protecting all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single page write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled.
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(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE020/29LE020/ 29VE020 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing. Please refer to the following Application Notes located at the back of this databook for more information on using SDP: * * Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories The Proper Use of JEDEC Standard Software Data Protection using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations. TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 H SST29EE020 Device Code 0001 H SST29LE020 Device Code 0001 H SST29VE020 Device Code 0001 H
Data BF H 10 H 12 H 12 H
307 PGM T1.1
Product Identification The product identification mode identifies the device as the SST29EE020/29LE020/29VE020 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST29EE020/29LE020/29VE020. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when
Product Identification Mode Exit In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the read operation. The Reset operation may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 17 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM OF SST 29EE020/29LE020/29VE020 2,097,152 Bit EEPROM Cell Array
X-Decoder
A17 - A0
Address Buffer & Latches Y-Decoder and Page Latches
CE# OE# WE#
Control Logic
I/O Buffers and Data Latches DQ7 - DQ0
307 ILL B1.0
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
A11 A9 A8 A13 A14 A17 WE# VCC NC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
307 ILL F01.0
1 2 3 4 5
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
WE# VCC
A12
A15
A16
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
VSS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
A17
NC
6
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
7 8 9
307 ILL F02.0
32-Lead PLCC Top View
21 14 15 16 17 18 19 20
10 11 12 13 14 15 16
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A17-A7 Row Address Inputs A6-A0 DQ7-DQ0 Column Address Inputs Data Input/output Functions To provide memory addresses. Row addresses define a page for a write cycle. Column Addresses are toggled to load page data. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the write operations To provide 5-volt supply ( 10%) for the SST29EE020, 3-volt supply (3.0-3.6V) for the SST29LE020 and 2.7-volt supply (2.7-3.6V) for the SST29VE020 Unconnected pins.
307 PGM T2.1 (c) 1999 Silicon Storage Technology, Inc. 307-04 2/99
CE# OE# WE# Vcc
Chip Enable Output Enable Write Enable Power Supply
Vss NC
Ground No Connection
5
2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Page Write VIL VIH Standby VIH X Write Inhibit X VIL Write Inhibit X X Software Chip Erase VIL VIH Product Identification Hardware Mode VIL VIL Software Mode SDP Enable Mode SDP Disable Mode VIL VIL VIL VIH VIH VIH
WE# VIH VIL X X VIH VIL VIH VIL VIL VIL
DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN Manufacturer Code (BF) Device Code (see notes)
Address AIN AIN X X X AIN, See Table 4 A17 - A1 = VIL, A9 = VH, A0 = VIL A17 - A1 = VIL, A9 = VH, A0= VIH See Table 4 See Table 4 See Table 4
307 PGM T3.0
TABLE 4: SOFTWARE COMMAND CODES
Command Sequence Software Data Protect Enable & Page Write Software Data Protect Disable Software Chip Erase Software ID Entry Software ID Exit 1st Bus Write Cycle Addr(1) Data 5555H AAH 2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 3rd Bus Write Cycle Addr(1) Data 5555H A0H 4th Bus Write Cycle Addr(1) Data Addr(2) Data 5th Bus Write Cycle Addr(1) Data 6th Bus Write Cycle Addr(1) Data
5555H 5555H 5555H 5555H
AAH AAH AAH AAH AAH
2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
55H 55H 55H 55H 55H
5555H 5555H 5555H 5555H 5555H
80H 80H 90H F0H 80H
5555H 5555H
AAH AAH
2AAAH 2AAAH
55H 55H
5555H 5555H
20H 10H
Alternate Software 5555H ID Entry(3)
Notes:
(1) (2)
5555H
AAH
2AAAH
55H
5555H
60H
307 PGM T4.0
Address format A14-A0 (Hex), Address A15 is a "Don't Care". Page Write consists of loading up to 128 bytes (A6 - A0). (3) Alternate six-byte Software Product ID Command Code (3) The software Chip Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, SST29EE020 Device Code = 10H, is read with A0 = 1, SST29LE020/29VE020 Device Code = 12H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. 3. This product supports both the JEDEC standard three-byte command code sequence and SST's original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used.
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ....................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
1 2 3 4 5 6 7 8
SST29EE020 OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C SST29LE020 OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C SST29VE020 OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 5V10% 5V10% Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 12 and 13
VCC 3.0V to 3.6V 3.0V to 3.6V
9 10
VCC 2.7V to 3.6V 2.7V to 3.6V
11 12 13 14 15 16
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
TABLE 5: SST29EE020 DC OPERATING CHARACTERISTICS VCC = 5V 10% Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open, Read 30 mA Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max Write 50 mA CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. ISB1 Standby VCC Current 3 mA CE#=OE#=WE#=VIH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 50 A CE#=OE#=WE#=VCC -0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN =GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 A VOUT =GND to VCC, VCC = VCC Max. Input Low Voltage 0.8 V VCC = VCC Min. VIL VIH Input High Voltage 2.0 V VCC = VCC Max. VOL Output Low Voltage 0.4 V IOL = 2.1 mA, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -400A, VCC = VCC Min. VH Supervoltage for A9 11.6 12.4 V CE# = OE# =VIL, WE# = VIH IH Supervoltage Current 200 A CE# = OE# = VIL, WE# = VIH, for A9 A9 = VH Max.
307PGM T5.1
TABLE 6: SST29LE020/29VE020 DC OPERATING CHARACTERISTICS VCC = 3.0-3.6V FOR SST29LE020, VCC = 2.7-3.6V FOR SST29VE020 Limits Symbol Parameter Min Max Units Test Conditions ICC Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open, Read 12 mA Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max Write 15 mA CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. ISB1 Standby VCC Current 1 mA CE#=OE#=WE#=VIH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 15 A CE#=OE#=WE#=VCC -0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN =GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 A VOUT =GND to VCC, VCC = VCC Max. VIL Input Low Voltage 0.8 V VCC = VCC Min. VIH Input High Voltage 2.0 V VCC = VCC Max. VOL Output Low Voltage 0.4 V IOL = 100 A, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -100 A, VCC = VCC Min. VH Supervoltage for A9 11.6 12.4 V CE# = OE# =VIL, WE# = VIH IH Supervoltage Current 200 A CE# = OE# = VIL, WE# = VIH, for A9 A9 = VH Max.
307PGM T6.1
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
TABLE 7: POWER-UP TIMINGS Symbol Parameter (1) TPU-READ Power-up to Read Operation (1) TPU-WRITE Power-up to Write Operation
Maximum 100 5
Units s ms
307 PGM T7.0
1 2 3
307 PGM T8.0
TABLE 8: CAPACITANCE (Ta = 25 C, f=1 MHz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V (1) CIN Input Capacitance VIN = 0V
Maximum 12 pF 6 pF
4 5
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention VZAP_HBM(1) ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up
Note:
(1)This
Minimum Specification 10,000 100 2000 200 100
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
307 PGM T9.3
6 7 8 9 10 11 12 13 14 15 16
parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
AC CHARACTERISTICS TABLE 10: SST29EE020 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change SST29EE020-120 SST29EE020-150 Min Max Min Max 120 150 120 150 120 150 50 60 0 0 0 0 30 30 30 30 0 0 Units ns ns ns ns ns ns ns ns ns
307 PGM T10.0
TABLE 11: SST29LE020 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change SST29LE020-200 SST29LE020-250 Min Max Min Max 200 250 200 250 200 250 100 120 0 0 0 0 50 50 50 50 0 0 Units ns ns ns ns ns ns ns ns ns
307 PGM T11.0
TABLE 12: SST29VE020 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change SST29VE020-200 SST29VE020-250 Min Max Min Max Units 200 250 ns 200 250 ns 200 250 ns 100 120 ns 0 0 ns 0 0 ns 50 50 ns 50 50 ns 0 0 ns
307 PGM T12.0
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
TABLE 13: PAGE WRITE CYCLE TIMING PARAMETERS Symbol TWC TAS TAH TCS TCH TOES TOEH TCP TWP TDS TDH TBLC(1) TBLCO(1) TIDA TSCE Parameter Write Cycle (Erase and Program) Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software ID Access and Exit Time Software Chip Erase SST29EE020 Min Max 10 0 50 0 0 0 0 70 70 35 0 0.05 100 200 10 20 SST29LE/VE020 Min Max 10 0 70 0 0 0 0 120 120 50 0 0.05 100 200 10 20 Units ms ns ns ns ns ns ns ns ns ns ns s s s ms
307 PGM T13.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
TRC ADDRESS A17-0 TCE CE# TOE OE# VIH WE# TCLZ TOH DATA VALID TOLZ
TAA
TOHZ
TCHZ HIGH-Z DATA VALID
307 ILL F03.0
HIGH-Z DQ 7-0
FIGURE 3: READ CYCLE TIMING DIAGRAM
Three-Byte Sequence for Enabling SDP ADDRESS A17-0 5555 2AAA 5555
TAH TAS
TCS CE# TOES OE# TWP WE#
TCH
TOEH
TBLC
TBLCO
TDH DQ 7-0 AA SW0 55 SW1 A0 SW2 BYTE 0 DATA VALID TDS BYTE 1 BYTE 127
307 ILL F04.1
TWC
FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Three-Byte Sequence for Enabling SDP ADDRESS A17-0 5555 2AAA 5555
TAH TAS
1
TBLC TBLCO
TCP CE#
2 3
TOES OE# TCS WE#
TOEH
4
TCH
5
TDH AA SW0 55 SW1 A0 SW2 BYTE 0 DATA VALID TDS BYTE 1 BYTE 127
307 ILL F05.1
DQ 7-0
TWC
6 7 8 9 10
FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM
ADDRESS A17-0 TCE CE# TOEH OE# TOE WE# TOES
11 12 13
D# TWC + TBLCO
307 ILL F06.0
DQ 7
D
D#
D
14 15 16
FIGURE 6: DATA# POLLING TIMING DIAGRAM
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
ADDRESS A17-0 TCE CE# TOEH TOE OE# TOES
WE#
DQ6 TWC + TBLCO
TWO READ CYCLES WITH SAME OUTPUTS
307 ILL F07.1
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
Six-Byte Sequence for Disabling Software Data Protection ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TWC
DQ 7-0
AA
55
80
AA
55
20
CE#
OE# TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5
307 ILL F08.1
TBLCO
FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Six-Byte Code for Software Chip Erase ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
1 2
DQ 7-0
AA
55
80
AA
55
10
3
CE#
4 5
TWP TBLCO TBLC SW0 SW1 SW2 SW3 SW4 SW5
307 ILL F09.1
OE#
WE#
6 7 8 9
FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM
Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 TAA DQ 7-0 AA 55 90 TIDA CE# BF DEVICE CODE 0001
10 11 12 13
OE# TWP WE# TBLC SW0 SW1 SW2 DEVICE CODE = 10 for SST29EE020 = 12 for SST29LE020/29VE020
307 ILL F10.0
14 15 16
FIGURE 10: SOFTWARE ID ENTRY AND READ
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Three-Byte Sequence for Software ID Exit and Reset ADDRESS A14-0 5555 2AAA 5555
DQ 7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# TBLC SW0 SW1 SW2
307 ILL F11.0
FIGURE 11: SOFTWARE ID EXIT AND RESET
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
1
307 ILL F12.1
VLT VILT
VLT
2 3 4 5 6 7
AC test inputs are driven at VIHT (2.4 V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% 90%) are <10 ns.
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE VCC TO TESTER RL HIGH
8 9 10
TO DUT CL RL LOW
11 12
307 ILL F13.0
13 14
FIGURE 13: A TEST LOAD EXAMPLE
15 16
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Start Software Data Protect Write Command
See Figure 16
Set Page Address
Set Byte Address = 0
Load Byte Data
Increment Byte Address By 1
No
Byte Address = 128? Yes Wait TBLCO
Wait for end of Write (TWC, Data# Polling bit or Toggle bit operation) Write Completed
307 ILL F14.0
FIGURE 14: WRITE ALGORITHM
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Internal Timer
Page Write Initiated
Toggle Bit
Page Write Initiated
Data# Polling
Page Write Initiated
1 2 3
Wait TWC
Read a byte from page
Read DQ7 (Data for last byte loaded)
4 5 6
Write Completed
Read same byte
No
Is DQ7 = true data?
7
Yes No Write Completed
8 9
Does DQ6 match?
Yes Write Completed
307 ILL F15.0
10 11 12
FIGURE 15: WAIT OPTIONS
13 14 15 16
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Software Data Protect Enable Command Sequence Write data: AA Address: 5555
Software Data Protect Disable Command Sequence Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Write data: A0 Address: 5555
Write data: 80 Address: 5555
Load 0 to 128 Bytes of page data
Optional Page Load Operation
Write data: AA Address: 5555
Wait TBLCO
Write data: 55 Address: 2AAA
Wait TWC
Write data: 20 Address: 5555
SDP Enabled
Wait TBLCO
Wait TWC
SDP Disabled
307 ILL F16.0
FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Software Product ID Entry Command Sequence Write data: AA Address: 5555
Software Product ID Exit & Reset Command Sequence Write data: AA Address: 5555
1 2 3
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
4 5 6
Write data: 90 Address: 5555
Write data: F0 Address: 5555
Pause 10 s
Pause 10 s
7 8
307 ILL F17.0
Read Software ID
Return to normal operation
9 10
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
11 12 13 14 15 16
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
Software Chip Erase Command Sequence Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 80 Address: 5555
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 10 Address: 5555
Wait TSCE
Chip Erase to FFH
307 ILL F18.0
FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
PRODUCT ORDERING INFORMATION
Device SST29XE020
Speed - XXX -
Suffix1 XX -
Suffix2 XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up) 8mm x 20mm U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns Voltage E = 5.0V-only L = 3.0-3.6V V = 2.7-3.6V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
SST29EE020 Valid combinations SST29EE020-120-4C- EH SST29EE020-150-4C- EH SST29EE020-120-4I-EH SST29EE020-150-4I-EH SST29EE020-150-4C-U2 SST29LE020 Valid combinations SST29LE020-200-4C- EH SST29LE020-250-4C- EH SST29LE020-200-4I-EH SST29LE020-250-4C-U2 SST29LE020-200-4C- NH SST29LE020-250-4C- NH SST29LE020-200-4I-NH SST29EE020-120-4C- NH SST29EE020-150-4C- NH SST29EE020-120-4I-NH SST29EE020-150-4I-NH SST29EE020-120-4C- PH SST29EE020-150-4C- PH
SST29VE020 Valid combinations SST29VE020-200-4C-EH SST29VE020-250-4C-EH SST29VE020-200-4I-EH SST29VE020-250-4C-U2 SST29VE020-200-4C-NH SST29VE020-250-4C-NH SST29VE020-200-4I-NH
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part.
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
PACKAGING DIAGRAMS
pin 1 index 1
1 2
.600 .625 .530 .550
C L
32
3 4 5
.065 .075
1.645 1.655
7 4 PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
.070 .080
.045 .065
.016 .022
.100 BSC
6 7
32.pdipPH-ILL.1
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
8 9
TOP VIEW
SIDE VIEW
BOTTOM VIEW
10
Optional Pin #1 Identifier .485 .495 .447 .453 .042 .048
2 1 32
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
11 12
.490 .530
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
13 14
.026 .032
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095
15
32.PLCC.NH-ILL.1
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
16
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c) 1999 Silicon Storage Technology, Inc. 307-04 2/99
25
2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
PIN # 1 IDENTIFIER
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
18.50 18.30
0.15 0.05
0.70 0.50
20.20 19.80
Note:
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
32.TSOP-EH-ILL.2
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: EH
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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2 Megabit Page Mode EEPROM SST29EE020 / SST29LE020 / SST29VE020
SST Area Offices
Customer Service Northwest USA, Rocky Mtns. & West Canada Central & Southwest USA East USA & East Canada North America - Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7754 (408) 523-7661 (727) 771-8819 (978) 356-3845 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000
International Sales Representatives & Distributors
Australia ACD Belgium Memec Benelux China/Hong Kong Actron Technology Co., Ltd. (HQ) Hong Kong Actron Technology Co., Ltd. - Shanghai Actron Technology Co., Ltd. - Shenzhen Actron Technology Co., Ltd. - Chengdu Actron Technology Co., Ltd. - Beijing Actron Technology Co., Ltd. - Wuhan Actron Technology Co., Ltd. - Xian
MetaTech Limited (HQ) - Hong Kong MetaTech Limited - Beijing MetaTech Limited - Shanghai MetaTech Limited - Chengdu MetaTech Limited - Fuzhou MetaTech Limited - Shenzhen Serial System Ltd. - Hong Kong Serial System Ltd. - Chengdu Serial System Ltd. - Shanghai Serial System Ltd. - Shenzhen (61) 3-762 7644 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (852) 2950-0820 (86) 28-524-0208 (86) 21-6473-2080 (86) 755-212-9076 (45) 7010-4888 (33) 4 72 37 0414 (33) 1 46 23 7900
North American Sales Representatives
Alabama M-Squared, Inc. - Huntsville Arizona QuadRep, Inc. California Costar - Northern Falcon Sales & Technology - San Marcos Westar Rep Company, Inc. - Calabasas Westar Rep Company, Inc. - Irvine Colorado Lange Sales, Inc. Florida M-Squared, Inc. - Clearwater M-Squared, Inc. - Coral Springs M-Squared, Inc. - Longwood Georgia M-Squared, Inc. - Atlanta Illinois Oasis Sales Corporation - Northern Rush & West Associates - Southern Indiana Applied Data Management Iowa Rush & West Associates Kansas Rush & West Associates Maryland Nexus Technology Sales Massachusetts A/D Sales Michigan Applied Data Management Minnesota Cahill, Schmitz & Cahill Missouri Rush & West Associates North Carolina M-Squared, Inc. - Charlotte M-Squared, Inc. - Raleigh New Jersey Nexus Technology Sales New Mexico QuadRep, Inc. New York Nexus Technology Sales Reagan/Compar - Endwell Reagan/Compar - E. Rochester Ohio Applied Data Management - Cincinnati Applied Data Management - Cleveland Oregon Thorson Pacific, Inc. Pennsylvania Nexus Technology Sales Texas Technical Marketing, Inc. - Carrollton Technical Marketing, Inc. - Houston Technical Marketing, Inc. - Austin Utah Lange Sales, Inc. Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation Canada Electronics Sales Professionals - Ottawa Electronics Sales Professionals - Toronto Electronics Sales Professionals - Montreal
Thorson Pacific, Inc. - B.C. (205) 830-0498 (602) 839-2102 (408) 946-9339 (760) 591-0504 (818) 880-0594 (949) 453-7900 (303) 795-3600 (727) 669-2408 (954) 753-5314 (407) 682-6662 (770) 447-6124 (847) 640-1850 (314) 965-3322 (317) 257-8949 (319) 398-9679 (913) 764-2700 (301) 663-4159 (978) 851-5400 (734) 741-9292 (612) 699-0200 (314) 965-3322 (704) 522-1150 (919) 848-4300 (201) 947-0151 (505) 332-2417 (516) 843-0100 (607) 754-2171 (716) 218-4370 (513) 579-8108 (440) 946-6812 (503) 293-9001 (215) 675-9600 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 487-0843 (425) 603-9393 (414) 782-6660 (613) 828-6881 (905) 856-8448 (514) 388-6596 (604) 294-3999
Denmark C-88 AS France
A2M - Bron A2M - Sevres
Germany Endrich Bauelemente Vertriebs GMBH - Bramstedt
Endrich Bauelemente Vertriebs GMBH - Nagold
(49) 4192-897910 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 61 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (65) 748-4844 (65) 280-0200 (27) 11 845-5011 (34) 91 371-7768 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 4-7-99
India Team Technology - Bangalore Team Technology - Hyderabad Team Technology - New Delhi Ireland Curragh Technology Israel Spectec Electronics Italy Carlo Gavazzi Cefra SpA Japan Asahi Electronics Co., Ltd. - Tokyo Asahi Electronics Co., Ltd. - Kitakyushu
Microtek, Inc. - Osaka Microtek, Inc. - Tokyo Ryoden Trading Co., Ltd. - Osaka Ryoden Trading Co., Ltd. - Tokyo Silicon Technology Co., Ltd.
Korea Bigshine Korea Co., Ltd. Malaysia MetaTech (M) SDN BHD
Serial System SDN BHD Serial System - Kuala Lumpur
Netherlands Memec Benelux Singapore MetaTech (S) Pte Ltd.
Serial System Ltd. (HQ)
South Africa KH Distributors Spain Tekelec Espana S.A. Switzerland Leading Technologies Taiwan, R.O.C. GCH-Sun Systems Co., Ltd. (GSS) PCT Limited Tonsam Corporation United Kingdom Ambar Components, Ltd.
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 1999 Silicon Storage Technology, Inc.
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