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1CY M14 64
CYM1464
512Kx8 Static RAM Module
Features
* High-density 4-megabit SRAM module * High-speed CMOS SRAMs -- Access time of 20 ns * Low active power -- 1.93W (max.) * JEDEC-compatible pinout * 32-pin, 0.6-inch-wide DIP package * TTL-compatible inputs and outputs * Low profile -- Max. height of 0.34 inches constructed using four 256K x 4 static RAMs in SOJ packages mounted on an epoxy laminate substrate with pins. Writing to the module is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is written into the memory location specified on the address pins (A0 through A18). Reading the device is accomplished by taking chip select and output enable (OE) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7). The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Functional Description
The CYM1464 is a high-performance 4-megabit static RAM module organized as 512K words by 8 bits. This module is
Logic Block Diagram
A0 - A17 WE OE 256K x 4 SRAM 256K x 4 SRAM
Pin Configuration
DIP Top View
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 - I/O 7
1464-1 1S 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A18 CS
1 OF 2 DECODER
256K x 4 SRAM
256K x 4 SRAM
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
1464-2
Selection Guide
1464-20 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 20 350 240 1464-22 22 350 240 1464-25 25 1464-30 30 300 240 1464-35 35 1464-45 45 300 240 1464-55 55
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 October 1989 - Revised February 1995
CYM1464
Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature ..................................... -55C to +125C Ambient Temperature with Power Applied.................................................... -10C to +85C Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-0.5V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
1464-20, 22, 25 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current GND < VI < VCC Output Leakage Current GND < V0 < VCC, Output Disabled VCC Operating Supply Current Automatic CS Power-Down Current Automatic CS Power-Down Current VCC = Max., IOUT = 0 mA, CS < VIL VCC = Max., CS > VIH, Min. Duty Cycle = 100% VCC = Max., CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 - 10 -10 Min. 2.4 0.4 VCC +0.3 0.8 +10 +10 350 240 60 2.2 -0.5 - 10 -10 Max. 1464-30, 35, 45, 55 Min. 2.4 0.4 VCC +0.3 0.8 +10 +10 300 240 60 Max. Unit V V V V A A mA mA mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 40 30 Unit pF pF
AC Test Loads and Waveforms
R1481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1481 3.0V 90% GND < 5 ns 10% 90% 10% < 5 ns ALL INPUT PULSES
(a)
Equivalent to: OUTPUT THEVENIN EQUIVALENT 167 1.73V
(b)
1464-3
1464-4
Notes: 1. VIL (min.) = -3.0V for pulse widths less than 20 ns. 2. Tested on a sample basis.
2
CYM1464
Switching Characteristics Over the Operating Range[3]
1464-20 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z CS HIGH to High
[5]
1464-22 Min. 22 Max.
1464-25 Min. 25 Max.
1464-30 Min. 30 Max. Unit ns 30 5 30 15 0 0 10 0 30 25 25 3 5 20 15 2 0 10 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Description
Min. 20
Max.
20 5 20 13 0 0 5 0 20 15 15 3 5 15 12 2 0 15
[3]
22 5 22 13 0 0 10 15 0 5 0 25 20 20 3 5 15 15 2 0 15 0 5 0 22 17 15 3 5 15 12 2 0 5
25 25 15 10 15
10 15
Z[4]
WRITE CYCLE
Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[4]
15
Switching Characteristics Over the Operating Range
Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS WRITE CYCLE tWC tSCS
[5]
1464-35 Description Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z CS HIGH to High Z[4] Write Cycle Time CS LOW to Write End 0 0 10 0 35 30 20 15 5 35 20 Min. 35 35 Max.
1464-45 Min. 45 45 5 45 25 0 0 10 0 45 40 20 15 Max.
1464-55 Min. 55 55 5 55 30 0 0 10 0 55 50 20 15 Max. Unit ns ns ns ns ns ns ns ns ns ns ns
Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 4. tHZCS and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1464
Switching Characteristics Over the Operating Range (continued)[3]
1464-35 Parameter tAW tHA tPWE tSD tHD tLZWE tHZWE Description Address Set-Up to Write End Address Hold from Write End WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[4] Min. 30 3 25 20 2 0 15 Max. 1464-45 Min. 40 3 35 25 3 0 15 Max. 1464-55 Min. 50 3 40 35 3 0 20 Max. Unit ns ns ns ns ns ns ns
Switching Waveforms
Read Cycle No. 1 [6,7]
tRC ADDRESS tAA tOHA DATAOUT PREVIOUS DATA VALID DATA VALID
1464-5
Read Cycle No. 2
CS
[6,8]
tRC tACS
OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU V CC SUPPLY CURRENT 50% tPD ICC 50% ISB
1464-6
tHZOE tHZCS DATA VALID HIGH IMPEDANCE
Notes: 6. WE is HIGH for read cycle. 7. Device is continuously selected, CS = VIL. 8. Address valid prior to or coincident with CS transition LOW.
4
CYM1464
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [5]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATAIN DATA VALID tHZWE DATAI/O DATA UNDEFINED
1464-7
tPWE
tHA
tHD
tLZWE HIGH IMPEDANCE
Write Cycle No. 2 (CS Controlled)[5,9]
tWC ADDRESS tSA CS tAW WE tPWE tSD DATAIN DATA VALID tHZWE DATAI/O HIGH IMPEDANCE DATA UNDEFINED
1464-8
tSCS
tHA
tHD
Note: 9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
5
CYM1464
Truth Table
CS H L L L WE X H L H OE X L X H Input/Output High Z Data Out Data In High Z Mode Deselect/Power-Down Read Word Write Word Deselect
Ordering Information
Speed (ns) 20 22 25 30 35 45 55 Ordering Code CYM1464PD-20C CYM1464PD-22C CYM1464PD-25C CYM1464PD-30C CYM1464PD-35C CYM1464PD-45C CYM1464PD-55C Package Type PD02 PD02 PD02 PD02 PD02 PD02 PD02 Package Type 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module 32-Pin DIP Module Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial
Document #: 38-M-00030-D
6
CYM1464
Package Diagrams
32-Pin DIP Module PD02
1.590 1.610
0.590 0.610
0.600 0.620
0.007 0.013 0.315 0.335 0.125 0.175 0.050 TYP DIMENSIONSININCHES MIN. MAX.
0.100 TYP
0.015 0.025
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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