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RFW2N06RLE
Data Sheet July 1999 File Number
2838.3
2A, 60V, 0.160 Ohm, Logic Level, N-Channel Power MOSFET
The RFW2N06RLE N-Channel, logic level, ESD protected, power MOSFET is manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. The RFW2N06RLE was designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor and relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA9861.
Features
* 2A, 60V * rDS(on) = 0.160 * UIS Rating Curve (Single Pulse) * Design Optimized For 5 Volt Gate Drive * Can be Driven Directly from CMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device * Electrostatic Discharge Protected
Ordering Information
PART NUMBER RFW2N06RLE PACKAGE HEXDIP BRAND RFW2N06RLE
* Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
NOTE: When ordering, use the entire part number.
Symbol
D
G
S
Packaging
4 PIN HEXDIP
DRAIN GATE SOURCE
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFW2N06RLE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFW2N06RLE 60 60 2 14 -5 to 10 1.09 0.009 Refer to UIS Curve 2 -55 to 150 300 260 UNITS V V A A V W W/oC KV oC
oC oC
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Electrostatic Discharge Rating, MIL-STD-883, Catagory B(2). . . . . . . . . . . . . . . . . . . . . . . .ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID =250A, VGS = 0V VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V TC = 125oC MIN 60 1 TYP 13 42 95 45 VGS = 0 to 10V VGS = 0 to 5V VGS = 0 to 1V VDD = 48V, ID = 2A, IG(REF) =0.5mA, RL = 24 (Figures 12, 15, 16) 20 11 0.6 535 175 32 MAX 2 1 25 100 160 200 100 200 30 16 1.0 115 UNITS V V A A nA m m ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2)
IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA
VGS =-5V to 10V ID = 2A, VGS = 5V (Figure 8) ID = 2A, VGS = 4.3V (Figure 8) VDD = 30V, ID = 2A, RL = 15, VGS = 5V, RG = 25 (Figures 12, 13, 14)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance, Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz (Figure 11)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time NOTES: 2. Pulse test: width 300s duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 2A ISD = 2A, dlSD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.2 200 UNITS V ns
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RFW2N06RLE Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A)
Unless Otherwise Specified
2.5
2.0
1.5
0.6 0.4
1.0
0.2 0 0 25 50 75 100 TC , CASETEMPERATURE (oC) 125 150
0.5
0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
10 TJ = MAX RATED TC = 25oC ID MAX CONTINUOUS ID, DRAIN CURRENT, (A) 1 IAS (A)
50
IF R = 0 tav = (L)(Ias) / (1.3 RATED BVDSS - VDD) IF R 0 tav = (L/R) IN ((Ias x R) / (1.3 RATED BVDSS - VDD) + 1)
Idm 10
STARTING TJ = 25oC STARTING TJ = 150oC
0.10
OPERATION IN THIS AREA IS LIMITED BY rDS(ON)
0.01 0.1
1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
100
1 0.01
0.1 1 TAV, TIME IN AVALANCHE (ms)
10
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
ID, DRAIN TO SOURCE CURRENT (A)
10V
5V
4V
PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX TC = 25oC
IDS(ON), DRAIN TO SOURCE CURRENT (A)
15
15
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V -55oC 25oC 150oC
10 3V
10
5
5
2V 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 6
0
0
1
2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V)
6
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
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RFW2N06RLE Typical Performance Curves
1.50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 2A
Unless Otherwise Specified (Continued)
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 2A
2.0
1.25
1.5
1.00
1.0
0.75
0.5
0.50 4.0
4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V)
7.0
0 -50
0
50
100
150
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON VOLTAGE vs GATE VOLTAGE
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
NORMALIZED GATE THRESHOLD VOLTAGE
1.50 VGS = VDS, ID = 250A 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
1.50 ID = 250A
1.25
1.00
1.00
0.75
0.75
0.50
0.25 -50
0
50
100
150
0.50 -50
0
50
100
150
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
60 VDS, DRAIN TO SOURCE VOLTAGE (V) RL = 30 IG(REF) = 0.5mA VGS = 5V 45 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS VDD = BVDSS GATE SOURCE VOLTAGE 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 10 VGS, GATE TO SOURCE VOLTAGE (V)
1200 C, CAPACITANCE (pF)
900
30
5
600
CISS
300
COSS CRSS
15
VDD = BVDSS DRAIN SOURCE VOLTAGE 0 I 20 G(REF) IG(ACT) t, TIME (s) I 80 G(REF) IG(ACT)
0 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V)
0
NOTE: Refer to Harris Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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RFW2N06RLE Test Circuits and Waveforms
tON td(ON) RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
VDS
90%
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 13. SWITCHING TIME TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 15. GATE CHARGE TEST CIRCUIT
FIGURE 16. GATE CHARGE WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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