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4 MEG x 16 FPM DRAM
DRAM
MT4LC4M16F5
For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html
FEATURES
* Single +3.3V 0.3V power supply * Industry-standard x16 pinout, timing, functions, and packages * 12 row, 10 column addresses * High-performance CMOS silicon-gate process * All inputs, outputs and clocks are LVTTL-compatible * FAST PAGE MODE (FPM) access * 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
PIN ASSIGNMENT (Top View) 50-Pin TSOP
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC A11 A10 A9 A8 A7 A6 VSS
OPTIONS
* Plastic Package 50-pin TSOP (400 mil) * Timing 50ns access 60ns access * Refresh Rate Standard Refresh
Part Number Example
MARKING
TG
-5 -6
None
MT4LC4M16F5TG-5
KEY TIMING PARAMETERS
SPEED -5 -6
tRC 90ns 110ns tRAC
50ns 60ns
tPC 30ns 35ns
tAA 25ns 30ns
tCAC
13ns 15ns
NOTE: 1. The # symbol indicates signal is active LOW.
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 rowaddress bits (A0-A11) and 10 column-address bits (A0A9). In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) are such that the internal
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data are such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the RAS# signal, then the column address by CAS#. The device provides FASTPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row. The MT4LC4M16F5 must be refreshed periodically in order to retain stored data.
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4 MEG x 16 FPM DRAM
FAST PAGE MODE ACCESS
Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). General byte and word access timing is shown in Figures 1 and 2. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. The WE# signal must be activated to execute a WRITE operation; otherwise a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation.
FUNCTIONAL BLOCK DIAGRAM MT4LC4M16F5 (12 row addresses)
WE#
CASL# CASH#
CAS# DATA-IN BUFFER
16
DQ0DQ15
NO. 2 CLOCK GENERATOR
DATA-OUT BUFFER
16
OE#
16
10
COLUMNADDRESS BUFFER(10) REFRESH CONTROLLER
16
10
COLUMN DECODER
1,024
SENSE AMPLIFIERS I/O GATING
1,024 x 16
A0A11
REFRESH COUNTER
ROW SELECT
12 12 ROWADDRESS BUFFERS (12)
ROW DECODER
COMPLEMENT SELECT
12
4,096
4,096 x 16
4,096 x 1,024 x 16 MEMORY ARRAY
RAS#
NO. 1 CLOCK GENERATOR
VDD VSS
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4 MEG x 16 FPM DRAM
DRAM REFRESH
The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all rows in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC4M16F5 internally refreshes one row for every CBR cycle, so executing 4,096 CBR cycles covers all rows. The CBR REFRESH will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.
WORD WRITE RAS#
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE (DQ0-DQ7) OF WORD
STORED DATA 1 1 0 1 1 1 1 1
INPUT DATA 0 0 1 0 0 0 0 0
INPUT DATA
STORED DATA 0 0 1 0 0 0 0 0
STORED DATA 0 0 1 0 0 0 0 0
INPUT DATA 1 1 0 1 1 1 1 1
INPUT DATA
STORED DATA 1 1 0 1 1 1 1 1
UPPER BYTE (DQ8-DQ15) OF WORD
0 1 0 1 0 0 0 0
X X X X X X X X ADDRESS 0
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 1 1
X X X X X X X X ADDRESS 1
1 0 1 0 1 1 1 1
X = NOT EFFECTIVE (DON'T CARE)
Figure 1 WORD and BYTE WRITE Example
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
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4 MEG x 16 FPM DRAM
WORD READ RAS# LOWER BYTE READ
CASL#
CASH#
WE#
STORED DATA 1
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
OUTPUT DATA 1 1 0 1 1 1 1 1 Z Z Z Z Z Z Z Z
STORED DATA 1 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0
LOWER BYTE (DQ0-DQ7) OF WORD
1 0 1 1 1 1 1 0 1
UPPER BYTE (DQ8-DQ15) OF WORD
0 1 0 0 0 0
ADDRESS 0 Z = High-Z
ADDRESS 1
Figure 2 WORD and BYTE READ Example
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4 MEG x 16 FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ................................................... 1W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6) (VCC = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN (0V VIN VCC + 0.3V); All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA OUTPUT LOW VOLTAGE: IOUT = 2mA OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V VOUT VCC + 0.3V); DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II MIN 3 2 -0.3 -2 MAX 3.6 VCC + 0.3 0.8 2 UNITS NOTES V V V A 37 37
VOH VOL IOZ
2.4 - -5
- 0.4 5
V V A
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V 0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# VCC - 0.2V; DQs may be left open; Other inputs: VIN VCC - 0.2V or VIN 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS# ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN])
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
SYMBOL SPEED MAX IDD1 ALL 1
UNITS NOTES mA
IDD2
ALL -5 -6 -5 -6 -5 -6 -5 -6
500 150 165 105 95 150 165 150 165
A
IDD3
mA
25
IDD4
mA
25
IDD5
mA
22
IDD6
mA
4, 7
5
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4 MEG x 16 FPM DRAM
CAPACITANCE
(Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI1 CI2 CIO MAX 5 7 7 UNITS pF pF pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z CAS# precharge time (FAST PAGE MODE) Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOFF tORD tPC tPRWC tRAC tRAD tRAH
-6 MAX 25 MIN 45 0 0 55 13 15 10 15 15 5 3 10 5 60 5 40 15 10 0 3 15 13 3 0 35 85 15 10 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 40 0 0 48 8 13 15 5 3 8 5 50 5 36 13 8 0 3 13 3 0 30 76 13 8
26 18 28 26 32, 34 4, 27 29 26, 28 13, 32 27 27 27 4, 26 18, 26 28 19, 28 19, 28 23, 24, 36 20 24 17, 23, 28 30 30 15
10,000
30
35
13 13
15 15
50
60
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
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4 MEG x 16 FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 13) (VCC = +3.3V 0.3V)
AC CHARACTERISTICS PARAMETER RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 50 50 90 18 0 0 30 0 0 13 131 73 13 2 8 40 0 8 10 10 MAX 10,000 125,000 MIN 60 60 110 20 0 0 40 0 0 15 155 85 15 2 10 45 0 10 10 10 -6 MAX 10,000 125,000 UNITS ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
64
64
14, 26 16, 27 26 22
16 35 18
50
50
35 18, 26
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
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4 MEG x 16 FPM DRAM
NOTES
1. 2. 3. All voltages referenced to VSS. This parameter is sampled. VCC = +3.3V; f = 1 MHz. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. An initial pause of 100s is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 5ns. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. If CAS# = VIH, data output is High-Z. If CAS# = VIL, data output may contain data from the last valid READ cycle. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. RAS#-ONLY REFRESH requires that all 4,096 rows be refreshed at least once every 64ms. CBR REFRESH requires that at least 4,096 cycles be completed every 64ms. 23. The DQs go High-Z during READ cycles once tOD or tOFF occur. If CAS# goes HIGH before OE#, the DQs will go High-Z regardless of the state of OE#. If CAS# stays LOW while OE# is brought HIGH, the DQs will go High-Z. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. The first CASx# edge to transition LOW. 27. The last CASx# edge to transition HIGH. 28. Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 29. Last falling CASx# edge to first rising CASx# edge.
4. 5.
6.
7. 8.
9.
10. 11. 12. 13.
14.
15.
16. 17.
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4 MEG x 16 FPM DRAM
NOTES (continued)
30. Last rising CASx# edge to next cycle's last rising CASx# edge. 31. Last rising CASx# edge to first falling CASx# edge. 32. First DQs controlled by the first CASx# to go LOW. 33. Last DQs controlled by the last CASx# to go HIGH. 34. 35. 36. 37. Each CASx# must meet minimum pulse width. Last CASx# to go LOW. All DQs controlled, regardless CASL# and CASH#. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
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4 MEG x 16 FPM DRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRRH tRP
RAS#
CAS#
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ tOFF
V DQ V IOH IOL
OPEN
VALID DATA
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD tOE
-6 MAX 25 MIN 45 0 0 13 15 10 15 5 3 5 13 13 60 3 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tRAC
tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 3 13 8 50 90 18 0 0 30 0 13 MAX 13 50 MIN 3 15 10 60 110 20 0 0 40 0 15
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 5 3 5 50 3
10,000
10,000
10,000
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4 MEG x 16 FPM DRAM
EARLY WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRP
RAS#
CAS#
ROW
COLUMN tCWL tRWL tWCS tWCR tWCH tWP
ROW
WE#
V IH V IL tDS tDH
V DQ V IOH IOL
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAR
tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS tRAD
-6 MAX MIN 45 0 0 10 10,000 15 5 5 60 15 10 0 15 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 8 50 90 18 30 13 13 8 40 0 8 10,000 MAX MIN 10 60 110 20 40 15 15 10 45 0 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 5 5 50 13 8 0 13
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
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4 MEG x 16 FPM DRAM
READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS#
tCRP V IH V IL tAR tRAD tRAH
tRCD
CAS#
tASR ADDR V IH V IL
tASC
tCAH
ROW
COLUMN tRWD tCWD tAWD tCWL tRWL tWP
ROW
tRCS
WE#
V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH
V DQ V IOH IOL
OPEN
VALID D IN tOEH
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 55 13 15 10 15 5 3 5 60 40 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD
tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP
-5 MIN 3 13 50 13 8 50 18 0 30 13 131 73 13 8 10,000 15 10 60 20 0 40 15 155 85 15 10 MAX 13 13 15 MIN 3
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 48 8 13 5 3 5 50 36 13 8 0
10,000
10,000
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4 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ROW
COLUMN
COLUMN tRCS tRCH
COLUMN tRCS
ROW tRRH
tRCS WE# V IH V IL
tRCH
tRCH
tAA tRAC tCAC tCLZ DQ V IOH V IOL OPEN tOE V IH V IL VALID DATA tOD tOFF tCLZ
tAA tCPA tCAC tOFF tCLZ VALID DATA tOD
tAA tCPA tCAC tOFF
tOE
tOE
VALID DATA tOD
OPEN
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tOD
-6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 5 3 10 30 35 5 60 13 3 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE
tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 3 30 13 8 50 18 0 0 30 0 13 125,000 MAX 13 13 50 15 10 60 20 0 0 40 0 15 MIN 3 35
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 5 3 8 5 50 3
125,000
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4 MEG x 16 FPM DRAM
FAST-PAGE-MODE EARLY WRITE CYCLE
tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CAS#
ROW
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
COLUMN tCWL tWCH tWP
ROW
tWCS
tWCS
tWCS
WE#
V IH V IL tDS tWCR tDH tDS tDH tDS tRWL tDH
V DQ V IOH IOL V IH V IL
VALID DATA
VALID DATA
VALID DATA
OE#
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAR tASC
tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS
-6 MAX MIN 45 0 0 10 15 5 10 5 60 15 10 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tPC tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP
-5 MIN 30 13 8 50 18 30 13 13 8 40 0 8 125,000 MAX MIN 35 15 10 60 20 40 15 15 10 45 0 10
-6 MAX UNITS ns ns ns 125,000 ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 5 8 5 50 13 8 0
10,000
10,000
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
14
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tRAH tRCD tCAS NOTE 1 tCP tPC tPRWC tCAS tRSH tCP tCAS tCP tRP
RAS#
CAS#
tASR ADDR V IH V IL
tASC
tCAH
tASC
tCAH
tASC
tCAH
ROW
COLUMN tRWD tRCS tCWL tWP tAWD tCWD
COLUMN
COLUMN tRWL tCWL tAWD tCWD tWP
ROW
tCWL tWP tAWD tCWD
WE#
V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ
VALID D OUT VALID DIN VALID D OUT VALID D IN
tAA tDH tDS tCPA tCAC tCLZ
VALID D OUT VALID D IN
tDH tDS
DQ
V IOH V IOL
OPEN
OPEN
tOD tOE OE# V IH V IL tOE
tOD tOE
tOD tOEH
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA tAR
tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH
-6 MAX 25 MIN 45 0 0 55 13 15 10 10,000 15 5 3 10 30 35 5 60 40 15 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tDS tOD tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP
-5 MIN 0 3 13 30 76 50 13 8 50 18 0 30 13 73 13 8 125,000 15 10 60 20 0 40 15 85 15 10 13 13 MAX MIN 0 3 15 35 85
-6 MAX 15 15 UNITS ns ns ns ns ns ns 60 ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 48 8 13 5 3 8 5 50 36 13 8
125,000
NOTE: 1. tPC is for LATE WRITE only.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 FPM DRAM
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP V IH V IL t RSH t CSH t CRP CAS# V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC t CAH t ASC t CAH t RCD t CAS t CP t PC t CAS t CP t RP
RAS#
ROW
COLUMN
COLUMN t CWL
ROW
t RCS t WCS WE# V IH V IL t CAC t CLZ V OH V OL NOTE 1 t OFF t DS VALID DATA t AA t RAC
t RWL t WP t WCH
t DH
DQ
OPEN
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 3 10 5 60 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP
-5 MIN 3 30 13 8 50 18 0 30 13 13 8 0 8 125,000 MAX 13 50 15 10 60 20 0 40 15 15 10 0 10 MIN 3 35
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 3 8 5 50 13 8 0
125,000
NOTE: 1. Do not drive input data prior to output data going High-Z.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 FPM DRAM
RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON'T CARE)
tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP
RAS#
CAS#
ROW
ROW
V DQ V OH OL
OPEN
CBR REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS
DQ
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tASR tCHR tCP tCRP tCSR tRAH
-6 MAX MIN 0 15 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC
tRP tRPC tWRH tWRP
-5 MIN 50 90 30 0 10 10 MAX 10,000 MIN 60 110 40 0 10 10
-6 MAX 10,000 UNITS ns ns ns ns ns ns
MIN 0 15 8 5 5 8
NOTE: 1. End of first CBR REFRESH cycle.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
17
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 FPM DRAM
HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW)
tRC tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS
CASL#/CASH#
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ tOFF
DQx
V IOH V IOL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
tORD
DON'T CARE UNDEFINED
TIMING PARAMETERS
-5 SYMBOL
tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD
-6 MAX 25 MIN 45 0 0 13 15 10 15 3 5 3 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tOFF tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH
-5 MIN 3 0 50 13 8 50 18 30 13 10,000 15 10 60 20 40 15 MAX 13 13 MIN 3 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 15 3 5 3
10,000
13
15
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
18
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.
4 MEG x 16 FPM DRAM
50-PIN PLASTIC TSOP (400 mil)
21.04 20.88 .88 TYP 50
11.86 11.66
10.21 10.11
SEE DETAIL A
1 .80 TYP
25 .45 .30 .18 .13
PIN #1 ID
.25 GAGE PLANE .10 1.2 MAX
.20 .25
.60 .40
DETAIL A
.80 TYP
NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
4 Meg x 16 FPM DRAM D28_2.p65 - Rev. 5/00
19
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.

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