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W79E201 Data Sheet 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATION ............................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 7 MEMORY ORGANIZATION ....................................................................................................... 8 INSTRUCTION.......................................................................................................................... 32 8.1 Instruction Timing ......................................................................................................... 32 POWER MANAGEMENT.......................................................................................................... 38 INTERRUPTS ........................................................................................................................... 41 PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 42 11.1 11.2 12. 13. Timer/Counters 0 & 1.................................................................................................... 42 Timer/Counter 2............................................................................................................ 45
WATCHDOG TIMER................................................................................................................. 48 SERIAL PORT .......................................................................................................................... 51 13.1 13.2 Framing Error Detection ............................................................................................... 56 Multiprocessor Communications .................................................................................. 56
14. 15. 16. 17. 18.
PULSE WIDTH MODULATED OUTPUTS (PWM) ................................................................... 58 ANALOG-TO-DIGITAL CONVERTER ...................................................................................... 60 TIMED ACCESS PROTECTION .............................................................................................. 63 H/W REBOOT MODE (BOOT FROM 4K BYTES OF LD FLASH EPROM)............................. 64 IN-SYSTEM PROGRAMMING ................................................................................................. 65 18.1 18.2 The Loader Program Locates at LD Flash EPROM Memory....................................... 65 The Loader Program Locates at AP Flash EPROM Memory....................................... 65
19. 20. 21.
H/W WRITER MODE ................................................................................................................ 65 SECURITY BITS ....................................................................................................................... 66 THE PERFORMANCE CHARACTERISTIC OF ADC .............................................................. 67 21.1 21.2 The Differential Nonlinearity VS Output code............................................................... 67 The Integral Nonlinearity VS Output code .................................................................... 68 Publication Release Date: December 16, 2004 Revision A2
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W79E201
22. 23. THE EMBEDDED ICE WITH JTAG INTERFACE .................................................................... 68 ELECTRICAL CHARACTERISTICS......................................................................................... 69 23.1 23.2 23.3 23.4 24. 25. 26. 27. Absolute Maximum Ratings .......................................................................................... 69 DC Characteristics........................................................................................................ 69 ADC DC Electrical Characteristics ............................................................................... 71 AC Characteristics ........................................................................................................ 71
TYPICAL APPLICATION CIRCUITS ........................................................................................ 77 PACKAGE DIMENSIONS ......................................................................................................... 79 APPLICATION NOTE ............................................................................................................... 81 REVISION HISTORY ................................................................................................................ 87
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W79E201
1. GENERAL DESCRIPTION
The W79E201 is a fast 8051 compatible microcontroller with a redesigned processor core without wasted clock and memory cycles. The W79E201 contains In-System Programmable (ISP) 16 KB AP Flash EPROM; 4KB LD Flash EPROM for loader program; a 256 bytes of RAM; one 8-bit digital or analog input port (Port 1); three 8-bit bi-directional and bit-addressable I/O ports; an 1-bit port P4.0 for external ISP reboot used; three 16-bit timer/counters; one serial ports. These peripherals are supported by 8 sources two-level interrupt capability. To facilitate programming and verification, the FLASH EPROM inside the W79E201 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W79E201 is added 10-bit ADC with an 8 channel analog input with digital input port. Furthermore, the W79E201A16LN, packaged in 48-pin LQFP, supports the in circuit emulation (ICE) function with JTAG interface to the development tool. The W79E201 executes every 8051 instruction faster than the original 8051 for the same crystal speed. Typically, the instruction executing time of W79E201 is 1.5 to 3 times faster than that of traditional 8051, depending on the type of instruction. In general, the overall performance is about 2.5 times better than the original for the same crystal speed. Giving the same throughput with lower clock speed, power consumption has been improved. Consequently, the W79E201 is a fully static CMOS design; it can also be operated at a lower crystal clock.
2. FEATURES
* * * * * * * * * * * * * * * * Fully static design 8-bit Turbo 51 CMOS microcontroller up to 16MHz 16K bytes of in-system-programmable Flash EPROM (AP Flash EPROM) 4KB Auxiliary Flash EPROM for loader program (LD Flash EPROM) 256 bytes of on-chip RAM Instruction-set compatible with MSC-51 On-chip debug function with JTGA interface to development tool Three 8-bit bi-directional ports Three 16-bit timer/counters 8 interrupt source with two levels of priority One enhanced full duplex serial port with framing error detection and automatic address recognition Port 0 internal pull-up resistor optional Programmable Watchdog Timer 6 channel PWM Software programmable access cycle to external RAM/peripherals 10-bits ADC with 8 channel analog input or digital input port (At least 8-bits resolution guaranteed) Packages: - - - PLCC 44: W79E201A16PN QFP 44: W79E201A16FN LQFP 48: W79E201A16LN
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Publication Release Date: December 16, 2004 Revision A2
W79E201
3. PIN CONFIGURATION
48-Pin LQFP
P 2 . 2 , A 1 0 P 2 . 1 , A 9 P 2 . X T 0 , TTTTPVA 4 A DDMC. S L 8OI SK0S1 X T A L 2 P 3 . 7 ,
/ R D
P2.3, A11 P2.4, A12 P2.5, A13 P2.6, A14 P2.7, A15 PSEN ALE EA P0.7, AD7 P0.6, AD6 P0.5, AD5 P0.4, AD4
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27
P3.6, WR P3.5, T1 P3.4, T0 P3.3, INT1 P3.2, INT0 P3.1, TXD P3.0, RXD RESET P1.7 P1.6 P1.5 P1.4
W79E201A16LN
10 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P 0 . 3 , A D 3 P 0 . 2 , A D 2 P .0 1 , A D 1 PVVVV 0 r . DSDe 0DSD AAf , A D 0 P 1 . 0 P 1 . 1 P 1 . 2 P 1 . 3
44-Pin PLCC
44-Pin QFP
A D 0 , PPPPVVV P 1 1 1 1r DSV 0 . . . . e DSD. 3210f AAD0 A D 1 , P 0 . 1 A D 2 , P 0 . 2
A D 0 , P P P PP VVV 1 1 11 r DSV0 . . . . eDSD. 3210 fAAD0 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
A D 1 , P 0 . 1
A D 2 , P 0 . 2 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 1 2
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 W79E201A16PN 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS.. L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 6 W79E201A16FN 28 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS.. L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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W79E201
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EA
IH
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within 16KB area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. Digital GROUND: Ground potential Digital POWER SUPPLY: Supply voltage for operation. Analog POWER SUPPLY: Supply analog voltage for operation. GROUND: Analog Ground potential Vref: Analog reference input maximum voltage for ADC
PSEN
OH
ALE RST XTAL1 XTAL2 VSS VDD AVDD AVSS Vref
OH IL I O P P P P P
PORT 0: Port 0 is an open-drain bi-directional I/O port with internal pull-up resister option that is enabled by setting bit 0 of P0R(8Fh) to logic high. This P0.0-P0.7 I/O D(H) port also provides a multiplexed low order address/data bus during accesses to external memory. P1.0-P1.7 P2.0-P2.7 P3.0-P3.7 P4.0 TCK TMS TDI TDO I I/O I/O I/O IL IH IH O PORT 1: Port 1 is an input port. Or with an 8-bit analog input port for ADC0ADC7(8 analog input channels) used. PORT 2: Port 2 is a bi-directional I/O port with internal weakly pull-ups. This port also provides the upper address bits for accesses to external memory. PORT 3: Port 2 is a bi-directional I/O port with internal weakly pull-ups. Function is the same as that of the standard 8052. PORT 4: A bi-directional I/O port with internal with weakly pull-ups TCK: JTAG test clock TMS: JTAG Test Mode select TDI: JTAG Test Data In TDO: JTAG Test Data Out
* Note: TYPE P: Power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
5. BLOCK DIAGRAM
P1.0 P1.7
Port 1
Port 1 Latch ADC
ACC
B
T2 Register
Port 0 Latch
Port 0
P0.0 P0.7
T1 Register Interrupt PSW Timer 2 Timer 0
DPTR
ALU
Stack Pointer Temp Reg.
PC
Incrementor
Address Bus
SFR RAM Address
Timer 1
Instruction Decoder & Sequencer
Addr. Reg.
1 UART
256 bytes RAM & SFR
Flash EPROM
P3.0 P3.7 P4.0
Port 3
Port 3 Latch Port 4 Latch
Bus & lock Controller
Port 2 Latch
Port 2
P2.0 P2.7
Port 4
Oscillator
Reset Block
Watchdog Timer
Power control & Power monitor
XTAL1 XTAL2
ALE PSEN
RST
VCC
GND
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W79E201
6. FUNCTIONAL DESCRIPTION
The W79E201 is not pin compatible with 8052 but the instruction set is compatible. It includes the resources of the standard 8052 such as three 8-bit I/O Ports, one 8-bit digital or analog input port, three 16-bit timer/counters, one full duplex serial port and interrupt sources. The W79E201 features a faster running and better performance 8-bit CPU with a redesigned core processor without wasted clock and memory cycles. it improves the performance not just by running at high frequency but also by reducing the machine cycle duration from the standard 8052 period of twelve clocks to four clock cycles for the majority of instructions. This improves performance by an average of 1.5 to 3 times. It can also adjust the duration of the MOVX instruction (access to off-chip data memory) between two machine cycles and nine machine cycles. This flexibility allows the W79E201 to work efficiently with both fast and slow RAMs and peripheral devices. The W79E201 is an 8052 compatible device that gives the user the features of the original 8052 device, but with improved speed and power consumption characteristics. It has the same instruction set as the 8051 family. While the original 8051 family was designed to operate at 12 clock periods per machine cycle, the W79E201 operates at a much reduced clock rate of only 4 clock periods per machine cycle. This naturally speeds up the execution of instructions. Consequently, the W79E201 can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since the W79E201 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving the same throughput in terms of instruction execution, yet reducing the power consumption. The 4 clocks per machine cycle feature in the W79E201 is responsible for a three-fold increase in execution speed. The W79E201 has all the standard features of the 8052, and has a few extra peripherals and features as well. I/O Ports The W79E201 has one 8-bit digital or analog input port, Three 8-bit I/O ports and one extra 1-bit port at P4.0. Port 0 can be used as an Address/Data bus when external program is running or external memory/device is accessed by MOVC or MOVX instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong pull-ups and pull-downs when it serves as an address bus. Port 1 is only input port which can be selected to 8-channel analog input pins of ADC. Port 3 act as I/O ports with alternate functions. Port 4.0 serves as a general purpose I/O port as Port 3. Serial I/O The W79E201 has one enhanced serial port that is functionally similar to the serial port of the original 8052 family. However the serial port on the W79E201 can operate in different modes in order to obtain timing similarity as well. The serial port has the enhanced features of Automatic Address recognition and Frame Error detection. Timers The W79E201 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the user with the option of operating in a mode that emulates the timing of the original 8052. The W79E201 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as a very long time period timer.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Interrupts The Interrupt structure in the W79E201 is slightly different from that of the standard 8052. Due to the presence of additional features and peripherals, the number of interrupt sources and vectors has been increased. The W79E201 provides 8 interrupt resources with two priority levels, including 2 external interrupt sources, 3 timer interrupts, 1 serial I/O interrupt, 1 ADC interrupt and 1 watch dog timer interrupt. Power Management Like the standard 80C52, the W79E201 also has IDLE and POWER DOWN modes of operation. In the POWER DOWN mode, all of the clocks of peripheral are stopped and the chip operation is completely stopped. This is the lowest power consumption state.
7. MEMORY ORGANIZATION
The W79E201 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for memory mapped devices. Program Memory The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. All instructions are fetched for execution from this memory area. The MOVC instruction can also access this memory region. There is an auxiliary 4KB Flash EPROM bank (LD Flash EPROM) resided user loader program for In-System Programming (ISP). The AP Flash EPROM allows serial or parallel download according to user loader program in LD Flash EPROM. Data Memory The W79E201 can access up to 64Kbytes of external Data Memory. This memory region is accessed by the MOVX instructions. Any MOVX directed to the space between 0000H and FFFFH goes to the expanded bus on Port 0 and 2. This is the default condition. In addition, the W79E201 has the standard 256 bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing. There are also some Special Function Registers (SFRs), which can only be accessed by direct addressing. Since the Scratchpad RAM is only 256 bytes, it can be used only when data contents are small.
FFh
Indirect Addressing RAM Direct & Indirect Addressing RAM
80h 7Fh
SFRs Direct Addressing
FFFFh
00h
64K Bytes External Data Memory 3FFFh
16K Bytes On-Chip Program Memory AP Flash EPROM 4K Bytes LD Flash EPROM
0FFFh
0000h
Memory Map
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W79E201
Special Function Registers The W79E201 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or 8. The W79E201 contains all the SFRs present in the standard 8052. However, some additional SFRs have been added. In some cases unused bits in the original 8052 have been given new functions. The list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate that there are no registers at these addresses. When a bit or register is not implemented, it will read high. Table 1. Special Function Register Location Table F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 CKCON P0R PCON SBUF SADDR SFRAL SFRAH P4 CHPCON SFRFD SFRCN SADEN EIP B EIE ACC WDCON PSW T2CON T2MOD RCAP2L RCAP2H PWM5 TL2 PMR TH2 Status PWMCON 2 PWM4 TA ADCCON PWMP ADCH PWM0 PWM1 ADCCEN PWMCON 1 PWM2 PWM3
Note: The SFRs in the column with dark borders are bit-addressable.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Port 0
Bit: 7 P0.7 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0
Mnemonic: P0
Address: 80h
Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.
Stack Pointer
Bit: 7 SP.7 6 SP.6 5 SP.5 4 SP.4 3 SP.3 2 SP.2 1 SP.1 0 SP.0
Mnemonic: SP
Address: 81h
The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it always points to the top of the stack.
Data Pointer Low
Bit: Mnemonic: DPL 7 DPL.7 6 DPL.6 5 DPL.5 4 DPL.4 3 DPL.3 2 DPL.2 1 DPL.1 0 DPL.0
Address: 82h
This is the low byte of the standard 8052 16-bit data pointer.
Data Pointer High
Bit: 7 DPH.7 6 DPH.6 5 DPH.5 4 DPH.4 3 DPH.3 2 DPH.2 1 DPH.1 0 DPH.0
Mnemonic: DPH
Address: 83h
This is the high byte of the standard 8052 16-bit data pointer.
Power Control
Bit: 7 SM0D 6 SMOD0 5 4 3 GF1 2 GF0
Address: 87h
1 PD
0 IDL
Mnemonic: PCON
BIT
NAME
FUNCTION
7 6 5
1: This bit doubles the serial port baud rate in mode 1, 2, and 3. 0: Framing Error Detection Disable. SCON.7 acts as per the standard 8052 function. SMOD0 1: Framing Error Detection Enable, then and SCON.7 indicates a Frame Error and acts as the FE flag. Reserve
SMOD
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W79E201
Continued
BIT
NAME
FUNCTION
4 3 2 1
GF1 GF0 PD
0
IDL
Reserve General purpose user flag. General purpose user flag. 1: Setting this bit causes the Chip to go into the POWER DOWN mode. In this mode all the clocks are stopped and program execution is frozen. 1: Setting this bit causes the Chip to go into the IDLE mode. In this mode the clocks to the CPU are stopped, so program execution is frozen. But the clock to the serial port, ADC, timer and interrupt blocks is not stopped, and these blocks continue operating.
Timer Control
Bit: 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1
Address: 88h
1 IE0
0 IT0
Mnemonic: TCON
BIT
NAME
FUNCTION
7 6 5 4 3 2 1 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear this bit. Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off. Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when the program does a timer 0 interrupt service routine. Software can also set or clear this bit. Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off. Interrupt 1 Edge Detect: Set by hardware when an edge/level is detected on INT1 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. Interrupt 0 Edge Detect: Set by hardware when an edge/level is detected on INT0 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Timer Mode Control
Bit: 7 GATE
Mnemonic: TMOD
6
C/ T
5 M1
4 M0
3 GATE
2
C/ T
1 M1
0 M0
Address: 89h
BIT
NAME
FUNCTION
7 6 5 4 3 2 1 0
GATE
Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. Mode Select bit. Mode Select bit. Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. Mode Select bit. Mode Select bit.
C/ T
M1 M0 GATE
C/ T
M1 M0
M1, M0: Mode Select bits:
M1 M0 MODE
0 0 1 1
0 1 0 1
Mode 0: 8-bits with 5-bit prescale. Mode 1: 18-bits, no prescale. Mode 2: 8-bits with auto-reload from THx Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/counter is stopped.
Timer 0 LSB
Bit: 7 TL0.7 6 TL0.6 5 TL0.5 4 TL0.4 3 TL0.3 2 TL0.2 1 TL0.1 0 TL0.0
Mnemonic: TL0
Address: 8Ah
TL0.7-0: Timer 0 LSB
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W79E201
Timer 1 LSB
Bit: 7 TL1.7 6 TL1.6 5 TL1.5 4 TL1.4 3 TL1.3 2 TL1.2 1 TL1.1 0 TL1.0
Mnemonic: TL1
Address: 8Bh
TL1.7-0: Timer 1 LSB
Timer 0 MSB
Bit: 7 TH0.7 6 TH0.6 5 TH0.5 4 TH0.4 3 TH0.3 2 TH0.2 1 TH0.1 0 TH0.0
Mnemonic: TH0
Address: 8Ch
TH0.7-0: Timer 0 MSB
Timer 1 MSB
Bit: 7 TH1.7 6 TH1.6 5 TH1.5 4 TH1.4 3 TH1.3 2 TH1.2 1 TH1.1 0 TH1.0
Mnemonic: TH1
Address: 8Dh
TH1.7-0: Timer 1 MSB
Clock Control
Bit: 7 WD1 6 WD0 5 T2M 4 T1M 3 T0M 2 MD2 1 MD1 0 MD0
Mnemonic: CKCON
Address: 8Eh
BIT
NAME
FUNCTION
Watchdog timer mode select bit 1: 7 WD1 These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time-out period. Watchdog timer mode select bit 0: 6 WD0 These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time-out period. Timer 2 clock select: 5 T2M When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock.
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W79E201
Continued
BIT
NAME
FUNCTION
Timer 1 clock select: 4 T1M When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to 0 it uses a divide by 12 clock. Timer 0 clock select: 3 T0M When T0M is set to 1, timer 0 uses a divide by 4 clock, and When set to 0 it uses a divide by 12 clock. Stretch MOVX select bit 2: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected. Stretch MOVX select bit 1: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected. Stretch MOVX select bit 0: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external circuits. The RD or WR strobe will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch setting. By default, the stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be selected.
2
MD2
1
MD1
0
MD0
WD1
WD0
INTERRUPT TIME-OUT
RESET TIME-OUT
0 0 1 1
0 1 0 1
2 2 2
17
2 2 2 2
17 20 23 26
+ 512 + 512 + 512 + 512
220
23 26
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W79E201
MD2
MD1
MD0
STRETCH VALUE
MOVX DURATION
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7
2 machine cycles 3 machine cycles (Default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles
Port 0 pull-up resister
Bit: 7 6 5 4 3 2 Address: 8Fh
1 -
0 P0UP
Mnemonic: P0R
BIT
NAME
FUNCTION
7~1 0
P0UP
Reserved Port 0 Pull-up resistor 0: No Pull-up resister 1: Pull-up resister(~10K)
Port 1
Bit: 7 P1.7 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General purpose digital input port or analog input port, AD0~AD7. By the digital input port, most instructions will read the port pins in case of a port read access, however in case of read instructions, the port latch is read. The alternate functions are described below:
BIT NAME FUNCTION
1 0
P1.1 P1.0
T2 : External Input for Timer/Counter 2 T2EX : Timer/Counter 2 Capture/Reload Trigger
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Serial Port Control
Bit: 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8
Address: 98h
1 TI
0 RI
Mnemonic: SCON
BIT
NAME
FUNCTION
7
Serial port, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is SM0/FE described below. When used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in software to clear the FE condition. Serial port Mode bit 1: Mode: SM0 SM1 Description 0 0 0 Synchronous 1 0 1 Asynchronous 2 1 0 Asynchronous 3 1 1 Asynchronous Length 8 10 11 11 Baud rate 4/12 Tclk Variable 64/32 Tclk Variable
6
SM1
5
SM2
Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives compatibility with the standard 8052. Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled. This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software as desired. In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0 it has no function. Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. This bit must be cleared by software. Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. However the restrictions of SM2 apply to this bit. This bit can be cleared only by software.
4 3 2 1
REN TB8 RB8 TI
0
RI
Serial Data Buffer
Bit: 7 6 5 4 3 2 1 0 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
Address: 99h
Mnemonic: SBUF
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W79E201
BIT NAME FUNCTION
7~0
SBUF
Serial data on the serial port is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive resister, and the other is the transmit buffer. Any read access gets data from the receive data buffer, while write access is to the transmit data buffer.
ISP Control Register
Bit: 7 SWRST/ REBOOT 6 5 LDAP 4 3 2 1 0 FBOOTSL FPROGEN
Mnemonic: CHPCON
Address: 9Fh
BIT
NAME
FUNCTION
7
SWRST/ Set this bit to launch a whole device reset that is same as asserting high to REBOOT RST pin, micro controller will be back to initial state and clear this bit automatically. To read this bit, its alternate function to indicate the ISP hardware reboot mode is invoking when reading it in high. LDAP Reserved This bit is Read Only. High: device is executing the program in LD Flash EPROM Low: device is executing the program in AP Flash EPROM. Reserved Reserved Reserved
6 5 4 3 2 1 0
FBOOTSL Loader program residence selection. Set to high to route the device fetching code from LD Flash EPROM. FPROGEN In System Programming Mode Enable. Set this bit to launch the ISP mode. Device will operate ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear this bit to disable ISP mode, device get back to normal operation including IDLE state.
Port 2
Bit: 7 P2.7 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0
Mnemonic: P2
Address: A0h
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Port 4
Bit:
Mnemonic: P4
7 -
6 -
5 -
4 -
3 -
2 Address: A5h
1 -
0 P4.0
P4.0: When B3 of security bits is set to logical 0, the P4.0 as reboot pin. When B3 of security bits is set to logical 1, the P4.0 as I/O pin.
Interrupt Enable
Bit: 7 EA 6 EADC 5 ET2 4 ES 3 ET1 2 EX1
Address: A8h
1 ET0
0 EX0
Mnemonic: IE
BIT
NAME
FUNCTION
7 6 5 4 3 2 1 0
EA EADC ET2 ES ET1 EX1 ET0 EX0
Global enable. Enable/disable all interrupts. Enable ADC interrupt. Enable Timer 2 interrupt. Enable Serial Port interrupt. Enable Timer 1 interrupt. Enable external interrupt 1. Enable Timer 0 interrupt. Enable external interrupt 0.
Slave Address
Bit: 7 6 5 4 3 2 1 0 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
Address: A9h
Mnemonic: SADDR
BIT
NAME
FUNCTION
7~0
SADDR
The SADDR should be programmed to the given or broadcast address for serial port to which the slave processor is designated.
ISP Address Low Byte
Bit: 7 6 5 4 3 2 1 0 SFRAL.7 SFRAL.6 SFRAL.5 SFRAL.4 SFRAL.3 SFRAL.2 SFRAL.1 SFRAL.0
Mnemonic: SFRAL Address: ACh
Low byte destination address is for In System Programming operations. SFRAH and SFRAL address are specific ROM bytes for erasure, programming or read. - 18 -
W79E201
ISP Address High Byte
Bit: 7 6 5 4 3 2 1 0 SFRAH.7 SFRAH.6 SFRAH.5 SFRAH.4 SFRAH.3 SFRAH.2 SFRAH.1 SFRAH.0
Mnemonic: SFRAH Address: ADh
High byte destination address is for In System Programming operations. SFRAH and SFRAL address are specific ROM bytes for erasure, programming or read.
ISP Data Buffer
Bit: 7 6 5 4 3 2 1 0 SFRFD.7 SFRFD.6 SFRFD.5 SFRFD.4 SFRFD.3 SFRFD.2 SFRFD.1 SFRFD.0
Mnemonic: SFRFD Address: AEh
In ISP mode, read/write a specific byte ROM content must go through SFRFD register.
ISP Operation Modes
Bit: 7 6 WFWIN 5 OEN 4 CEN 3 CTRL3 2 CTRL2 1 CTRL1 0 CTRL0
Mnemonic: SFRCN
Address: AFh
BIT
NAME
FUNCTION
7 6
WFWIN
Reserve On-chip Flash EPROM bank select for in-system programming. 0: 16K bytes Flash EPROM bank is selected as destination for re-programming. 1: 4K bytes Flash EPROM bank is selected as destination for re-programming. Flash EPROM output is enabled. Flash EPROM chip is enabled.
5 4 3~0
OEN CEN
CTRL[3:0] The flash control signals
SFRAH, SFRAL
ISP MODE
WFWIN
NOE
NCE
CTRL<3:0>
SFRFD
Erase 4KB LD FLASH PROM Erase 16K AP FLASH EPROM Program 4KB LD FLASH EPROM Program 16KBAP FLASH EPROM Read 4KB LD FLASH EPROM Read 16KB AP FLASH EPROM
1 0 1 0 1 0
1 1 1 1 0 0
0 0 0 0 0 0
0010 0010 0001 0001 0000 0000
X X Address in Address in Address in Address in
X X Data in Data in Data out Data out
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Port 3
Bit: 7 P3.7 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0
Mnemonic: P3
Address: B0h
P3.7-0: General purpose I/O port. Each pin also has an alternate input or output function. There alternate functions are described below table.
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
Strobe for read from external RAM
WR Strobe for write to external RAM
T1 Timer/counter 1 external count input T0 Timer/counter 0 external count input
INT1 External interrupt 1 INT0 External interrupt 0
TxD Serial port 0 output RxD Serial port 0 input
Interrupt Priority
Bit:
Mnemonic: IP
7 -
6 PADC
5 PT2
4 PS
3 PT1
2 PX1
Address: B8h
1 PT0
0 PX0
BIT
NAME
FUNCTION
7 6 5 4 3 2 1 0
PADC PT2 PS PT1 PX1 PT0 PX0
This bit is un-implemented and will read high. 1: To set interrupt priority of ADC is highest priority level. 1: To set interrupt priority of Timer 2 is highest priority level. 1: To set interrupt priority of Serial port 0 is highest priority level. 1: To set interrupt priority of Serial port 0 is highest priority level. 1: To set interrupt priority of External interrupt 1 is highest priority level. 1: To set interrupt priority of Timer 0 is highest priority level. 1: To set interrupt priority of External interrupt 0 is highest priority level.
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W79E201
Slave Address Mask Enable
Bit: 7 6 5 4 3 2 1 0 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
Address: B9h
Mnemonic: SADEN
BIT
NAME
FUNCTION
7~0
SADEN
This register enables the Automatic Address Recognition feature of the Serial port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the incoming serial data. When SADEN is 0, then the bit becomes a "don't care" in the comparison. This register enables the Automatic Address Recognition feature of the Serial port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
PWM 5 Register
Bit: 7 6 5 4 3 2 1 0 PWM5.7 PWM5.6 PWM5.5 PWM5.4 PWM5.3 PWM5.2 PWM5.1 PWM5.0
Address: C3h
Mnemonic: PWM 5
Power Management Register
Bit: 7 6 5 4 3 2 ALE-OFF
Address: C4h
1 -
0 -
Mnemonic: PMR
BIT
NAME
FUNCTION
7~3
-
Reserved. This bit disables the expression of the ALE signal on the device pin during all on-board program and data memory accesses. External memory accesses will automatically enable ALE independent of ALE-OFF. 0: ALE expression is enabled. 1: ALE expression is disabled and keep in logic high state.
2
ALE-OFF
1~0
-
Reserved.
Status Register
Bit: 7 6 HIP 5 LIP 4 3 2 1 SPTA0 0 SPRA0
Mnemonic: STATUS
Address: C5h
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Publication Release Date: December 16, 2004 Revision A2
W79E201
BIT
NAME
FUNCTION
7 6
HIP
Reserved. High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. Reserved. Reserved. Reserved. Serial Port 0 Transmit Activity. This bit is set during serial port is currently transmitting data. It is cleared when TI bit is set by hardware. Serial Port 0 Receive Activity. This bit is set during serial port is currently receiving a data. It is cleared when RI bit is set by hardware.
5 4 3 2 1 0
LIP SPTA0 SPRA0
Timed Access
Bit: 7 TA.7 6 TA.6 5 TA.5 4 TA.4 3 TA.3 2 TA.2 1 TA.1 0 TA.0
Mnemonic: TA
Address: C7h
TA: The Timed Access register controls the access to protected bits. To access protected bits, the user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA. Now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits.
Timer 2 Control
Bit: 7 TF2
Mnemonic: T2CON
6 EXF2
5 RCLK
4 TCLK
3 EXEN2
2 TR2
1
C/ T2
0
CP/ RL2
Address: C8h
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W79E201
BIT
NAME
FUNCTION
7
TF2
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is equal to the capture register in down count mode. It can be set only if RCLK and TCLK are both 0. It is cleared only by software. Software can also set or clear this bit. Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 underflow/overflow will cause this flag to set based on the CP/RL2, EXEN2 and DCEN bits. If set by a negative transition, this flag must be cleared by software. Setting this bit in software or detection of a negative transition on T2EX pin will force a timer interrupt if enabled. Receive clock Flag: This bit determines the serial port time-base when receiving data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation, else timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode. Transmit clock Flag: This bit determines the serial port time-base when transmitting data in mode 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud rate clock, else timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode. Timer 2 External Enable: This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin will be ignored, else a negative transition detected on the T2EX pin will result in capture or reload. Timer 2 Run Control: This bit enables/disables the operation of timer 2.halting this will preserve the current count in TH2, TL2. Counter/Timer select: This bit determines whether timer 2 will function as a timer or a counter. Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on T2M bit (CKCON.5), else, it will count negative edges on T2 pin. Capture/Reload Select: This bit determines whether the capture or reload function will be used for timer 2. If either RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1. If this bit is 1, then timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1.
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/ T2
0
CP/ RL2
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Publication Release Date: December 16, 2004 Revision A2
W79E201
Timed 2 Mode Control
Bit: 7 6 5 4 3 T2CR 2 Address: C9h
1 -
0 DCEN
Mnemonic: T2MOD
BIT
NAME
FUNCTION
7~4 3
T2CR
Reserved. Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the capture register. Reserved. Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts in 16-bit auto-reload mode.
2~1 0
DCEN
Timer 2 Capture LSB
Bit: 7 6 5 4 3 2 1 0 RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
Mnemonic: RCAP2L Address: CAh
RCAP2L: This register is used to capture the TL2 value when a timer 2 is configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is configured in autoreload mode.
Timer 2 Capture MSB
Bit: 7 6 5 4 3 2 1 0 RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
Mnemonic: RCAP2H Address: CBh
RCAP2H: This register is used to capture the TH2 value when a timer 2 is configured in capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when timer 2 is configured in auto-reload mode.
Timer 2 LSB
Bit: 7 TL2.7 6 TL2.6 5 TL2.5 4 TL2.4 3 TL2.3 2 TL2.2 1 TL2.1 0 TL2.0
Mnemonic: TL2
Address: CCh
TL2: Timer 2 LSB
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W79E201
Timer 2 MSB
Bit: 7 TH2.7 6 TH2.6 5 TH2.5 4 TH2.4 3 TH2.3 2 TH2.2 1 TH2.1 0 TH2.0
Mnemonic: TH2
Address: CDh
TH2: Timer 2 MSB
PWM 4~5 Control Register 2
Bit: 7 6 5 4 3 2 1 0 PWM5OE PWM4OE ENPWM5 ENPWM4
Address: CEh
Mnemonic: PWMCON2
BIT
NAME
FUNCTION
7~4 3
PWM5OE
Reserved. Output enable for PWM5 0: Disable PWM5 Output. 1: Enable PWM5 Output.
2
PWM4OE
Output enable for PWM4 0: Disable PWM4 Output. 1: Enable PWM4 Output.
1
ENPWM5
Enable PWM5 0: Disable PWM5. 1: Enable PWM5.
0
ENPWM4
Enable PWM4 0: Disable PWM4. 1: Enable PWM4.
PWM 4 Register
Bit: 7 6 5 4 3 2 1 0 PWM4.7 PWM4.6 PWM4.5 PWM4.4 PWM4.3 PWM4.2 PWM4.1 PWM4.0
Address: CFh
Mnemonic: PWM 4
Program Status Word
Bit: 7 CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0 P
Mnemonic: PSW
Address: D0h
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Publication Release Date: December 16, 2004 Revision A2
W79E201
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV F1 P
Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations. Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble. User flag 0: The General purpose flag that can be set or cleared by the user. Register bank select bits: Register bank select bits: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous operation, or vice-versa. User Flag 1: The General purpose flag that can be set or cleared by the user by software. Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
RS.1-0: Register bank select bits:
RS1 RS0 REGISTER BANK ADDRESS
0 0 1 1
0 1 0 1
0 1 2 3
00-07h 08-0Fh 10-17h 18-1Fh
Watchdog Control
Bit: 7 6 POR 5 4 3 WDIF 2 WTRF 1 EWT 0 RWT
Mnemonic: WDCON
Address: D8h
BIT
NAME
FUNCTION
7 6 5 4 3
POR WDIF
Reserved. Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read or written by software. A write by software is the only way to clear this bit once it is set. Reserved. Reserved. Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. This bit must be cleared by software. Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no affect on this bit. - 26 -
2
WTRF
W79E201
Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function. Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
1
EWT
0
RWT
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1 by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets. All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA register description. TA WDCON CKCON EG REG REG MOV MOV ORL MOV MOV ORL C7H D8H 8EH TA, #AAH TA, #55H ; Reset watchdog timer ; Select 26 bits watchdog timer CKCON, #11000000B TA, #AAH TA, #55H WDCON, #00000010B ; Enable watchdog
SETB WDCON.0
PWM Prescale Register
Bit: 7 6 5 4 3 2 1 0 PWMP.7 PWMP.6 PWMP.5 PWMP.4 PWMP.3 PWMP.2 PWMP.1 PWMP.0
Address: D9h
Mnemonic: PWMP
PWM 0 Register
Bit: 7 6 5 4 3 2 1 0 PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0
Address: DAh
Mnemonic: PWM0
PWM 1 Register
Bit: 7 6 5 4 3 2 1 0 PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0
Address: DBh
Mnemonic: PWM1
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Publication Release Date: December 16, 2004 Revision A2
W79E201
PWM 0~3 Control Register 1
Bit: 7 6 5 4 3 2 1 0 PWM3OE PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENPWM0
Address: DCh
Mnemonic: PWMCON1
BIT
NAME
FUNCTION
7
PWM3OE
6
PWM2OE
5
ENPWM3
4
ENPWM2
3
PWM1OE
2
PWM0OE
1
ENPWM1
0
ENPWM0
Output enable for PWM3 0: Disable PWM3 Output. 1: Enable PWM3 Output. Output enable for PWM2 0: Disable PWM2 Output. 1: Enable PWM2 Output. Enable PWM3 0: Disable PWM3. 1: Enable PWM3. Enable PWM2 0: Disable PWM2. 1: Enable PWM2. Output enable for PWM1 0: Disable PWM1 Output. 1: Enable PWM1 Output. Output enable for PWM0 0: Disable PWM0 Output. 1: Enable PWM0 Output. Enable PWM1 0: Disable PWM1. 1: Enable PWM1. Enable PWM0 0: Disable PWM0. 1: Enable PWM0.
PWM 2 Register
Bit: 7 6 5 4 3 2 1 0 PWM2.7 PWM2.6 PWM2.5 PWM2.4 PWM2.3 PWM2.2 PWM2.1 PWM2.0
Address: DDh
Mnemonic: PWM2
PWM 3 Register
Bit: 7 6 5 4 3 2 1 0 PWM3.7 PWM3.6 PWM3.5 PWM3.4 PWM3.3 PWM3.2 PWM3.1 PWM3.0
Address: DEh
Mnemonic: PWM3
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W79E201
Accumulator
Bit: 7 ACC.7 6 ACC.6 5 ACC.5 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1 0 ACC.0
Mnemonic: ACC
Address: E0h
ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.
ADC Control Register
Bit: 7 ADC.1 6 ADC.0 5 ADCEX 4 ADCI 3 ADCS 2 1 0 AADR2 AADR1 AADR0
Address: E1h
Mnemonic: ADCCON
BIT
NAME
FUNCTION
7 6 5
ADC.1 ADC.0 ADCEX
Bit 1 of ADC result. Bit 0 of ADC result. Enable external start of conversion by STADC 0 = Conversion can be started by software only (by setting ADCS) 1 = Conversion can be started by software or externally pin P2.0 (by a rising edge on STADC)
4
ADCI
ADC Interrupt flag: This ADCI flag is set when an A/D conversion result is ready to be read. An interrupt is invoked if it is enabled. The flag may be cleared by the interrupt service routine. While this flag is set, the ADC can not start a new conversion. ADCI can not set by software. ADC Start and Status: setting this bit starts an A/D conversion. It may be set by software or by the external STADC signal. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset immediately after the interrupt flag has been set. ADCS can not be reset by software. A new conversion may not be started while either ADCS or ADCI is high.
ADCI 0 0 1 1 ADCS 0 1 0 1 ADC Status ADC not busy; a conversion can be started ADC busy; start of a new conversion is blocked Conversion completed; start of a new conversion requires ADCI=0 Conversion completed; start of a new conversion requires ADCI=0
3
ADCS
If ADCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the same channel number may be started. But it is recommended to reset ADCI before ADCS is set. 2 1 0 AADR2 AADR1 AADR0 See the below table. See the below table. See the below table.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
AADR2~AADR0: The ADC analog input channel select bits: This binary coded address selects one of eight analogue port bits of ADC input converter. It can only be changed when ADCI and ADCS are both LOW. AADR2 0 0 0 0 1 1 1 1 AADR1 0 0 1 1 0 0 1 1 AADR0 0 1 0 1 0 1 0 1 Selected Analog Channel ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
ADC Conversion Result Register
Bit: 7 ADC.9 6 ADC.8 5 ADC.7 4 ADC.6 3 ADC.5 2 ADC.4 1 ADC.3
Address: E2h
0 ADC.2
Mnemonic: ADCH
BIT
NAME
FUNCTION
7 6 5 4 3 2 1 0
ADC.9 ADC.8 ADC.7 ADC.6 ADC.5 ADC.4 ADC.3 ADC.2
Bit 9 of ADC result. Bit 8 of ADC result. Bit 7 of ADC result. Bit 6 of ADC result. Bit 5 of ADC result. Bit 4 of ADC result. Bit 3 of ADC result. Bit 2 of ADC result.
ADC Conversion Enable Register
Bit: 7 6 5 4 3 2 1 0 nADCEN
Mnemonic: ADCCEN
Address: E4h
nADCEN: Enable ADC Function: The default is "1" that disables ADC analog circuit. Clear this bit to enable ADC analog circuit.
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W79E201
Extended Interrupt Enable
Bit: 7 6 5 4 EWDI 3 2 1 0 -
Mnemonic: EIE
Address: E8h
BIT
NAME
FUNCTION
7~5 4 3~0
EWDI -
Reserved, will read high Enable Watchdog timer interrupt Reserved, will read high
B Register
Bit:
Mnemonic: B
7 B.7
6 B.6
5 B.5
4 B.4
3 B.3
2 B.2
Address: F0h
1 B.1
0 B.0
B.7-0: The B register is the standard 8052 register that serves as a second accumulator.
Extended Interrupt Priority
Bit:
Mnemonic: EIP
7 -
6 -
5 -
4 PWDI
3 -
2 -
1 -
0 -
Address: F8h
BIT
NAME
FUNCTION
7~5 4 3~0
PWDI -
Reserved. Watchdog Timer Interrupt Priority. Reserved.
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Publication Release Date: December 16, 2004 Revision A2
W79E201
8. INSTRUCTION
The W79E201 executes all the instructions of the standard 8032 family. The operation of these instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of these instructions is different. The reason for this is two fold. Firstly, in the W79E201, each machine cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the W79E201 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. The advantage the W79E201 has is that since there is only one fetch per machine cycle, the number of machine cycles in most cases is equal to the number of operands that the instruction has. In case of jumps and calls there will be an additional cycle that will be needed to calculate the new address. But overall the W79E201 reduces the number of dummy fetches and wasted cycles, thereby improving efficiency as compared to the standard 8032.
8.1
Instruction Timing
The instruction timing for the W79E201 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between the W79E201 and the standard 8032. In the W79E201 each machine cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the W79E201 does one op-code fetch per machine cycle. Therefore, in most of the instructions, the number of machine cycles needed to execute the instruction is equal to the number of bytes in the instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than half of all opcodes in the W79E201 are executed in just four clock periods. Most of the two-cycle instructions are those that have two byte instruction codes. However there are some instructions that have only one byte instructions, yet they are two cycle instructions. One instruction which is of importance is the MOVX instruction. In the standard 8032, the MOVX instruction is always two machine cycles long. However in the W79E201, the user has a facility to stretch the duration of this instruction from 2 machine cycles to 9 machine cycles. The RD and WR strobe lines are also proportionately elongated. This gives the user flexibility in accessing both fast and slow peripherals without the use of external circuitry and with minimum software overhead. The rest of the instructions are either three, four or five machine cycle instructions. Note that in the W79E201, based on the number of machine cycles, there are five different types, while in the standard 8032 there are only three. However, in the W79E201 each machine cycle is made of only 4 clock periods compared to the 12 clock periods for the standard 8032. Therefore, even though the number of categories has increased, each instruction is at least 1.5 to 3 times faster than the standard 8032 in terms of clock periods.
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W79E201
Single Cycle C1 CLK ALE PSEN AD7-0 PORT 2 A7-0
Data_ in D7-0
C2
C3
C4
Address A15-8
Single Cycle Instruction Timing
Instruction Fetch C1 CLK ALE PSEN AD7-0 PORT 2
PC OP-CODE
Address A15-8
Operand Fetch C4 C1 C2 C3 C4
C2
C3
PC+1
OPERAND
Address A15-8
Two Cycle Instruction Timing
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Instruction Fetch C1 CLK ALE PSEN AD7-0 PORT 2 A7-0 OP-CODE C2 C3 C4 C1
Operand Fetch C2 C3 C4 C1
Operand Fetch C2 C3 C4
A7-0
OPERAND
A7-0
OPERAND
Address A15-8
Address A15-8
Address A15-8
Three Cycle Instruction Timing
Instruction Fetch C1 CLK ALE PSEN AD7-0 A7-0 OP-CODE C2 C3 C4
Operand Fetch C1 C2 C3 C4
Operand Fetch C1 C2 C3 C4
Operand Fetch C1 C2 C3 C4
A7-0 OPERAND
A7-0 OPERAND
A7-0 OPERAND
Port 2
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Four Cycle Instruction Timing
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W79E201
Instruction Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
Operand Fetch
C1 C2 C3 C4
CLK ALE PSEN AD7-0 A7-0 OP-CODE A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND A7-0 OPERAND
PORT 2
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Five Cycle Instruction Timing
8.1.1
External Data Memory Access Timing
The timing for the MOVX instruction is another feature of the W79E201. In the standard 8032, the MOVX instruction has a fixed execution time of 2 machine cycles. However in the W79E201, the duration of the access can be varied by the user. The instruction starts off as a normal op-code fetch of 4 clocks. In the next machine cycle, the W79E201 puts out the address of the external Data Memory and the actual access occurs here. The user can change the duration of this access time by setting the STRETCH value. The Clock Control SFR (CKCON) has three bits that control the stretch value. These three bits are M2-0 (bits 2-0 of CKCON). These three bits give the user 8 different access time options. The stretch can be varied from 0 to 7, resulting in MOVX instructions that last from 2 to 9 machine cycles in length. Note that the stretching of the instruction only results in the elongation of the MOVX instruction, as if the state of the CPU was held for the desired period. There is no effect on any other instruction or its timing. By default, the Stretch value is set at 1, giving a MOVX instruction of 3 machine cycles. If desired by the user the stretch value can be set to 0 to give the fastest MOVX instruction of only 2 machine cycles.
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Table 4. Data Memory Cycle Stretch Values
RD OR WR
M2 M1 M0 MACHINE CYCLES STROBE WIDTH IN CLOCKS
RD OR WR
STROBE WIDTH @ 25 MHZ
RD OR WR
STROBE WIDTH @ 40 MHZ
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 3 (default) 4 5 6 7 8 9
2 4 8 12 16 20 24 28
80 nS 160 nS 320 nS 480 nS 640 nS 800 nS 960 nS 1120 nS
50 nS 100 nS 200 nS 300 nS 400 nS 500 nS 600 nS 700 nS
Last Cycle of Previous Instruction
First Machine cycle
Second Machine cycle
Next Instruction Machine Cycle
MOVX instruction cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK ALE PSEN WR PORT 0
A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7 A0-A7 D0-D7
MOVX Inst. Address MOVX Inst.
Next Inst. Address
MOVX Data Address MOVX Data out A15-A8 A15-A8
Next Inst. Read
A15-A8
PORT 2
A15-A8
Data Memory Write with Stretch Value = 0
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W79E201
Last Cycle of Previous Instruction
First Machine Cycle
Second Machine Cycle
Third Machine Cycle
Next Instruction Machine Cycle
MOVX instruction cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK ALE PSEN WR PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Inst. Address
Next Inst. Address
MOVX Data Address
MOVX Data out
MOVX Inst.
Next Inst. Read A15-A8 A15-A8 A15-A8
PORT 2
A15-A8
Data Memory Write with Stretch Value = 1
Last Cycle of Previous Instruction
First Machine Cycle
Second Machine Cycle
Third Machine Cycle
Fourth Machine Cycle
Next Instruction Machine Cycle
MOVX instruction cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK ALE PSEN WR PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Inst. Address
Next Inst. Address
MOVX Data Address
MOVX Data out
MOVX Inst.
Next Inst. Read A15-A8 A15-A8 A15-A8
PORT 2
A15-A8
Data Memory Write with Stretch Value = 2
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9. POWER MANAGEMENT
The W79E201 has several features that help the user to control the power consumption of the device. The power saving features is basically the POWER DOWN mode and the IDLE mode of operation.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The ALE and PSEN pins are held high during the Idle state. The port pins hold the logical states they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. This will automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine (ISR) will be executed. After the ISR, execution of the program will continue from the instruction which put the device into Idle mode. The Idle mode can also be exited by activating the reset. The device can be put into reset either by applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the SFRs are set to the reset condition. Since the clock is already running there is no delay and execution starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt which will wake up the device. The software must reset the Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out. When the W79E201 is exiting from an Idle mode with a reset, the instruction following the one which put the device into Idle mode is not executed. So there is no danger of unexpected writes.
Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The W79E201 will exit the Power Down mode with a reset or by an external interrupt pin enabled as level detect. An external reset can be used to exit the Power down state. The high on RST pin terminates the Power Down mode, and restarts the clock. The program execution will restart from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power down mode. The W79E201 can be woken from the Power Down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and the external input has been set to a level detect mode. If these conditions are met, then the low level on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the corresponding external interrupt. After the interrupt service routine is completed, the program execution returns to the instruction after the one which put the device into Power Down mode and continues from there.
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Table 5. Status of external pins during Idle and Power Down
MODE PROGRAM MEMORY ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle Idle Power Down Power Down
Internal External Internal External
1 1 0 0
1 1 0 0
Data Float Data Float
Data Data Data Data
Data Address Data Data
Data Data Data Data
Reset Conditions
The user has several hardware related options for placing the W79E201 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state depends on the source of reset. The user can use these flags to determine the cause of reset using software. There are two ways of putting the device into reset state. They are External reset and Watchdog reset. External Reset The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST pin must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous operation and requires the clock to be running to cause an external reset. Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin program execution from 0000h. There is no flag associated with the external reset condition. However since the other two reset sources have flags, the external reset can be considered as the default reset if those two flags are cleared. The software must clear the POR flag after reading it, otherwise it will not be possible to correctly determine future reset sources. If the power fails, i.e. falls below Vrst, then the device will once again go into reset state. When the power returns to the proper operating levels, the device will again perform a power on reset delay and set the POR flag. Watchdog Timer Reset The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached an interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog timer will generate a reset. This places the device into the reset condition. The reset condition is maintained by hardware for two machine cycles. Once the reset is removed the device will begin execution from 0000h. Reset State Most of the SFRs and registers on the device will go to the same condition in the reset state. The Program Counter is forced to 0000h and is held there as long as the reset condition is applied. However, the reset state does not affect the on-chip RAM. The data in the RAM will be preserved during the reset. However, the stack pointer is reset to 07h, and therefore the stack contents will be lost. The RAM contents will be lost if the VDD falls below approximately 2V, as this is the minimum voltage level required for the RAM to operate normally. Therefore after a first time power on reset the Publication Release Date: December 16, 2004 Revision A2
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W79E201
RAM contents will be indeterminate. During a power fail condition, if the power falls below 2V, the RAM contents are lost. After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is disabled if the reset source was a POR. The ports SFRs have FFh written into them which puts the port pins in a high state. Port 0 floats as it does not have on-chip pull-ups. Table 6. SFR Reset Value
SFR NAME RESET VALUE SFR NAME RESET VALUE
P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 SCON SBUF P2 P0R P4 IE SADDR CHPCON SFRAL SFRAH SFRFD SFRCN P3 PWM5
11111111b 00000111b 00000000b 00000000b 00xx0000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000001b 11111111b 00000000b xxxxxxxxb 11111111b 00000000b Xxxxxxx1b 00000000b 00000000b 00000000b 00000000b 00000000b 11111111b 00111111b 11111111b 00000000b
EIP IP SADEN PMR STATUT2 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PSW WDCON PWMP PWMCON1 PWM0 PWM1 PWM2 PWM3 ACC ADCCON ADCH ADCCEN PWMCON2 PWM4 EIE B
xxx00000b x0000000b 00000000b xxxxx0xxb 000x0000b 00000000b 00000x00b 00000000b 00000000b 00000000b 00000000b 00000000b 0x0x0xx0b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b xxxxx000b xxxxxxxxb xxxxxxx1b 00000000b 00000000b xxx00000b 00000000b
The WDCON SFR bits are Set/Cleared in reset condition depending on the source of the reset. External reset WDCON 0x0x0xx0b Watchdog reset 0x0x01x0b Power on reset 01000000b
The POR bit WDCON.6 is set only by the power on reset. The WTRF bit WDCON.2 is set when the Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit WDCON.1 is - 40 -
W79E201
cleared by power on resets. This disables the Watchdog timer resets. A watchdog or external reset does not affect the EWT bit.
10. INTERRUPTS
The W79E201 has a two priority level interrupt structure with 8 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the external interrupts are sampled every machine cycle, they have to be held high or low for at least one complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the interrupt continues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same source. The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The hardware does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag. The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is enabled by the enable bit EIE.4, then an interrupt will occur. All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disable all the interrupts.
Priority Level Structure
There are two priority levels for the interrupts, highest, high and low. The interrupt sources can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. This hierarchy is defined as shown below; the interrupts are numbered starting from the highest priority to the lowest.
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Table 7. Priority structure of interrupts
SOURCE FLAG VECTOR ADDRESS PRIORITY LEVEL
External Interrupt 0 ADC Interrupt Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port Timer 2 Overflow Watchdog Timer
IE0 ADCI TF0 IE1 TF1 RI + TI TF2 + EXF2 WDIF
0003h 006Bh 000Bh 0013h 001Bh 0023h 002Bh 0063h
1(highest) 2 3 4 5 6 7 8 (lowest)
11. PROGRAMMABLE TIMERS/COUNTERS
The W79E201 has three 16-bit programmable timer/counters and one programmable Watchdog timer. The Watchdog timer is operationally quite different from the other two timers.
11.1 Timer/Counters 0 & 1
The Timer/Counters 0/1 have two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit registers which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The two can be configured to operate either as timers, counting machine cycles or as counters counting external inputs. When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the register is incremented on the falling edge of the external input pin, T0 in case of Timer 0, and T1 for Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. Since it takes two machine cycles to recognize a negative transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. In either the "Timer" or "Counter" mode, the count register will be updated at C3. Therefore, in the "Timer" mode, the recognized negative transition on pin T0 and T1 can cause the count register value to be updated only in the machine cycle following the one in which the negative edge was detected. The "Timer" or "Counter" function is selected by the " C/ T " bit in the TMOD Special Function Register. Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done by bits M0 and M1 in the TMOD SFR. Time-Base Selection The W79E201 gives the user two modes of operation for the timer. The timers can be programmed to operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed. This will ensure that timing loops on the W79E201 and the standard 8051 can be matched. This is the default mode of operation of the W79E201 timers. The user also has the option to count in the turbo mode, where the - 42 -
W79E201
timers will increment at the rate of 1/4 clock speed. This will straight-away increase the counting speed three times. This selection is done by the T0M and T1M bits in CKCON SFR. A reset sets these bits to 0, and the timers then operate in the standard 8051 mode. The user should set these bits to 1 if the timers are to operate in turbo mode. Mode 0 In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The upper 3 bits of TLx are ignored. The negative edge of the clock is increments the count in the TLx register. When the fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the count in THx is moving from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if TRx is set and either GATE = 0 or INTx = 1. When C/ T is set to 0, then it will count clock cycles, and if C/ T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1. When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when used as a timer, the time-base may be either clock cycles/12 or clock cycles/4 as selected by the bits TxM of the CKCON SFR.
T0M = CKCON.3 (T1M = CKCON.4) 1/4 1 0 C/T = TMOD.2 (C/T = TMOD.6) 0 1 T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) 0
Timer 1 functions are shown in brackets
M1,M0 = TMOD.1,TMOD.0 (M1,M0 = TMOD.5,TMOD.4) 00 4 TL0 (TL1) 7 01 0 TH0 (TH1) 7
osc
1/12
GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
TFx TF0 (TF1)
Interrupt
Timer/Counter Mode 0 & Mode 1
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Mode 1 Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in Mode 0. The gate function operates similarly to that in Mode 0. Mode 2 In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues from here. The reload operation leaves the contents of the THx register unchanged. Counting is enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1 mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
T0M = CKCON.3 (T1M = CKCON.4) 1/4
Timer 1 functions are shown in brackets
TL0 (TL1)
osc
1/12 T0 = P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE = TMOD.7) INT0 = P3.2 (INT1 = P3.3)
1 0
C/T = TMOD.2 (C/T = TMOD.6) 0 1
0
7
TFx
TF0 (TF1)
Interrupt
0
TH0 (TH1)
7
Timer/Counter Mode 2
Mode 3 Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0 control bits C/ T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin T0 as determined by C/ T (TMOD.2). TH0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1 and 2., but its flexibility is somewhat limited. While its basic functionality is maintained, it no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port.
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W79E201
1/4
osc
1/12 T0 = P3.4 TR0 = TCON.4 GATE = TMOD.3 INT0 = P3.2
T0M = CKCON.3 1 C/T = TMOD.2 0 0 1
TL0
0
7
TF0
Interrupt
TH0 TR1 = TCON.6
0
7
TF1
Interrupt
Timer/Counter 0 Mode 3
11.2 Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer 0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in defining the operating mode. The clock source for Timer/Counter 2 may be selected for either the external T2 pin ( C/ T2 = 1) or the crystal oscillator, which is divided by 12 or 4 ( C/ T2 = 0). The clock is then enabled when TR2 is a 1, and disabled when TR2 is a 0. Capture Mode The capture mode is enabled by setting the CP/RL2 bit in the T2CON register to a 1. In the capture mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from FFFFh to 0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a negative transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W79E201 allows hardware to reset timer 2 automatically after the value of TL2 and TH2 have been captured.
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RCLK+TCLK=0, CP/RL2 =T2CON.0=1
1/4 T2M = CKCON.5 1 0 0 1 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1 C/T2 = T2CON.1 TL2 TH2 T2CON.7 TF2
osc
1/12
Timer 2 Interrupt
RCAP2L RCAP2H
EXEN2 = T2CON.3
EXF2 T2CON.6
16-Bit Capture Mode
Auto-reload Mode, Counting up The auto-reload mode as an up counter is enabled by clearing the CP/RL2 bit in the T2CON register and clearing the DCEN bit in T2MOD register. In this mode, Timer/Counter 2 is a 16 bit up counter. When the counter rolls over from FFFFh, a reload is generated that causes the contents of the RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. The reload action also sets the TF2 bit. If the EXEN2 bit is set, then a negative transition of T2EX pin will also cause a reload. This action also sets the EXF2 bit in T2CON. RCLK+TCLK=0, CP/RL2 =T2CON.0=0, DCEN=0
1/4
osc 1/12 T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1
RCAP2L RCAP2 H
T2M = CKCON.5
1
0
C/T2 = T2CON.1 0
T2CON.7 TL2 TH2
1
TF2
Timer 2 Interrupt
EXEN2 = T2CON.3
EXF2 T2CON.6
16-Bit Auto-reload Mode, Counting Up
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Auto-reload Mode, Counting Up/Down Timer/Counter 2 will be in auto-reload mode as an up/down counter if CP/RL2 bit in T2CON is cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter 2 is an up/down counter whose direction is controlled by the T2EX pin. A 1 on this pin cause the counter to count up. An overflow while counting up will cause the counter to be reloaded with the contents of the capture registers. The next down count following the case where the contents of Timer/Counter equal the capture registers will load an FFFFh into Timer/Counter 2. In either event a reload will set the TF2 bit. A reload will also toggle the EXF2 bit. However, the EXF2 bit can not generate an interrupt while in this mode. RCLK+TCLK=0, CP/RL2 =T2CON.0=0, DCEN=1
Down Counting Reload Value
0FFh 1/4 T2M = CKCON.5
0FFh
osc
1/12 T2 = P1.0 TR2 = T2CON.2
1 0
C/T = T2CON.1 0
T2CON.7
TL2 TH2
1
TF2
Timer 2 Interrupt
RCAP2L
RCAP2H
T2EX = P1.1
Up Counting Reload Value
EXF2 T2CON.6
16-Bit Auto-reload Up/Down Counter
Baud Rate Generator Mode The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register. While in the baud rate generator mode, Timer/Counter 2 is a 16 bit counter with auto reload when the count rolls over from FFFFh. However, rolling-over does not set the TF2 bit. If EXEN2 bit is set, then a negative transition of the T2EX pin will set EXF2 bit in the T2CON register and cause an interrupt request. RCLK+TCLK=0
osc
T2 = P1.0 TR2 = T2CON.2 T2EX = P1.1
0
C/T = T2CON.1 TL2 TH2
1
Timer 2 overflow
RCAP2L RCAP2H
EXEN2 = T2CON.3
EXF2 T2CON.6
Timer 2 Interrupt
Baud Rate Generator Mode
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12. WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set. The interrupt and reset functions are independent of each other and may be used separately or together depending on the user's software.
XT
0
16
WD1,WD0
WDIF EWDI(EIE.4) 17 19
Interrupt
00 01 10 Time-out
WTRF
20
22
11
512 clock delay
Reset
Reset Watchdog RWT(WDCON.0)
23
25
Enable Watchdog timer reset EWT(WDCON.1)
Watchdog Timer
The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing, i.e. after writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. If the Watchdog Reset EWT (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system reset due to Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the cause of the reset. When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an interrupt will occur if the global interrupt enable EA is set. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of some power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. Using the watchdog timer interrupt during software development will allow the user to select ideal watchdog reset locations. The code is first written without the watchdog interrupt or reset. Then the watchdog interrupt is enabled to identify code locations where interrupt occurs. The user can now insert instructions to reset the watchdog timer which will allow the code to run without any watchdog timer interrupts. Now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. If - 48 -
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any errant code is executed now, then the reset watchdog timer instructions will not be executed at the required instants and watchdog reset will occur. The watchdog time-out selection will result in different time-out values depending on the clock speed. The reset, when enabled, it will occur 512 clocks after the time-out had occurred. Table 9. Time-out values for the Watchdog timer WD1 0 0 1 1 WD0 0 1 0 1 Watchdog Interval 2 2 2 2
17 20 23 26
Number of Clocks 131072 1048576 8388608 67108864
Time @ 1.8432 MHz 71.11 mS 568.89 mS 4551.11 mS 36408.88 mS
Time @ 10 MHz 13.11 mS 104.86 mS 838.86 mS 6710.89 mS
Time @ 25 MHz 5.24 mS 41.94 mS 335.54 mS 2684.35 mS
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Control
BIT NAME FUNCTION
7 6 5 4 3
POR WDIF
Reserved. Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read or written by software. A write by software is the only way to clear this bit once it is set. Reserved. Reserved. Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. This bit must be cleared by software. Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit. This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no affect on this bit. Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function. Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
2
WTRF
1
EWT
0
RWT
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Clock Control WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the timeout interval for the watchdog timer. The reset time is 512 clocks longer than the interrupt time-out value. The default Watchdog time-out is 2 clocks, which is the shortest time-out period. The EWT, WDIF and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant code can enable or disable the watchdog timer. Please refer as below demo program. org mov mov clr jnb jmp bypass_reset: mov mov setb reti org start: mov ; ; ; mov mov mov mov mov mov setb setb jmp ckcon,#01h ckcon,#61h ckcon,#81h ckcon,#c1h TA,#aah TA,#55h WDCON,#00000011B EWDI ea $ ; wait time out ; select 2 ^ 17 timer ; select 2 ^ 20 timer ; select 2 ^ 23 timer ; select 2 ^ 26 timer 300h TA,#AAH TA,#55H RWT 63h TA,#AAH TA,#55H WDIF execute_reset_flag,bypass_reset $ ; Test if CPU need to reset. ; Wait to reset
17
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W79E201
13. SERIAL PORT
Serial port in the W79E201 is a full duplex port. The W79E201 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports are capable of synchronous as well as asynchronous communication. In Synchronous mode the W79E201 generates the clock and operates in a half duplex mode. In the asynchronous mode, full duplex operation is available. This means that it can simultaneously transmit and receive data. The transmit register and the receive buffer are both addressed as SBUF Special Function Register. However any write to SBUF will be to the transmit register, while a read from SBUF will be from the receive buffer register. The serial port can operate in four different modes as described below. Mode 0 This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is provided by the W79E201 whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is Transmitted/Received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This baud rate is determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port runs at 1/12 of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional facility of programmable baud rate in mode 0 is the only difference between the standard 8051 and the W79E201. The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line. The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the W79E201 and the device at the other end of the line. Any instruction that causes a write to SBUF will start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all 8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift clock on TxD or latched when the TxD clock is low.
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OSC
Write to SBUF 12 4
TX START TX CLOCK
Transmit Shift Register Internal Data Bus
PARIN LOAD CLOCK SOUT
RXD P3.0 Alternate Output Function
TX SHIFT TI
SM2 0
1
SERIAL CONTROLLE
RX CLOCK
Serial Port Interrupt
RI
SHIFT CLOCK LOAD SBUF RX SHIFT CLOCK
RI REN RXD P3.0 Alternate Iutput function
TXD P3.1 Alternate Output function Read SBUF SBUF Internal Data Bus
RX START
PAROUT SIN
SBUF
Receive Shift Register
Serial Port Mode 1
The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch data on the rising edge of shift clock. The external device should therefore present data on the falling edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is cleared by software. Mode 1 In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of 10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB first), and a stop bit (1). On received, the stop bit goes into RB8 in the SFR SCON. The baud rate in this mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow. Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 Counter and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be at the 10th rollover of the divide by 16 Counter after a write to SBUF. Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 Counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 Counter. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By - 52 -
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using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set. However certain conditions must be met before the loading and setting of RI can be done. 1. RI must be 0 and 2. Either SM2 = 0, or the received stop bit = 1. If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin.
Timer 1 Overflow Timer 2 Overflow Transmit Shift Register
0
Internal Data Bus Write to SBUF 1
16 TX START TX CLOCK TX SHIFT TI
STOP PARIN
2 SMOD= 0
1
START LOAD CLOCK
SOUT
TXD
1 0
TCLK
RCLK
0
1 16
SERIAL CONTROLLER
RX CLOCK RX START
Serial Port Interrupt
RI
SAMPLE
1-TO-0 DETECTOR
LOAD SBUF RX SHIFT CLOCK PAROUT D8 SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
Receive Shift Register
Serial Port Mode 1
Mode 2 This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1 following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the Publication Release Date: December 16, 2004 Revision A2
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divide by 16 Counter, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be at the 11th rollover of the divide by 16 Counter after a write to SBUF. Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 Counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 Counter. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature of the serial port.
Transmit Shift Register
OSC
2
SMOD=
TB8
D8 STOP PARIN START LOAD CLOCK
Internal Data Bus 0 1 Write to SBUF
TX START
0 1
SOUT
TXD
TX SHIFT
16 16
SAMPLE 1-TO-0 DETECTOR
TX CLOCK
TI
SERIAL CONTROLLE RI
RX CLOCK RX START LOAD SBUF RX SHIFT
CLOCK PAROUT
Serial Port Interrupt
Read SBUF
SBUF RB8
RXD
BIT DETECTOR
SIN
D8
Internal Data Bus
Receive Shift Register
Serial Port Mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set. However certain conditions must be met before the loading and setting of RI can be done. 1. RI must be 0 and 2. Either SM2 = 0, or the received stop bit = 1. If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin. Mode 3
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This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user must first initialize the Serial related SFR SCON before any communication can take place. This involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3 are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the incoming start bit if REN = 1. The external device will start the communication by transmitting the start bit.
Transmit Shift Register Timer 1 Overflow Timer 2 Overflow
0
TB8 Internal Data Bus Write to SBUF
STOP D8 PARIN START LOAD CLOCK SOUT
2
TXD
1
SMOD = 0
1 0 1
TCLK
TX START 16 TX CLOCK
TX SHIFT TI
RCLK
0
1
16
SERIAL CONTROLLER
RX CLOCK RX START
Serial Port Interrupt
RI
SAMPLE
1-TO-0 DETECTOR
LOAD SBUF RX SHIFT CLOCK PAROUT D8 SBUF RB8
Read SBUF Internal Data Bus
RXD
BIT DETECTOR
SIN
Receive Shift Register
Serial Port Mode 3
Table 10. Serial Ports Modes SM1 0 0 1 1 SM0 0 1 0 1 Mode 0 1 2 3 Type Synch. Asynch. Asynch. Asynch. Baud Clock 4 or 12 TCLKS Timer 1 or 2 32 or 64 TCLKS Timer 1 or 2 Frame Size 8 bits 10 bits 11 bits 11 bits Start Bit No 1 1 1 Stop Bit No 1 1 1 9th bit Function None None 0, 1 0, 1
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13.1 Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically the frame error is due to noise and contention on the serial communication line. The W79E201 has the facility to detect such framing errors and set a flag which can be checked by software. The Frame Error FE(FE_1) bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051 family. However, in the W79E201 it serves a dual function and is called SM0/FE. There are actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE. The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while reading or writing to FE. If FE is set, then any following frames received without any error will not clear the FE flag. The clearing has to be done by software.
13.2 Multiprocessor Communications
Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W79E201, the RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware feature eliminates the software overhead required in checking every received address, and greatly simplifies the software programmer task. In the multiprocessor communication mode, the address bytes are distinguished from the data bytes by transmitting the address with the 9th bit set high. When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the slave processors should have their SM2 bit set high when waiting for an address byte. This ensures that they will be interrupted only by the reception of a address byte. The Automatic address recognition feature ensures that only the addressed slave will be interrupted. The address comparison is done in hardware not software. The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0, the slave will be interrupted on the reception of every single complete frame of data. The unaddressed slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th bit is the stop bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is received and the received byte matches the Given or Broadcast address. The Master processor can selectively communicate with groups of slaves by using the Given Address. All the slaves can be addressed together using the Broadcast Address. The addresses for each slave are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives the user flexibility to address multiple slaves without changing the slave address in SADDR. The following example shows how the user can define the Given Address to address different slaves. Slave 1: SADDR 1010 0100 SADEN 1111 1010 Given 1010 0x0x
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Slave 2: SADDR 1010 0111 SADEN 1111 1001 Given 1010 0xx1 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010 0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2. The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature, since any selectivity is disabled.
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14. PULSE WIDTH MODULATED OUTPUTS (PWM)
There are six pulse width modulated output channels to generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of six registers: PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5. Provided the contents of either these registers is greater than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3, PWM4 or PWM5 output is set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3, ENPWM4 and ENPWM5 bit will enable or disable PWM output. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWM0/1/2/3/4/5. The repetition frequency Fpwm at the PWM0/1/2/3/4/5 output is given by:
Fpwm = Fosc 2 x (1 + PWMP) x 255
Prescaler division factor = PWM + 1 PWMn high/low ratio of PWMn =
(PWMn) 255 - (PWMn)
This gives a repetition frequency range of 123 Hz to 31.4K Hz ( fosc = 16M Hz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4, PWM5) is loaded with a new value, the associated output updated immediately. It does not have to wait until the end of the current counter period. There is weakly pulled high on PWM output.
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PWMP Register ENPWM 0/1/2/3/4/5
PWM0 Register
X Y
+ > -+ > + > + > PWM3OE PWM2OE PWM1OE PWM0OE
PWM0 (P0.2)
1/2 Fosc
8-bits Counter PWM1 Register
X Y
PWM1 (P0.3)
PWM2 Register
X Y
PWM2 (P0.4)
PWM3 Register
X Y
PWM3 (P0.5)
PWM4 Register
X Y
+ > PWM4OE PWM4 (P0.6)
PWM5 Register
X Y
+ > PWM5OE PWM5 (P0.7)
PWM block diagram
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15. ANALOG-TO-DIGITAL CONVERTER
The ADC contains a DAC which converts the contents of a successive approximation register to a voltage (VDAC) which is compared to the analog input voltage (Vin). The output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. A conversion is initiated by setting ADCS in the ADCCON register. ADCS can be set by software only or by either hardware (P2.0) or software. Before used ADC circuit, it must enabled by ADCCEN. The software only start mode is selected when control bit ADCCON.5 (ADEX) =0. A conversion is then started by setting control bit ADCCON.3 (ADCS) The hardware or software start mode is selected when ADCCON.5 =1, and a conversion may be started by setting ADCCON.3 as above or by applying a rising edge to external pin STADC. When a conversion is started by applying a rising edge, a low level must be applied to STADC for at least one machine cycle followed by a high level for at least one machine cycle. The low-to-high transition of STADC is recognized at the end of a machine cycle, and the conversion commences at the beginning of the next cycle.
MSB DAC Successive Approximation Register LSB Successive Approximation Control Logic
Start Ready (Stop)
Comparator VDAC Vin
Successive Approximation ADC
The end of the 10-bit conversion is flagged by control bit ADCCON.4 (ADCI). The upper 8 bits of the result are held in special function register ADCH, and the two remaining bits are held in ADCCON.7 (ADC.1) and ADCCON.6 (ADC.0). The user may ignore the two least significant bits in ADCCON and use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion time is 50 machine cycles. ADC will be set and the ADCS status flag will be reset 50 cycles after the ADCS is set.
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Control bits ADCCON.0, ADCCON.1 and ADCCON.2 are used to control an analog multiplexer which selects one of eight analog channels. An ADC conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1; a new ADC conversion already in progress is aborted when the idle or power down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode.
ADC Resolution and Analog Supply:
The ADC has its own supply pins (AVDD and AVSS ) and one pins (Vref+) connected to each end of the DAC's resistance-ladder. The ladder has 1023 equally spaced taps, separated by a resistance of "R". The first tap is located 0.5XR above AVss, and the last tap is located 0.5XR below Vref+. This gives a total ladder resistance of 1024XR. This structure ensures that the DAC is monotonic and results in a symmetrical quantization error. For input voltages between AVss and [(Vref+) + 1/2 LSB], the 10-bit result of an A/D conversion will be 00 0000 0000 b = 000H. For input voltages between [(Vref+) - 3/2 LSB] and Vref+, the result of a conversion will be 11 1111 1111B = 3FFH. AVref+ and AVSS may be between AVDD + 0.2V and AVSS - 0.2 V. Avref+ should be positive with respect to AVSS, and the input voltage (Vin) should be between AVref+ and AVSS. The result can always be calculated from the following formula: Result = 1024 x
Vin AVref +
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W79E201
AADR0 ADC0 ADC7 Analog Input Multiplexer AADR1 AADR2 ADCS ADCI AVDD Vin ADEX
ADCON 0 1 2 3 4 5 6 7
STADC ADC.0 ADC.1 10-Bit A/D converter ADC.2 ADC.3 ADC.4 ADC.5 ADC.6 ADC.7 ADC.8 ADC.9
ADCH 0 1 2 3 4 5 6 7
AVref+
AVSS
ADC Functional block Diagram
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W79E201
16. TIMED ACCESS PROTECTION
The W79E201 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation and loss of control. In order to prevent this, the W79E201 has a protection scheme which controls the write access to critical bits. This protection scheme is done using a timed access. In this method, the bits which are to be protected have a timed write enable window. A write is successful only if this window is active, otherwise the write will be discarded. This write enable window is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window automatically closes. The window is opened by writing AAh and immediately 55h to the Timed Access (TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed access window is TA REG MOV MOV 0C7h TA, #0AAh TA, #055h ; Define new register TA, located at 0C7h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles, during which the user may write to the protected bits. Once the window closes the procedure must be repeated to access the other protected bits. Examples of Timed Assessing are shown below. Example 1: Valid access MOV MOV MOV TA, #0AAh TA, #055h WDCON, #00h 3 M/C ; Note: M/C = Machine Cycles 3 M/C 3 M/C
Example 2: Valid access MOV MOV NOP SETB EWT Example 3: Valid access MOV MOV ORL TA, #0Aah TA, #055h 3 M/C 3 M/C TA, #0AAh TA, #055h 3 M/C 3 M/C 1 M/C 2 M/C
WDCON, #00000010B 3M/C
Example 4: Invalid access MOV MOV TA, #0AAh TA, #055h 3 M/C 3 M/C
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W79E201
NOP NOP CLR POR 1 M/C 1 M/C 2 M/C
Example 5: Invalid Access MOV NOP MOV TA, #055h SETB EWT TA, #0AAh 3 M/C 1 M/C 3 M/C 2 M/C
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window closes. In Example 3, however, the writing to the protected bit occurs after the window has closed, and so there is effectively no change in the status of the protected bit. In Example 4, the second write to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all, and the write to the protected bit fails.
17. H/W REBOOT MODE (BOOT FROM 4K BYTES OF LD FLASH EPROM)
The W79E201 boots from AP Flash EPROM program (16K bytes) by default at the external reset. On some occasions, user can force W79E201 to boot from the LD Flash EPROM program (4K bytes) at the external reset. The set for this special mode is as follow. It is necessary to add 10K resistor on P4.0 pins. Reboot Mode
OPTION BITS RST P4.0 MODE
Bit3 L
H
L
REBOOT
The Reset Timing For Entering REBOOT Mode
P4.0
Hi-Z
RST
20 US 10 mS
Notes: 1: In application system design, user must take care the P4.0, ALE, /EA and /PSEN pin value at reset to avoid W79E201 entering the programming mode or REBOOT mode in normal operation.
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W79E201
18. IN-SYSTEM PROGRAMMING
18.1 The Loader Program Locates at LD Flash EPROM Memory
CPU is Free Run at AP Flash EPROM memory. CHPCON register had been set #03H value before CPU has entered idle state. CPU will switch to LD Flash EPROM memory and execute a reset action. H/W reboot mode will switch to LD Flash EPROM memory, too. Set SFRCN register where it locates at user's loader program to update AP Flash EPROM memory. Set a SWRESET (CHPCON=#83H) to switch back AP Flash EPROM after CPU has updated AP Flash EPROM program. CPU will restart to run program from reset state.
18.2
The Loader Program Locates at AP Flash EPROM Memory
CPU is Free Run at AP Flash EPROM memory. CHPCON register had been set #01H value before CPU has entered idle state. Set SFRCN register to update LD Flash EPROM program. CPU will continue to run user's AP Flash EPROM program after CPU has updated program. Please refer demonstrative code to understand other detail description.
19. H/W WRITER MODE
This mode is for the writer to write / read Flash EPROM operation. A general user may not enter this mode.
The Timing For Entering Flash EPROM Mode on the Programmer
EA
Hi-Z
PSEN
Hi-Z
ALE
Hi-Z
P2.7
Hi-Z
P2.6
Hi-Z
P3.7
Hi-Z
P3.6
Hi-Z
RST
10ms 300ms
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W79E201
20. SECURITY BITS
Using device programmer, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those operations on it are described below. The W79E201 has Special Setting Register which can be accessed by device programmer. The register can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation.
Reserved B3 B2 B1 B0
Security Bits
B3: 0 -> Enable H/W reboot with P4.0 B2: 0 -> Encryption B1: 0 -> MOVC Inhibuted B0: 0 -> Data out lock Default 1 for each bit.
B0: Lock bit This bit is used to protect the customer's program code in the W79E201. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and Special Setting Registers can not be accessed again. B1: MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. B2: Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. B3: H/W Reboot with P4.0 If this bit is set to logic 0, enable to reboot 4k LD Flash EPROM mode while RST =H and P4.0 = L state. CPU will start from LD Flash EPROM to update the user's program
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W79E201
21. THE PERFORMANCE CHARACTERISTIC OF ADC
OFFSET ERROR The offset error is the deviation between ideal transfer value and actual transfer value. GAIN ERROR The gain error is the difference between the slope of ideal transfer curve and the slope of actual transfer curve. DIFFERENTIAL NONLINEARITY (DNL) The differential non-linearity is the difference between the actual step width and ideal step width. The ideal step width is 1 LSB. The characteristic of DNL is as below figure. INTEGRAL NONLINEARITY (INL) The integral non-linearity is the deviation of a code from actual straight line. The deviation of each code is measured from middle of this code. The characteristic of INL is as below figure.
21.1 The Differential Nonlinearity VS Output code
VDD - VSS = 5V 10%, AVDD - VSS =5V, Vref=5V, TA = 25C, Fosc = 16 MHz
Differential Nonlinearity vs Output Code
1 0.8 0.6
DNL ERROR (DNL)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 1 27 53 79 105 131 157 183 209 235 261 287 313 339 365 391 417 443 469 495 521 547 573 599 625 651 677 703 729 755 781 807 833 859 885 911 937 963 989 1015
Output Code
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W79E201
21.2 The Integral Nonlinearity VS Output code
VDD - VSS = 5V 10%, AVDD - VSS = 5V, Vref = 5V, TA = 25C, Fosc = 16 MHz
Integral Nonlinearity vs Output Code
1.4 1.2 1
INL ERROR (INL)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 1 27 53 79 105 131 157 183 209 235 261 287 313 339 365 391 417 443 469 495 521 547 573 599 625 651 677 703 729 755 781 807 833 859 885 911 937 963 989 1015
Output Code
22. THE EMBEDDED ICE WITH JTAG INTERFACE
The W79E201A16LN is packaged in 48-pins LQFP with the function of in-circuit emulation (ICE). The embedded ICE provides the below functions. Eight breakpoints to detect program counter Two enhanced watch breakpoints that can hold program by observing CPU access to data memory and Flash ROM Read/Write data memory when program holds Write application code to Flash ROM
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W79E201
23. ELECTRICAL CHARACTERISTICS
23.1 Absolute Maximum Ratings
SYMBOL PARAMETER CONDITION RATING UNIT
DC Power Supply Input Voltage Operating Temperature Storage Temperature
VDD - VSS VIN TA Tst
-0.3 VSS -0.3 0 -55
+7.0 VDD +0.3 +70 +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
23.2 DC Characteristics
(VDD - VSS = 5V 10%, TA = 25C, Fosc = 16 MHz, unless otherwise specified.)
PARAMETER
SYMBOL
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3 Input Current RST[*1] Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3 Input Low Voltage P0, P1, P2, P3, EA Input Low Voltage RST[*1]
VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL[*4] VIL1 VIL2
4.5 -50 -10 -10 -500 0 0
5.5 30 24 10 +10 +120 +10 -200 0.8 0.8
V mA mA A A A A A V V No load VDD = RST = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0- 69 -
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W79E201
DC Characteristics, continued
PARAMETER
SYMBOL
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Input Low Voltage XTAL1[*3] Input High Voltage P0, P1, P2, P3, EA Input High Voltage RST Input High Voltage XTAL1[*3] Sink current P1, P3 Sink current P0,P2, ALE, PSEN Source current P1, P3 Source current P0, P2, ALE, PSEN Output Low Voltage P1, P3 Output Low Voltage P0, P2, ALE, PSEN [*2] Output High Voltage P1, P3 Output High Voltage P0, P2, ALE, PSEN [*2]
Notes:
VIL3 VIH1 VIH2 VIH3 ISK1 ISK2 ISR1 ISR2 VOL1 VOL2 VOH1 VOH2
0 2.4 3.5 3.5 4 8 -180 -10 2.4 2.4
0.8 VDD +0.2 VDD +0.2 VDD +0.2 10 12 -360 -14 0.45 0.45 -
V V V V mA mA uA mA V V V V
VDD = 4.5V VDD = 5.5V VDD = 5.5V VDD = 5.5V VDD =4.5V Vs = 0.45V VDD =4.5V VOL = 0.45V VDD =4.5V VOL = 2.4V VDD =4.5V VOL = 2.4V VDD = 4.5V IOL = +6 mA VDD = 4.5V IOL = +10 mA VDD = 4.5V IOH = -180 A VDD = 4.5V IOH = -10mA
*1. RST pin is a Schmitt trigger input. *2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V.
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W79E201
23.3 ADC DC Electrical Characteristics
(AVDD - AVSS= 5V10%, TA= 25C, Fosc = 16MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION MIN. MAX. UNIT
TEST CONDITIONS
Analog input Reference voltage Resistance between AVref and AVSS Conversion time Offset error Gain error Differential non-linearity Integral non-linearity
AVin AVref Rref tC Ofe Ge DNL INL
AVSS-0.2 10
AVDD+0.2 AVDD+0.2 50 52tMC
V V K s LSB % LSB LSB When ADC is enabled tMC is machine cycle
-2 -0.4 -1 -2
+2 +0.4 +1 +2
23.4 AC Characteristics
tCLCL tCLCH tCLCX
Clock
tCHCL
tCHCX
Note: Duty cycle is 50%.
External Clock Characteristics
PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCH tCHCL MIN. 12 12 TYP. MAX. 10 10 UNITS nS nS nS nS NOTES
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W79E201
23.4.1 AC Specification
PARAMETER SYMBOL VARIABLE CLOCK MIN. VARIABLE CLOCK MAX. UNITS
Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low Address Hold After ALE Low for MOVX Write ALE Low to Valid Instruction In ALE Low to PSEN Low
PSEN Pulse Width
1/tCLCL tLHLL tAVLL tLLAX1 tLLAX2 tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV1 tAVIV2 tPLAZ tRHDX tRHDZ tRLAZ
0 1.5tCLCL - 5 0.5tCLCL - 5 0.5tCLCL - 5 0.5tCLCL - 5
16
MHz nS nS nS nS
2.5tCLCL - 20 0.5tCLCL - 5 2.0tCLCL - 5 2.0tCLCL - 20 0 tCLCL - 5 3.0tCLCL - 20 3.5tCLCL - 20 0 0 tCLCL - 5 0.5tCLCL - 5
nS nS nS nS nS nS nS nS nS nS nS nS
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In
PSEN Low to Address Float
Data Hold After Read Data Float After Read
RD Low to Address Float
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W79E201
23.4.2 MOVX Characteristics Using Stretch Memory Cycle
PARAMETER SYM. VARIABLE CLOCK MIN. VARIABLE CLOCK MAX. UNITS STRECH
Data Access ALE Pulse Width Address Hold After ALE Low for MOVX write
RD Pulse Width WR Pulse Width
tLLHL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ
1.5tCLCL - 5 2.0tCLCL - 5 0.5tCLCL - 5 2.0tCLCL - 5 tMCS - 10 2.0tCLCL - 5 tMCS - 10 2.0tCLCL - 20 tMCS - 20 0 tCLCL - 5 2.0tCLCL - 5 2.5tCLCL - 5 tMCS + 2tCLCL 40 3.0tCLCL - 20 2.0tCLCL - 5 0.5tCLCL - 5 1.5tCLCL - 5 tCLCL - 5 2.0tCLCL - 5 1.5tCLCL - 5 2.5tCLCL - 5 -5 1.0tCLCL - 5 tCLCL - 5 2.0tCLCL - 5 0.5tCLCL - 5 0 1.0tCLCL - 5 10 1.0tCLCL + 5 0.5tCLCL + 5 1.5tCLCL + 5
nS nS nS nS nS nS nS
tMCS = 0 tMCS>0
tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0 tMCS = 0 tMCS>0
RD Low to Valid Data In
Data Hold after Read Data Float after Read
ALE Low to Valid Data In
tLLDV
nS
Port 0 Address to Valid Data In ALE Low to RD or WR Low Port 0 Address to RD or WR Low Port 2 Address to RD or WR Low Data Valid to WR Transition Data Hold after Write
RD Low to Address Float RD or WR high to ALE high
tAVDV1 tLLWL tAVWL tAVWL2 tQVWX tWHQX tRLAZ tWHLH
nS nS nS nS nS nS nS nS
tMCS = 0 tMCS>0
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W79E201
Note: The tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of the tMCS for each selection of the Stretch value.
M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
MOVX Cycles 2 machine cycles 3 machine cycles 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles
tMCS 0 4 tCLCL 8 tCLCL 12 tCLCL 16 tCLCL 20 tCLCL 24 tCLCL 28 tCLCL
Explanation of Logics Symbols In order to maintain compatibility with the original 8051 family, this device specifies the same parameter for each device, using the same symbols. The explanation of the symbols is as follows. t C H I Q V X Time Clock Logic level high Instruction Output Data Valid No longer a valid state A D L P R W Z Address Input Data Logic level low
PSEN
RD signal
WR signal
Tri-state
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W79E201
23.4.3 Program Memory Read Cycle
tLHLL
ALE
tLLIV tAVLL tPLPH tPLIV tLLPL tPLAZ tLLAX1 tPXIX
INSTRUCTION IN ADDRESS A0-A7
PSEN
tPXIZ
PORT 0
ADDRESS A0-A7
tAVIV1 tAVIV2
PORT 2 ADDRESS A8-A15 ADDRESS A8-A15
23.4.4 Data Memory Read Cycle
ALE
tLLDV tWHLH
PSEN
tLLWL tLLAX1 tAVLL tAVWL1
tRLRH tRLDV
RD
tRLAZ
DATA IN
tRHDZ tRHDX
ADDRESS A0-A7
PORT 0
INSTRUCTION IN
ADDRESS A0-A7
tAVDV1 tAVDV2
PORT 2 ADDRESS A8-A15
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W79E201
23.4.5 Data Memory Write Cycle
ALE
tWHLH
PSEN
tLLWL tLLAX2 tAVLL
tWLWH
WR
tAVWL1 tQVWX
tWHQX
DATA OUT ADDRESS A0-A7
PORT 0
INSTRUCTION IN
ADDRESS A0-A7
t AVDV2
PORT 2 ADDRESS A8-A15
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W79E201
24. TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
VCC VCC 31 19 10 u R 18
CRYSTAL
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W79E201
8.2 K C1 C2
9 12 13 14 15 1 2 3 4 5 6 7 8
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
3 4 7 8 13 14 17 18 11
D0 D1 D2 D3 D4 D5 D6 D7 OC G
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
GND 1
74F373
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND 20 22
Figure A
CRYSTAL
C1
C2
R
12 MHz 16 MHz
Not necessary Not necessary
Not necessary Not necessary
Not necessary Not necessary
Pull EA low to let CPU fetches code in the embedded flash ROM when the program counter is lower than 16K and as the program counter is higher than 16K the CPU will fetch program code from extended external program memory automatically.
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W79E201
Expanded External Data Memory and Oscillator
VCC VCC
OSCILLATOR
31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W79E201
10 u
8.2 K
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
GND1 OC 11 G 74F373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 GND 20 22 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256
D0 D1 D2 D3 D4 D5 D6 D7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure B
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W79E201
25. PACKAGE DIMENSIONS
44-pin QFP
HD D
44 34
Dimension in inch
Dimension in mm
Symbol
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 L L1 Detail F
Seating Plane
See Detail F
y
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
44-pin PLCC
H
D
D
6 1 44 40
Symbol
39
Dimension in inches
Dimension in mm
Min.
0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.590 0.590 0.680 0.680 0.090
Nom.
Max.
0.185
Min.
0.508
Nom.
Max.
4.699
7
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.150 0.028 0.018 0.010 0.653 0.653
0.155 0.032 0.022 0.014 0.658 0.658 BSC 0.630 0.630 0.700 0.700 0.110 0.004
3.683 0.66 0.406 0.203 16.46 16.46 14.99 14.99 17.27 17.27 2.296
3.81 0.711 0.457 0.254 16.59 16.59
3.937 0.813 0.559 0.356 16.71 16.71 16.00 16.00 17.78 17.78 2.794 0.10
0.050 0.610 0.610 0.690 0.690 0.100
1.27
BSC
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane G
D
b b
A1
1
y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W79E201
48-pin LQFP
HD D
36 25
Symbol
Dimension in mm Min. Nom.
--0.05 1.35 0.17 0.09 ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 0.45 0.60 1.00 --0 0.08 3.5 --7 0.75
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
c
Notes:
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
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W79E201
26. APPLICATION NOTE
In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W79E201 Flash EPROM microcontroller. In this example, microcontroller will boot from 16 KB AP Flash EPROM and waiting for a key to enter in-system programming mode for re-programming the contents of 16 KB AP Flash EPROM. While entering in-system programming mode, microcontroller executes the loader program in 4KB LD Flash EPROM. The loader program erases the 16 KB AP Flash EPROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 16KB AP Flash EPROM. If the customer uses the reboot mode to update his program, please enable this b3 of security bit from the writer. Please refer security bits for detail description
EXAMPLE 1:
;******************************************************************************************************************* ;* Example of 64K AP Flash EPROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating the content of AP Flash EPROM code else executes the current ROM code. ;* XTAL = 24 MHz ;******************************************************************************************************************* .chip 8052 .RAMCHK OFF .symbols CHPCON TA SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU ORG LJMP 100H 0H ; JUMP TO MAIN PROGRAM 9FH C7H ACH ADH AEH AFH
;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG CLR MOV MOV RETI 00BH TR0 TL0,R6 TH0,R7 ; TR0 = 0, STOP TIMER0
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W79E201
;************************************************************************ ;* 64K AP Flash EPROM MAIN PROGRAM ;************************************************************************ ORG MAIN_64K: MOV ANL CJNE JMP PROGRAM_64: MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV PROGRAMMING ;************** ****************************************************************** ;* Normal mode 64KB AP Flash EPROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . ; User's application program . . . TA, #AAH TA, #55H CHPCON, #03H ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE SFRCN, #0H TCON, #00H IP, #00H IE, #82H R6, #F0H R7, #FFH TL0, R6 TH0, R7 TMOD, #01H TCON, #10H PCON, #01H ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ; TR = 0 TIMER0 STOP ; IP = 00H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ; TL0 = F0H ; TH0 = FFH ; CHPCON register is written protect by TA register. A,P1 A,#01H A,#01H,PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE NORMAL_MODE ; SCAN P1.0 100H
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W79E201
EXAMPLE 2:
;***************************************************************************************************************************** ;* Example of 4KB LD Flash EPROM program: This loader program will erase the 64KB AP Flash EPROM first, ;* then reads the new code from external SRAM and program them into 64KB AP Flash EPROM. ;* XTAL = 24 MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON TA SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H ; JUMP TO MAIN PROGRAM 9FH C7H ACH ADH AEH AFH
;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR MOV MOV RETI ;************************************************************************ ;* 4KB LD Flash EPROM MAIN PROGRAM ;************************************************************************ ORG MAIN_4K: MOV MOV MOV MOV MOV MOV TA,#AAH TA,#55H CHPCON,#03H SFRCN,#0H TCON,#00H TMOD,#01H ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. 100H TR0 TL0, R6 TH0, R7 ; TR0 = 0, STOP TIMER0
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MOV MOV MOV MOV MOV MOV MOV MOV UPDATE_64K: MOV MOV MOV MOV MOV MOV MOV MOV ERASE_P_4K: MOV MOV MOV ;* BLANK CHECK ;********************************************************************* MOV MOV MOV MOV MOV MOV MOV SETB MOV MOV CJNE INC MOV SFRCN,#0H SFRAH,#0H SFRAL,#0H R6,#FDH R7,#FFH TL0,R6 TH0,R7 TR0 PCON,#01H A,SFRFD A,#FFH,blank_check_error SFRAL A,SFRAL ; next address ; enable TIMER 0 ; enter idle mode ; read one byte ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S. ; SFRCN = 00H, READ 64KB AP Flash EPROM ; START ADDRESS = 0H SFRCN,#22H TCON,#10H PCON,#01H ; SFRCN = 22H, ERASE 64K AP Flash EPROM ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (FOR ERASE OPERATION) TCON,#00H IP,#00H IE,#82H TMOD,#01H R6,#D0H R7,#8AH TL0,R6 TH0,R7 ; TCON = 00H , TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 ms ;DEPENDING ON USER'S SYSTEM CLOCK RATE. IP,#00H IE,#82H R6,#F0H R7,#FFH TL0,R6 TH0,R7 TCON,#10H PCON,#01H ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED
;*********************************************************************
blank_check_loop:
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W79E201
JNZ INC MOV CJNE JMP JMP blank_check_loop SFRAH A,SFRAH A,#0H,blank_check_loop PROGRAM_64KROM $ ; end address = FFFFH
blank_check_error: ;******************************************************************************* ;* RE-PROGRAMMING 64KB AP Flash EPROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV MOV MOV MOV MOV MOV MOV MOV MOV PROG_D_64K: MOV CALL MOV MOV MOV MOV INC INC CJNE INC MOV CJNE SFRAL,R2 @DPTR,A SFRFD,A TCON,#10H PCON,#01H DPTR R2 R2,#0H,PROG_D_64K R1 SFRAH,R1 R1,#0H,PROG_D_64K ; SFRAL = LOW BYTE ADDRESS ; SAVE DATA INTO SRAM TO VERIFY CODE. ; SFRFD = data IN ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (PRORGAMMING) GET_BYTE_FROM_PC_TO_ACC ; tHIs prOGRAM IS BASED ON USER'S CIRCUIT. R2,#00H R1,#00H DPTR,#0H SFRAH,R1 SFRCN,#21H R6,#9CH R7,#FFH TL0,R6 TH0,R7 ; SFRAH, Target high address ; SFRCN = 21H, PROGRAM 16K AP Flash EPROM ; SET TIMER FOR PROGRAMMING, ABOUT 50 S. ; Target low byte address ; TARGET HIGH BYTE ADDRESS
;***************************************************************************** ; * VERIFY 16KB AP Flash EPROM BANK ;***************************************************************************** MOV MOV R4,#03H R6,#FDH ; ERROR COUNTER ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S.
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W79E201
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV INC MOVX INC CJNE CJNE INC MOV CJNE R7,#FFH TL0,R6 TH0,R7 DPTR,#0H R2,#0H R1,#0H SFRAH,R1 SFRCN,#00H SFRAL,R2 TCON,#10H PCON,#01H R2 A,@DPTR DPTR A,SFRFD,ERROR_64K R2,#0H,READ_VERIFY_64K R1 SFRAH,R1 R1,#0H,READ_VERIFY_64K ; The start address of sample code ; Target low byte address ; Target high byte address ; SFRAH, Target high address ; SFRCN = 00H, Read AP Flash EPROM ; SFRAL = LOW ADDRESS ; TCON = 10H, TR0 = 1,GO
READ_VERIFY_64K:
;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV MOV MOV ERROR_64K: DJNZ R4,UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYST PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. . . . TA,#AAH TA,#55H CHPCON,#83H ; SOFTWARE RESET. CPU will restart from AP Flash EPROM
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27. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2
November 9, 2004 December 16, 2004
58 / 60
Initial Issued 1. To add PWM Function Description 2. To add ADC Function Description
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: December 16, 2004 Revision A2

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