|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
FDS8876 N-Channel PowerTrench(R) MOSFET April 2005 FDS8876 N-Channel PowerTrench(R) MOSFET 30V, 12.5A, 8.2m Features r DS(ON) = 8.2m, VGS = 10V, ID = 12.5A r DS(ON) = 10.2m, VGS = 4.5V, ID = 11.4A High performance trench technology for extremely low r DS(ON) Low gate charge High power and current handling capability General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r DS(ON) and fast switching speed. Applications DC/DC converters Branding Dash 5 5 4 3 2 1 6 7 1 2 3 4 8 SO-8 (c)2005 Fairchild Semiconductor Corporation FDS8876 Rev. A 1 www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TA = 25oC, VGS = 10V, R JA = 50oC/W) Continuous (TA = 25 C, VGS = 4.5V, RJA = 50 C/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature o o Ratings 30 20 12.5 11.4 Figure 4 105 2.5 20 -55 to 150 Units V V A A A mJ W mW/oC o C Thermal Characteristics RJC RJA RJA Thermal Resistance, Junction to Case (Note 2) Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 25 50 85 oC/W o o C/W C/W Package Marking and Ordering Information Device Marking FDS8876 FDS8876 Device FDS8876 FDS8876_NL (Note 4) Package SO-8 SO-8 Reel Size 330mm 330mm Tape Width 12mm 12mm Quantity 2500 units 2500 units Electrical Characteristics TA = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 24V VGS = 0V VGS = 20V TA = 150oC 30 1 250 100 V A nA On Characteristics VGS(TH) Gate to Source Threshold Voltage V GS = VDS, ID = 250A ID = 12.5A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 11.4A, VGS = 4.5V ID = 12.5A, VGS = 10V, TA = 150oC 1.2 2.5 V 0.0068 0.0082 0.0083 0.0102 0.0109 0.0141 Dynamic Characteristics CISS COSS CRSS RG Qg(TOT) Qg(5) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 15V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V ID = 12.5A Ig = 1.0mA 0.5 1650 330 180 2.3 28 15 1.5 4.3 2.8 5.0 4.0 36 20 2 pF pF pF nC nC nC nC nC nC 2 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Switching Characteristics (VGS = 10V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 12.5A VGS = 10V, RGS = 10 8 34 53 19 63 108 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 12.5A ISD = 2.1A ISD = 12.5A, dISD/dt=100A/s ISD = 12.5A, dISD/dt=100A/s 1.25 1.0 21 10 V V ns nC Notes: 1: Starting TJ = 25C, L = 1mH, IAS = 14.5A, VDD = 30V, VGS = 10V. 2: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R JC is guaranteed by design while RJA is determined by the user's board design. 3: RJA is measured with 1.0 in2 copper on FR-4 board 4: FDS8876_NL is lead free product. FDS8876_NL marking will appear on the reel label. 3 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 1.2 16 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 12 VGS = 10V 8 VGS = 4.5V 0.8 0.6 0.4 4 RJA=50 oC/W 0.2 0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (o C) TA , AMBIENT TEMPERATURE (oC) 0 Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Ambient Temperature RJA=50oC/W ZJA, NORMALIZED THERMAL IMPEDANCE 0.1 PDM 0.01 SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 0.001 10-5 10-4 10 -3 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 10 2 103 Figure 3. Normalized Maximum Transient Thermal Impedance 1400 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) TA = 25oC FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 100 VGS = 4.5V VGS = 10V 10 10-5 10-4 10-3 10-2 10-1 t , PULSE WIDTH (s) 100 101 102 103 Figure 4. Peak Current Capability 4 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V IAS, AVALANCHE CURRENT (A) 40 30 TJ = 25oC 10 STARTING TJ = 25o C 20 TJ = 150oC 10 TJ = -55oC STARTING TJ = 150o C 1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 0 2.0 2.5 3.0 3.5 VGS , GATE TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Unclamped Inductive Switching Capability 50 VGS = 10V ID, DRAIN CURRENT (A) 40 VGS = 3.5V 30 VGS = 3V 20 VGS = 5V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 40 50 Figure 6. Transfer Characteristics PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 12.5A 30 20 10 TA = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0.2 0.4 0.6 VDS , DRAIN TO SOURCE VOLTAGE (V) 0.8 10 ID = 1A 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) 0 Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Gate Voltage and Drain Current 1.2 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.4 NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 1.2 0.8 1.0 0.6 0.8 VGS = 10V, ID = 12.5A 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.4 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature 5 FDS8876 Rev. A Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.05 COSS CDS + C GD 1000 CRSS = CGD 3000 CISS = CGS + C GD 1.00 0.95 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz 0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) 100 0.1 1 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8 Figure 12. Capacitance vs Drain to Source Voltage 6 4 2 WAVEFORMS IN DESCENDING ORDER: ID = 12.5A ID = 1A 0 5 10 15 20 25 30 0 Qg, GATE CHARGE (nC) Figure 13. Gate Charge Waveforms for Constant Gate Currents 6 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD + BVDSS VDS VDD IAS 0.01 0 tAV Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms VDS RL VDD Qg(TOT) VDS Qg(5) + VGS VGS = 10V VGS Qgs2 VDD VGS = 5V DUT Ig(REF) VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% 90% VGS 50% PULSE WIDTH 50% RGS VGS 0 10% Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms 7 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. (T -T ) JM A P = -----------------------------DM R JA maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 64 + ------------------------------- 26 0.23 + Area (EQ. 2) (EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 200 RJA = 64 + 26/(0.23+Area) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized 150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 RJA (o C/W) 150 100 50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10 Figure 21. Thermal Resistance vs Mounting Pad Area ZJA, THERMAL IMPEDANCE (o C/W) 120 90 60 30 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 Figure 22. Thermal Impedance vs Mounting Pad Area 8 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET PSPICE Electrical Model .SUBCKT FDS8876 2 1 3 ; Ca 12 8 10.3e-10 Cb 15 14 10.3e-10 Cin 6 8 1.6e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 10 rev January 2005 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 18 DRAIN 2 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B 13 8 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 SOURCE 3 21 16 EBREAK RSLC2 5 51 ESG + 6 8 LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 CA It 8 17 1 Lgate 1 9 5.29e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.18e-10 RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.6e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3.8e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=5.6e-3 TRS1=8e-4 TRS2=2e-7 + CJO=5.7e-10 M=0.52 TT=7e-11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=5.3e-10 IS=1e-30 N=10 M=0.37) .MODEL MmedMOD NMOS (VTO=1.9 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MstroMOD NMOS (VTO=2.42 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.62 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=8.0e-3 TC2=1.0e-6) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6) .MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 9 FDS8876 Rev. A + Ebreak 11 7 17 18 33.7 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 DBODY MWEAK MMED www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET SABER Electrical Model REV January 2005 template FDS8876 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=5.6e-3,trs1=8e-4,trs2=2e-7,cjo=5.7e-10,m=0.52,tt=7e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5.3e-10,isl=10e-30,nl=10,m=0.37) m..model mmedmod = (type=_n,vto=1.9,kp=5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.42,kp=150,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.62,kp=0.02,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) LDRAIN DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) DRAIN 2 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5) RLDRAIN RSLC1 c.ca n12 n8 = 10.3e-10 51 c.cb n15 n14 = 10.3e-10 RSLC2 c.cin n6 n8 = 1.6e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33.7 spe.eds n14 n8 n5 n8 = 1 GATE 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.29e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.18e-9 res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8 CA S1A 12 S1B 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY RLGATE LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE RBREAK 18 RVTEMP 19 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 2.6e-3, tc1=8.0e-3,tc2=1.0e-6 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.8e-3, tc1=1e-3,tc2=3e-6 res.rvthres n22 n8 = 1, tc1=-2.0e-3,tc2=-6e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } 10 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET SPICE Thermal Model REV January 2005 FDS8876 Copper Area =1.0 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 th JUNCTION RTHERM1 CTHERM1 8 RTHERM2 CTHERM2 7 RTHERM3 CTHERM3 6 SABER Thermal Model SABER thermal model FDS8876 Copper Area = 1.0 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 } RTHERM4 CTHERM4 5 RTHERM5 CTHERM5 4 RTHERM6 CTHERM6 3 RTHERM7 CTHERM7 2 RTHERM8 CTHERM8 tl CASE TABLE 1. THERMAL MODELS COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25 11 FDS8876 Rev. A www.fairchildsemi.com FDS8876 N-Channel PowerTrench(R) MOSFET TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET (R) UniFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production 12 FDS8876 Rev. A www.fairchildsemi.com |
Price & Availability of FDS8876 |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |