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SPICE Device Model SI7440DP Vishay Siliconix N-Channel 30-V (D-S) Fast Switching MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70670 24-May-04 www.vishay.com 1 SPICE Device Model SI7440DP Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 1.5 824 0.0052 0.0064 61 0.75 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 A VDS 5 V, VGS = 10 V VGS = 10 V, ID = 21 A VGS = 4.5 V, ID = 19 A VDS = 15 V, ID = 21 A IS = 4.3 A, VGS = 0 V V A 0.0053 0.0065 65 0.72 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = 4.3 A, di/dt = 100 A/s VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, RG = 6 VDS = 15 V, VGS = 4.5 V, ID = 21 A 30 10.5 10 22 12 50 49 36 29 10.5 10 18 16 75 41 50 Ns nC Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70670 24-May-04 SPICE Device Model SI7440DP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70670 24-May-04 www.vishay.com 3 |
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