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PRELIMINARY CM9107 Triple-Output LDO for WLAN
Features
* * * * * * * * * * * * * * 3.0V to 3.6V input voltage range Preset output voltage with excellent line and load regulation LDO1 = 1.80V/500mA, 1.5% max load regulation LDO2 = 2.84V/300mA, 1% max load regulation LDO3 = 2.84V/200mA, 1% max load regulation Low output noise (<30Vrms for LDO3) Low dropout voltage; 135mV (typ.) for LDO2 at 300mA, and 110mV (typ.) for LDO3 at 200mA. Low quiescent current, < 600A typical Integrated microprocessor RESET circuit with adjustable RESET delay (2.5ms per-nF of CT) Logic controlled shutdown Power good signal Built-in power up and power down sequence con trol between LDO1 and LDO2 Over-temperature and over-current protection TQFN-16, RoHS compliant lead-free package
Product Description
The CM9107 is a triple-output, low noise, low dropout (LDO) linear regulator with an integrated microproces sor reset circuit. It is designed for use with wireless local-area network chipsets. It has an input voltage range of 3.0V to 3.6V, and supplies a 500mA, 1.80V preset output (LDO1); a 300mA, 2.84V output (LDO2), and a 200mA, low noise output of 2.84V (LDO3). The CM9107 has excellent line and load regulation over the operating temperature range. The CM9107 LDOs features low dropout voltage by using efficient P-channel MOSFETs for each output. It also features a power good signal (active high) when all three LDOs are in regulation. It provides two shut down control pins, LDO1 and LDO2 power sequencing, plus short-circuit and over-temperature shutdown pro tection. The CM9107 also provides a microprocessor RESET circuit with RST and RST outputs. The RESET signal is asserted when the VIN supply voltage drops below 2.63V, remaining asserted for the adjustable RESET delay period, controlled by an external capacitor on the CT pin. The CM9107 is packaged in a 16-pin TQFN (4mm x 4mm) package. It can operate over the industrial tem perature range of -40C to 85C.
Applications
* * * Wireless LAN 802.11 chipset power supply Wireless LAN cards Wireless instrumentation
Typical Application
3.0V to 3.6V 10uF CIN 16
RST
15
PGOOD VIN3
14
VIN
13
1 RST 2 0.01uF CT CT
12 VO1 11 Co1
1.8V, 500mA Baseband 3.3uF 2.84V, 300mA Co2 3.3uF
Processor/ MAC
CM9107
GND3
CB1 10 VO2 CC2 9 Cb 0.033uF
Analog Circuitry
3 SHDN 4 SHDN3
CC3 VO3
5
6
7
8 2.84V, 200mA
VCO
GND
Co3
3.3uF
(c) 2006 California Micro Devices Corp. All rights reserved. 07/11/06
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PRELIMINARY CM9107
Package Pinout
PACKAGE / PINOUT DIAGRAM
TOP VIEW
(Pins Down View)
Pin 1 Marking
PGOOD VIN3 RST VIN
BOTTOM VIEW
(Pins Up View)
13
14
15
16
15
14
13
RST CT SHDN SHDN3
1
12 VO1
12 11 10 9
16
1
CM910 700QE
2 3 4
11 CB1 10 VO2 9 CC2
GND PAD
2 3 4
8
7
6
VO3 5
CC3 6
GND3 7
CM9107-00QE 16-Lead TQFN Package (4mmx4mm)
Note: This drawing is not to scale.
LEAD(s) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NAME
DESCRIPTION Reset bar pin. This is the inverse output of the RST signal pin (pin 16). CT pin for setting the delay time for RST assert (2.5ms per nF). Shutdown control input pin for LDO1 and LDO2. Active low, LDO1 and LDO2 will be off when the pin is pulled low. Connect to VIN when unused. Shutdown control input pin for LDO3. Active low. Connect to VIN when unused. LDO3 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2F, minimum. This pin is used for testing. In the application it could be either floating or tied to ground Ground pin for LDO3 Ground pin for LDO1, LDO2 and control circuit This pin is used for testing. In the application it could be either floating or tied to ground LDO2 output pin (2.84V). Connect a low-ESR bypass capacitor of 2.2F, minimum. Bypass capacitor pin for internal bandgap reference (typically 0.033F low-ESR type). LDO1 output pin (1.80V). Connect a low-ESR bypass capacitor of 2.2F, minimum. Power input pin for LDO2 and LDO3. Connect to a low-ESR bypass capacitor of 2.2F, minimum. Power input pin for LDO3. Connect to Pin 13, on the PC board, very near the device. Power good output pin with internal pull-up resistor to VIN, goes high when all 3 LDOs are in regulation.
RST
CT SHDN SHDN3 VO3 CC3 GND3 GND CC2 VO2 CB1 VO1 VIN VIN3 PGOOD
(c) 2006 California Micro Devices Corp. All rights reserved.
2
GND 8
PIN DESCRIPTIONS
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PRELIMINARY CM9107
Pin Descriptions (cont'd)
PIN DESCRIPTIONS
16 RST Reset output pin. When VIN falls below the RESET threshold, this RST pin is asserted (active high). When VIN rises above the RESET threshold, RST goes low after a delay of 2.5ms per nF of CT capacitance. Refer to RESET section in the Application Information.
Ordering Information
PART NUMBERING INFORMATION
Lead Free Finish Pins 16 Package TQFN Ordering Part Number1 CM9107-00QE Part Marking CM9107 00QE
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER ESD Protection (HBM) VIN, VIN3, GND3 to GND Pin Voltages VO1, VO2, VO3 to GND CB1 to GND to GND SHDN, SHDN3 to GND CT, RST, RST, PGOOD to GND Storage Temperature Range Operating Temperature Range (Ambient) Lead Temperature (Soldering, 10sec) RATING 2 [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 [GND - 0.3] to +5.0 [GND - 0.3] to +5.0 -65 to +150 -40 to +85 300 UNITS kV V
V V V V C C C
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL VIN IQ VSHDN VIL VIH TSTART PARAMETER Input Supply Voltage Quiescent Current Shutdown Supply Current Shutdown (active low) Input Low Threshold Shutdown Input High Threshold Start-up Time (from SHDN going high to VOUT in regulation) (Note 3) All outputs are no load SHDN = SHDN3 = 0 CONDITIONS MIN 3.0 TYP 3.3 600 5.0 MAX 3.6 750 10 0.4 2.0 VOUT = 95% of final value 120 UNITS V A A V V s
(c) 2006 California Micro Devices Corp. All rights reserved. 07/11/06
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PRELIMINARY CM9107
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL TPGOOD OPGOOD TOVER THYS UVLO LDO1 VOUT VOUT acc ILIM VR LIN VR LOAD VOUT N LDO2 VOUT VOUT acc ILIM VR LIN VR LOAD VDROP VOUT N LDO3 VOUT VOUT acc ILIM VR LIN VR LOAD VDROP VOUT N RESET TRESET THYS RESET VDROP RESETD TRST Output Voltage Output Voltage Accuracy Over-current Limit (Note 2) Line Regulation Load Regulation (Note 5) Dropout Voltage (Note 4) Output Noise VIN3 = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 200mA IOUT = 200mA 10Hz < f < 100kHz, IOUT = 10mA Co3 = 2.2F Co3 = 10F IOUT = 10mA -1.5 250 -0.15 0.2 110 30 20 450 0.15 1.0 200 2.84 +1.5 V % mA %/V % mV Vrms Vrms Output Voltage Output Voltage Accuracy Over-current Limit (Note 2) Line Regulation Load Regulation (Note 5) Dropout Voltage (Note 4) Output Noise VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 300mA IOUT = 30 mA 10Hz < f < 100kHz, IOUT = 10mA Co2 = 2.2F Co2 = 10F IOUT = 10mA -1.5 330 -0.15 0.2 135 70 60 550 0.15 1.0 220 2.84 +1.5 V % mA %/V % mV Vrms Vrms PARAMETER PGOOD Threshold PGOOD Output Level OTP Threshold OTP Hysteresis Undervoltage Lockout (Note 2) Output Voltage Output Voltage Accuracy Over-current Limit (Note 2) Line Regulation Load Regulation (Note 5) Output Noise VIN = 3.0V to 3.6V, IOUT = 10mA IOUT =10mA to 500mA 10Hz < f < 100kHz, Co1 = 3.3F, IOUT = 50mA IOUT = 10mA -1.5 550 -0.15 -1.5 100 750 0.15 1.5 All outputs are no load. 2.20 CONDITIONS All output currents = 50% rating ISINK = 2mA 150 20 2.45 1.80 +1.5 2.65 MIN -5 TYP MAX +5 0.25 UNITS % V C C V V % mA %/V % Vrms
RESET Threshold (Vth) (Note 2) RESET Threshold Hysteresis VIN Dropout Reset Delay RST / RST Timeout Period (Note 2) VCC = Vth to Vth -100mV CT = 10nF
2.56
2.63 10 20
2.69
V mV s ms
25
(c) 2006 California Micro Devices Corp. All rights reserved.
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PRELIMINARY CM9107
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL VRST_L VRST_H IQ RST PARAMETER RST / RST Output Low Signal RST / RST Output High Signal RESET Block Quiescent Current .8 x VIN 4 CONDITIONS MIN TYP MAX 0.4 UNITS V V A
Note 1: VIN = VIN3 = 3.3V. CIN = 10F, CO1 = CO2 = CO3 = 3.3F, CB = 33nF. TA = 25C unless otherwise specified. Note 2: Parameter is guaranteed by design, not production tested. Note 3: The start-up time is defined as from SHDN pin goes high until Vo1 reaches regulation; or from SHDN3 goes high until VO3 reaches regulation. Note 4: The dropout voltage is defined as Vind- Vod, where Vod is 50mV below VOUT value measured at VIN = 3.3V. Note 5: Regulation is measured at constant junction temperature using low duty cycle pulse testing.
Functional Block Diagram
CC2 3.3V VIN
CIN 10uF
CC3
CB1
Cb
UVLO & Bandgap
LDO1
0.033uF 1.8V 500mA CO1 3.3uF
PGOOD Pgood Logic
Window Comparator
VO1
GND
LDO2
SHDN SHDN3 Control Logic Enables
Window Comparator 2.84V
VO2 300mA
CO2 3.3uF
VIN RST RST CT
CT .01uF
OTP 150oC
LDO3
Reset Circuit
VIN3
2.84V 200mA CO3
Window Comparator
VO3
CM9107
GND3
3.3uF
(c) 2006 California Micro Devices Corp. All rights reserved. 07/11/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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PRELIMINARY CM9107
Typical Performance Curves
Vout = 1.8V Load = 50 mA 20 0
Output Voltage Deviation (mV)
Output Voltage Deviation (mV)
Vout = 2.84V Load = 50 mA 20 0
Input Voltage (V)
Input Voltage (V)
4 3
4 3
Time (1 ms/div)
Time (10 ms/div)
Line Reguation Response, LDO1
Output Voltage Deviation (mV) Output Voltage Deviation (mV) Vout = 2.84V Load = 50 mA
Line Reguation Response, LDO2
Vout = 1.8V Vin = 3.3V
20 0
20 10 0
Input Voltage (V)
Load Current (mA) Time (1 ms/div)
4 3
100 0
Time (5 ms/div)
Line Reguation Response, LDO3
Output Voltage Deviation (mV) Output Voltage Deviation (mV) Vout = 2.84V Vin = 3.3V
Load Reguation Response, LDO1
Vout = 2.84V Vin = 3.3V
20 10 0
20 10 0
Load Current (mA)
0
Load Current (mA)
100
100 0
Time (10 ms/div)
Time (20 ms/div)
Load Reguation Response, LDO2
Load Reguation Response, LDO3
(c) 2006 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM9107
Application Information
The CM9107 is a triple-output, low noise, low dropout (LDO) linear voltage regulator with an integrated micro processor reset circuit. It provides a single-chip power management solution for WLAN systems, providing the fixed output voltages needed for popular wireless chipsets. It has an input voltage range of 3.0V to 3.6V. The device can supply 500mA output from LDO1 (1.8V), 300mA from LDO2 (2.84V) and 200mA from the low-noise LDO3 (2.84V). The CM9107 achieves its low dropout voltage by using efficient, internal P-channel MOSFETs for each output. The dropout voltage for LDO2 is less than 220mV at 300mA load. The dropout voltage for LDO3 is less than 200mV at 200mA load. The lower voltage output from LDO1 assures sufficient headroom to deliver 500mA once VIN is above the undervoltage lockout point, typi cally 2.45V. The CM9107 has excellent line and load regulation over the operating temperature range. The LDO outputs allow the use of low cost, space-efficient ceramic capacitors. The LDO3 has exceptionally low output noise, and is ideal for VCO power supplies. The WLAN's VCO circuit is very phase noise sensitive, and needs clean power for reliable operation. At 10mA output, the noise den sity from 10Hz to 100kHz is typically less than 30VRMS when using a 2.2F output capacitor. With a 10F output capacitor, the noise density is typically 20VRMS. +/-5% of their nominal regulation value. The PGOOD pin will go low when any output is out of regulation due to over-current dropout, or when thermal shutdown is triggered. The PGOOD pin has an internal pull-up resistor. In the shutdown mode (SHDN and SHDN3 both low), PGOOD goes high.
Shutdown Control and Power Up/Down Sequence
The CM9107 provides two active low, shutdown control pins, SHDN and SHDN3. SHDN controls both LDO1 and LDO2. LDO3 is independently controlled with SHDN3. Each shutdown pin has internal pull-up resis tor to VIN. Pulling the pins low shuts-down the appropri ate output. When SHDN goes high, LDO1's output will rise first. Once LDO1's output is above about 1.7V, LDO2's out put will start to rise. When SHDN goes low, LDO2's output will drop first. When LDO2's output drops below about 2.7V, LDO1's output will start to drop. Refer to Figure 1.
SHDN
Protection
The CM9107 has independent over-current protection for each LDO output, with current foldback. The mini mum over-current limit is 550mA for LDO1, 330mA for LDO2, and 250mA for LDO3. The CM9107 includes a thermal shutdown. If there is excessive internal power dissipation due to an over current condition, or a high VIN-VOUT differential, and device's junction temperature exceeds 150C (typical), the outputs are turned off. The LDOs are turned on again after the junction temperature drops below 130C.
VO1 1.71V
Power down sequence 1.80V Power up sequence
VO2
2.84V 2.70V
Figure 1. Power Sequencing
Power Good
The CM9107 provides a high power good signal (PGOOD) if all three LDOs output voltages are within
(c) 2006 California Micro Devices Corp. All rights reserved. 07/11/06
Reset
The CM9107's RESET circuit monitors the VIN voltage only, upstream of the LDOs. This circuit is completely
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM9107
Application Information (cont'd)
independent of the three LDOs and their control cir cuits, functioning as a supervisory circuit for the MAC/ Baseband microprocessor. The RESET circuit has complimentary RST and RST push-pull outputs. When the system is powered-up and VIN reaches a pre-set threshold, RESET waits for the programmed time-period and then signals the microprocessor that VIN is stable. During system operation, VIN is continu ously monitored, and if it drops below the preset threshold, it tells the microprocessor to reset, thus pre venting loss of data. The RESET signals are asserted when the VIN supply voltage drops below 2.63V and will remain asserted for the adjustable RESET delay period, controlled by con necting an external capacitor on the CT pin. The RESET delay period is 2.5ms/nF of CT pin capaci tance. At the end of the delay period, the RESET sig nals are released; RST goes low and RST goes high. Refer to Figure 2. If VIN drops below the RESET threshold again, the RESET signal is re-asserted. The reset delay and threshold hysteresis help assure valid RESET signals in the presence of erratic VIN behavior. The maximum low output voltage is 0.3V at 1.6mA sink current. Minimum high output voltage is 80% of VIN. The RESET circuit consumes less than 5A quiescent current.
20 s delay VIN
2.63V
Capacitor Selection
The CM9107's LDOs have a wide stability region for a range of output capacitance and ESR values. While 2.2F will be sufficient for each LDO output, higher out put capacitance, such as 3.3F, 4.7F or 10F, will reduce output noise and over-shoot during load tran sients. Low ESR ceramic capacitors are ideally suited for the outputs of the CM9107, with X5R and X7R dielectrics being the most stable over voltage and tem perature, providing the best performance. To reduce the noise generated by the bandgap circuit, a 33nF, low ESR ceramic capacitor is recommended from the CB1 pin to ground.
Load Transient
The input and output capacitors will effect the transient load response. The input capacitor will reduce input drop during load transients, improving response on all outputs, while increased output capacitance improves the individual LDO output's load transient response.
Layout Issues
Input and output capacitors should be located close to the device. For good thermal conduction, connections to large areas of CU should be provided on the PCB.
RST
25 ms delay (CT = 0.01 F)
RST
Figure 2. Reset Delay
(c) 2006 California Micro Devices Corp. All rights reserved.
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Tel: 408.263.3214
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Fax: 408.263.7846
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PRELIMINARY CM9107
Application Circuit
Power Good CIN Reset 16 RST 15 PGOOD 14 VIN3 13 VIN 10uF
+ 3.3V
Reset
1 2
RST CT SHDN
VO1 CB1 VO2 GND3
12 11 10 Co2 3.3uF Co1 3.3uF
VOUT1 +1.8V
CT
0.01uF
3 4
CM9107
VOUT2 +2.84V
LDO 1 & 2
GND
VO3
CC3
Shutdown
SHDN3
CC2 9 Cb 0.033uF
Shutdown
LDO 3
5
6
7
8 VOUT3 +2.84V 3.3uF
Co3
Bill of Materials
BILL OF MATERIALS
ITEM 1 2 3 4 QUANTITY 1 3 1 1 REFERENCE CIN Co1, Co2, Co3 CT CB PART 10F/10V/1210/X7R 3.3F/10V/1206/X7R .01F/10V/X7R .033F/10V/X7R MFR any any any any
(c) 2006 California Micro Devices Corp. All rights reserved. 07/11/06
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Tel: 408.263.3214
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PRELIMINARY CM9107
Mechanical Details
TQFN-16 Mechanical Specifications The CM9107-00QE is supplied in a 16-lead, 4.0mm x 4.0mm TQFN package. Dimensions are presented below. For complete information on the TQFN16, see the Cal ifornia Micro Devices TQFN Package Information doc ument. Mechanical Package Diagrams
D
PACKAGE DIMENSIONS
Package Leads Dim. A A1 A3 b D D1 E E1 e L # per tape and reel 0.25 3.85 2.40 3.85 2.40 Millimeters Min 0.70 0.00 Nom 0.75 0.02 0.203 REF 0.30 4.00 2.50 4.00 2.50 0.65 BSC. 0.40 BSC 3000 pieces 0.35 4.15 2.80 4.15 2.80 0.010 0.152 0.094 0.152 0.094 Max 0.8 0.05 Min 0.027 0.000 TQFN-16 (4x4) 16 Inches Nom 0.029 0.001 .008 0.012 0.157 0.098 0.157 0.098 0.026 0.016 0.014 0.163 0.110 0.163 0.110 Max 0.031 0.002
E
Pin 1 Marking
0.15 C 0.15 C
TOP VIEW
0.10 C
0.08 C
SIDE VIEW
A3 A1
A
E1
Controlling dimension: millimeters
D1 L
e
b
16X 0.10
M
CAB
BOTTOM VIEW
Package Dimensions for 16-Lead QFN
(c) 2006 California Micro Devices Corp. All rights reserved.
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Tel: 408.263.3214
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Fax: 408.263.7846
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07/11/06

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