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| ISL9N316AD3ST February 2002 ISL9N316AD3ST N-Channel Logic Level PWM Optimized UltraFET(R) Trench Power MOSFETs General Description This device employs a new advanced trench MOSFET technology and features low gate charge while maintaining low on-resistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies. Features * Fast switching * rDS(ON) = 0.014 (Typ), VGS = 10V * rDS(ON) = 0.020 (Typ), VGS = 4.5V * Qg (Typ) = 13nC, VGS = 5V * Qgd (Typ) = 4.5nC * CISS (Typ) = 1450pF Applications * DC/DC converters DRAIN (FLANGE) D GATE SOURCE G S TO-252 MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 4.5V) Continuous (TC = 25oC, VGS = 10V, RJA = 52oC/W) Pulsed PD TJ, TSTG Power dissipation Derate above 25oC Operating and Storage Temperature 48 28 10 Figure 4 65 0.43 -55 to 175 A A A A W W/oC o Ratings 30 20 Units V V C Thermal Characteristics RJC RJA RJA Thermal Resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 2.31 100 52 o C/W C/W oC/W o Package Marking and Ordering Information Device Marking N316AD Device ISL9N316AD3ST Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST Electrical Characteristics TA = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 25V VGS = 0V VGS = 20V TC = 150o 30 1 250 100 V A nA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 48A, VGS = 10V ID = 28A, VGS = 4.5V 1 0.014 0.020 3 0.0155 0.023 V Dynamic Characteristics CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (VGS = 4.5V) VDD = 15V, ID = 10A VGS = 4.5V, RGS = 11 (VGS = 10V) VDD = 15V, ID = 10A VGS = 10V, RGS = 11 8 30 45 30 57 115 ns ns ns ns ns ns 15 60 25 30 115 83 ns ns ns ns ns ns VDS = 15V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 1V VGS = 0V to 5V V = 15V DD ID = 28A Ig = 1.0mA 1450 300 120 25 13 1.5 4.3 4.5 38 20 2.3 pF pF pF nC nC nC nC nC Switching Characteristics tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Switching Characteristics tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Unclamped Inductive Switching tAV Avalanche Time ID = 2.9A, L = 3.0mH 195 s Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 28A ISD = 13A ISD = 28A, dISD/dt = 100A/s ISD = 28A, dISD/dt = 100A/s 1.25 1.0 20 7 V V ns nC (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST Typical Characteristic 1.2 60 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) VGS = 10V 40 0.8 0.6 VGS = 4.5V 20 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Case Temperature ZJC, NORMALIZED THERMAL IMPEDANCE PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x R JC + TC 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 0.01 10-5 10-4 10-3 Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM , PEAK CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I 25 175 - TC 150 VGS = 10V 100 VGS = 5V 40 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST Typical Characteristic (Continued) 100 PULSE DURATION = 80s 80 ID , DRAIN CURRENT (A) DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) 80 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 4.5V 60 VGS = 4.0V VGS = 10V 60 40 TJ = 25oC 20 TJ = 175oC 0 1 2 3 4 5 6 VGS , GATE TO SOURCE VOLTAGE (V) TJ = -55oC 40 20 VGS = 3V 0 0 0.5 1.0 1.5 2.0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics 40 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) ID = 48A 30 Figure 6. Saturation Characteristics 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.5 ID = 28A 20 ID = 10A 1.0 VGS = 10V, ID = 48A 0.5 10 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) Figure 7. Drain to Source On Resistance vs Gate Voltage and Drain Current 1.4 Figure 8. Normalized Drain to Source On Resistance vs Junction Temperature 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A 1.2 NORMALIZED GATE THRESHOLD VOLTAGE ID = 250A 1.1 1.0 0.8 1.0 0.6 0.4 -80 -40 0 40 80 120 (oC) 160 200 0.9 -80 -40 0 40 80 120 (oC) 160 200 TJ, JUNCTION TEMPERATURE TJ , JUNCTION TEMPERATURE Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST Typical Characteristic (Continued) 2000 VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 15V 8 C, CAPACITANCE (pF) 1000 COSS CDS + CGD CISS = CGS + CGD 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 28A ID = 10A CRSS = CGD 2 VGS = 0V, f = 1MHz 100 0.1 1 10 30 0 0 10 20 30 VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 11. Capacitance vs Drain to Source Voltage 150 VGS = 4.5V, VDD = 15V, ID = 10A SWITCHING TIME (ns) Figure 12. Gate Charge Waveforms for Constant Gate Currents 200 VGS = 10V, VDD = 15V, ID = 10A 150 td(OFF) 100 tf 50 tr td(ON) 0 100 tr td(OFF) tf 50 td(ON) 0 0 10 20 30 40 50 SWITCHING TIME (ns) 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () RGS, GATE TO SOURCE RESISTANCE () Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG - BVDSS VDS VDD + VDD IAS 0.01 0 tAV Figure 15. Unclamped Energy Test Circuit (c)2002 Fairchild Semiconductor Corporation Figure 16. Unclamped Energy Waveforms Rev. B, February 2002 ISL9N316AD3ST Test Circuits and Waveforms (Continued) VDS RL VDD VDS Qg(TOT) VGS = 10V VGS Qg(5) VDD DUT Ig(REF) 0 VGS VGS = 1V Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V + Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% 90% VGS 50% PULSE WIDTH 50% RGS VGS 0 10% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - T A ) P DM = -----------------------------Z JA 125 RJA = 33.32 + 23.84/(0.268+Area) 100 RJA (oC/W) 75 (EQ. 1) 50 In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. 25 0.01 0.1 1 10 AREA, TOP COPPER AREA (in2) Figure 21. Thermal Resistance vs Mounting Pad Area R JA = 33.32 + ------------------------------------ 23.84 ( 0.268 + A rea) (EQ. 2) (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST PSPICE Electrical Model .SUBCKT ISL9N316AD3ST 2 1 CA 12 8 9e-10 CB 15 14 9.5e-10 CIN 6 8 1.2e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 31.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 ESG LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 13 8 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 DBODY 5 DRAIN 2 3 ;rev May 2001 RSLC2 5 51 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 - IT 8 17 1 LGATE 1 9 5.61e-9 LDRAIN 2 5 1.0e-9 LSOURCE 3 7 1.98e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2e-3 RGATE 9 20 1.98 RLDRAIN 2 5 10 RLGATE 1 9 56.1 RLSOURCE 3 7 19.8 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 9.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD EVTHRES 16 21 + 19 8 6 S1B CA VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),3))} .MODEL DBODYMOD D (IS = 2.4e-11 N = 1.09 RS = 9.2e-3 TRS1 = 9e-4 TRS2 = 1e-6 XTI=2.2 CJO = 7e-10 M = 0.49 TT = 8e11) .MODEL DBREAKMOD D (RS = 0. 8TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 4e-1 0IS = 1e-3 0N = 10 M = 0.43) .MODEL MMEDMOD NMOS (VTO = 1.625 KP = 4 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.98) .MODEL MSTROMOD NMOS (VTO = 2.08 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.32 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19.8 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7) .MODEL RDRAINMOD RES (TC1 = 1.7e- 2TC2 = 5e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-4 TC2 = 5e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.1e-3 TC2 = -0.5e-5) .MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -1.0) VON = -1.0 VOFF= -4.0) VON = -0.3 VOFF= 0.2) VON = 0.2 VOFF= -0.3) (c)2002 Fairchild Semiconductor Corporation + RDRAIN Rev. B, February 2002 ISL9N316AD3ST SABER Electrical Model REV May 2001 template ISL9N316AD3ST n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, nl = 1.09, rs = 9.2e-3, trs1 = 9e-4, trs2 = 1e-6, xti=2.2, cjo = 7e-10, tt = 8e-11, m = 0.49) dp..model dbreakmod = (rs = 0.8, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 4e-10, isl=10e-30, nl=10, m=0.43) m..model mmedmod = (type=_n, vto = 1.625, kp=4, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.08, kp = 55, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.32, kp = 0.04, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -1.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) LDRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) DPLCAP 5 DRAIN c.ca n12 n8 = 9e-10 c.cb n15 n14 = 9.5e-10 c.cin n6 n8 = 1.2e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod ESG 10 RSLC1 51 RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 50 RDRAIN EVTHRES 16 21 + 19 8 6 MMED MSTRO CIN 8 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 DBREAK 11 DBODY MWEAK EBREAK + 17 18 LSOURCE 7 SOURCE 3 RLDRAIN 2 i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.618e-9 l.lsource n3 n7 = 1.98e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 2e-3, tc1 = 1.7e-2, tc2 = 5e-5 res.rgate n9 n20 = 1.98 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 56.1 res.rlsource n3 n7 = 19.8 res.rslc1 n5 n51= 1e-6, tc1 = 3.5e-4, tc2 =5e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 9.5e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -2.1e-3, tc02 = -5e-6 spe.ebreak n11 n7 n17 n18 = 31.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/110))**3)) } } (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N316AD3ST SPICE Thermal Model REV 23 May 2001 TISL9N316AD3ST CTHERM1 th 6 1.0e-3 CTHERM2 6 5 1.5e-3 CTHERM3 5 4 1.9e-3 CTHERM4 4 3 3e-3 CTHERM5 3 2 5.0e-3 CTHERM6 2 tl 2.5e-2 RTHERM1 th 6 2.5e-3 RTHERM2 6 5 3.5e-3 RTHERM3 5 4 5.2e-2 RTHERM4 4 3 5.0e-1 RTHERM5 3 2 5.7e-1 RTHERM6 2 tl 6.9e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model TISL9N316AD3ST template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.0e-3 ctherm.ctherm2 6 5 = 1.5e-3 ctherm.ctherm3 5 4 = 1.9e-3 ctherm.ctherm4 4 3 = 3e-3 ctherm.ctherm5 3 2 = 5e-3 ctherm.ctherm6 2 tl = 2.5e-2 rtherm.rtherm1 th 6 =2.5e-3 rtherm.rtherm2 6 5 = 3.5e-3 rtherm.rtherm3 5 4 = 5.2e-2 rtherm.rtherm4 4 3 = 5.0e-1 rtherm.rtherm5 3 2 = 5.7e-1 rtherm.rtherm6 2 tl = 6.9e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE (c)2002 Fairchild Semiconductor Corporation Rev. B, February 2002 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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