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CY22313
Two-PLL Clock Generator with Direct RambusTM (Lite) Support
Features
* * * * * * Two integrated phase-locked loops (PLLs) Ultra-accurate PLLs Direct RambusTM clock support Two input selects 3.45V core; 3.45V, 2.5V, 1.8V, and 1.675V outputs 24-pin TSSOP package
Benefits
* High-performance PLL tailored for multimedia applications * Frequency tolerance within 1 PPM on all frequencies * One pair of differential output drivers, identical specification to CY2212 * Selectable 54.0-/53.946-MHz output and 294.912-/393.216-MHz Rambus(R) output * Supports output voltage requirements * Industry-standard packaging saves on board space
Block Diagram
XIN XOUT
XTAL. OSC.
Divide by 2
LCLK
CONFIGURATION LOGIC FS S
PLL1
Divider
54MOUT
CLK PLL2 CLKB
Pin Configuration
VDDRP VSSRP Xout Xin NC VSSVPA VDDVPA VSS54 54MOUT FS VDD54 VDDVP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 S VDDR VSSR CLK CLKB VSSR VDDR NC VDDL VSSL LCLK VSSVP
Frequency Select Tables
FS 0 1 S 0 1 54MOUT 54 53.94605395 CLK, CLKB 294.912 393.216 LCLK 9.216 Unit MHz MHz Unit MHz MHz Unit MHz PPM 0 -1 PPM 0 0 PPM 0
Cypress Semiconductor Corporation Document #: 38-07434 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised June 29, 2004
CY22313
Pin Definitions
Name VDDRP VSSRP Xout Xin NC VSSVPA VDDVPA VSS54 54MOUT FS VDD54 VDDVP VSSVP LCLK VSSL VDDL NC VDDR VSSR CLKB CLK VSSR VDDR S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Numbers Power for DRCG PLL Ground for DRCG PLL Crystal Output Crystal Input Do Not Connect, Leave Floating Analog Ground For Video PLL Analog Power for Video PLL Ground for 54MOUT 54-MHz/53.94605395-MHz Output Frequency Select Pin for 54MOUT (internal pull-down resistor) Power for 54MOUT Power for Video PLL Ground for Video PLL LCLK Output Ground for LCLK Power for LCLK Do Not Connect, Leave Floating Power for DRCG CLK/CLKB Ground for DRCG CLK/CLKB Output Clock to Rambus (complement) Output Clock to Rambus Ground for DRCG CLK/CLKB Power for DRCG CLK/CLKB Frequency Select Pin for DRCG CLK/CLKB (internal pull-up resistor) Pin Description
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CY22313
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guidelines; not tested.) Supply Voltage ............................................... -0.5V to +4.0V DC Input Voltage ..............................-0.5V to + (VDD + 0.5V) Storage Temperature .................................. -65C to +125C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................... 2000V Latch-up (per JEDEC 17) .................................... > 200 mA Min. 3.15 2.25 1.6 1.6 0.05 0 18.432 Typ 3.45 2.5 1.675 1.8 Max. 3.6 2.75 1.75 2.0 500 +85 15 Unit V V V V ms C pF MHz
Recommended Operating Conditions
Parameter VDDRP, VDDVPA, VDDVP, VDDR VDD54 (2.5V) VDD54 (1.675V) VDDL tPU TA CLOAD_54MOUT fREF
[1]
Description Supply Voltage for PLL's, Crystal Oscillator, and 3.45V Outputs Supply Voltage for 2.5V Outputs Supply Voltage for 1.675V Outputs Supply Voltage for 1.8V Outputs Power-up time for all VDDS to reach minimum specified voltage (power ramps must be monotonic) Operating Temperature, Ambient Max. Load Capacitance, CMOS Output External Reference Crystal
Electrical Specifications
Parameter IOH
[2]
Description Output High Current, 2.5V outputs[3] outputs[3] Output High Current, 1.8V outputs[3] Output High Current, 1.675V
Conditions VOH = VDD - 0.5, VDD = 2.5V VOH = VDD - 0.5, VDD = 1.8V VOH = VDD - 0.5, VDD = 1.675V VOL = 0.5V, VDD = 2.5V VOL = 0.5V, VDD = 1.8V Total effective load of internal load caps Except crystal pins CMOS levels,% of VDDRP/VDDVPA/VDDVP CMOS levels,% of VDDRP/VDDVPA/VDDVP Pull-down resistor on FS Pull-up resistor on S Sum of all supply currents
Min. 8 6 5 8 6 5
Typ. 16 12 10 16 12 10 11[4] 7
Max.
Unit mA mA mA mA mA mA pF pF VDD
IOL[2]
Output Low Current, 2.5V outputs[3] Output Low Current, 1.8V outputs[3]
Output Low Current, 1.675V outputs[3] VOL = 0.5V, VDD = 1.675V CXTAL CLOAD_IN VIH VIL RI_FS RI_S IDD Crystal Load Capacitance[3] Input Pin Capacitance[3] HIGH-Level Input Voltage LOW-Level Input Voltage FS Input Resistor S Input Resistor Total Power Supply Current
70% 30% 60 10 150 225 100 125
VDD k k mA
Direct Rambus Electrical Specifications[3]
Parameter VCM VX VCOS VCOH VCOL rOUT Description Differential output common-mode voltage Differential output crossing-point voltage[5] Output Voltage swing (p-p Output high voltage Output low voltage Output dynamic resistance (at pins)[7] 1.0 12 50 single-ended)[6] Min. 1.35 1.25 0.4 Typ. Max. 1.75 1.85 0.7 2.1 Unit V V V V V
Notes: 1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions. 2. LCLK and 54MOUT outputs only. 3. Guaranteed by design, not 100% tested. 4. Identical Crystal Load Capacitance as CY2212ZC-2. Use the same crystal and XIN / XOUT board layout as implemented with the original crystal-driven CY2212ZC-2. 5. Differential output crossing point voltages shown in Figure 1. 6. VCOS = VOH - VOL. 7. rOUT = VO/ IO. This is defined at the output pins, not at the measurement point of Figure 9.
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CY22313
Switching Characteristics[3]
Parameter FPPM DC t3_54, 2.5 t3_54, 1.675 t4_54, 2.5 t4_54, 1.675 tCR, tCF tCR-CF t5 Description Frequency Error Output Duty Cycle Conditions Part to Part, does not include PCB variation Over commercial temperature range[9] Duty cycle for all outputs, measured at VDD/2 45 0.75 0.35 0.75 0.35 160 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 2.5V 54MOUT Rising Edge Slew Rate 20% to 80% of VDD54, VDD54 = 1.675V 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 2.5V 54MOUT Falling Edge Slew Rate 80% to 20% of VDD54, VDD54 = 1.675V CLK/CLKB Rise and Fall Times CLK/CLKB Rise and Fall Difference[10] Lock Time[11] 20% to 80% of output voltage 20% to 80% of output voltage PLL lock time from power-up 1.0
[8]
Min.
Typ. 5 2 50 1.2 0.5 1.2 0.5
Max. 10 5 55 4.0 2.5 4.0 2.5 400 100 3.0
Unit PPM PPM % V/ns V/ns V/ns V/ns ps ps ms
Phase Noise Specifications
Parameter Description Phase Noise Phase Noise Conditions 54 MHz at 10-kHz offset 53.946 MHz at 10-kHz offset Min. Typ. -95 -92 Max. Unit dBc dBc
Jitter Specifications[3]
Parameter t6_LCLK t6_54, 2.5 t6_54, 1.675 t7_LCLK t7_54 t8 t9 t10 LCLK 1000 Cycle Jitter[13] 54MOUT 1000 Cycle Jitter[13] CLK/CLKB 1-6 Cycle CLK/CLKB Long-term Jitter[14] Jitter[15]
[16]
Description LCLK Jitter[12] 54MOUT Jitter[12]
Conditions Cycle-Cycle Jitter - 9.216 MHz Cycle-Cycle Jitter - 54 MHz, VDD = 2.5V Cycle-Cycle Jitter - 53.946 MHz, VDD = 2.5V Cycle-Cycle Jitter - 54 MHz, VDD = 1.675V Cycle-Cycle Jitter - 53.946 MHz, VDD = 1.675V 1000 Cycle Jitter - 9.216 MHz 1000 Cycle Jitter - 54 MHz, 1000 Cycle Jitter - 53.946 MHz, Cycle-Cycle Jitter, 1-6 Cycles, 400 MHz Cycle-Cycle Jitter, 1-6 Cycles, 300 MHz Long-term Jitter, 400 MHz Long-term Jitter, 300 MHz Cycle-Cycle Duty Cycle Error, 400 MHz Cycle-Cycle Duty Cycle Error, 300 MHz
Typ.
Max. 250 150 150 250 250 250 400 400 50 70 300 400 50 70
Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps
CLK/CLKB Duty Cycle Error
Notes: 8. Tested across three lots on same board, PCB boards can vary more than 5 PPM. 9. Crystal should not be heated for this test, only IC. 10. Measured on same pin of a single device. 11. Lock Time shown in Figure 2. 12. LCLK and 54MOUT Cycle-Cycle Jitter shown in Figure 3. 13. LCLK and 54MOUT 1000 Cycle Jitter shown in Figure 4. 14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in Figure 5 and Figure 6. 15. CLK/CLKB Long Term Jitter shown in Figure 7. 16. CLK/CLKB Duty Cycle Error shown in Figure 8.
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CY22313
CLK
Vx
CLKB
Figure 1. Direct Rambus Crossing Point Voltage
VDD
80%
Output
t5 Figure 2. PLL Lock Time
Output stable within PPM spec.
tcycle,i
tcycle,i+1
t6 = tcycle,i - tcycle,i+1 Figure 3. 54MOUT, LCLK Cycle-to-Cycle Jitter
1000 cycles
1000 cycles
...
t1000cycle,i
...
t1000cycle,i+1
t7 = t1000cycle,i - t1000cycle,i+1 Figure 4. 54MOUT, LCLK 1000 Cycle Jitter
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CY22313
CLK CLKB
tCYCLE,i tCYCLE,i+1
t8 = tCYLCE,i - tCYCLE,i+1 over 10000 consecutive cycles Figure 5. CLK, CLKB Cycle-to-Cycle Jitter
CLK
CLKB
t4CYCLE,i
t4CYCLE,i+1
t8 = t4CYCLE,i - t4CYCLE,i+1 over 10000 consecutive cycles
Figure 6. CLK, CLKB 4-Cycle-to-Cycle Jitter
CLK CLKB
tCYCLE t9 = tCYCLE,max - tCYCLE,min over 10000 cycles Figure 7. CLK, CLKB Long-term Jitter
CLK CLKB
Cycle i
Cycle i+1
tPW+,i tCYCLE,i t10 = tPW+,i - tPW+,i+1 Figure 8. CLK, CLKB Duty Cycle Error tCYCLE,i+1
tPW+,i+1
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CY22313
Measurement Point RT = ZCH RP RP RS CF ZCH Measurement Point RT = ZCH CMID ZCH CMID
CF RS 22313
Figure 9. Direct Rambus Test Circuit
All VDD 0.1 F OUTPUTS CLK out CLOAD
GND
Figure 10. LCLK, 54MOUT Output Test Circuits
Table 1. Direct Rambus Test Circuit Component Values Parameter RS RP CF CMID Description Series Resistor Parallel Resistor Edge-Rate Filter Capacitor[17] AC Ground Capacitor Value 68 39 15 0.01 Tolerance 5% 5% 10% 20% Unit pF F
Ordering Information
Ordering Code CY22313ZC CY22313ZCT Lead Free CY22313ZXC CY22313ZXCT Z24 24-lead TSSOP Commercial (TA = 0C to 85C) 3.45 3.45 Z24 24-lead TSSOP - Tape and Reel Commercial (TA = 0C to 85C) Notes: 17. CF is OPTIONAL filter capacitor for adjusting edge rates and EMI. No filter capacitors are used for characterization and test data. Package Name Z24 Z24 Package Type 24-lead TSSOP 24-lead TSSOP - Tape and Reel Operating Range Commercial (TA = 0C to 85C) Commercial (TA = 0C to 85C) Operating Voltages 3.45V 3.45V
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CY22313
Package Drawing and Dimensions
24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
PIN 1 ID
1
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
DIMENSION IN MM(INCHES)
24
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX. GAUGE PLANE 0.076[0.003]
0.25[0.010] BSC 0-8
0.85[0.033] 0.95[0.037]
7.70[0.303] 7.90[0.311]
0.05[0.002] 0.15[0.006]
SEATING PLANE
0.50[0.020] 0.70[0.027]
0.09[[0.003] 0.20[0.008]
51-85119-*A
Rambus is a registered trademark, and Direct Rambus is a trademark, of Rambus Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY22313
Document History Page
Document Title: CY22313 Two-PLL Clock Generator with Direct RambusTM (Lite) Support Document Number: 38-07434 REV. ** *A ECN NO. 117092 121365 Issue Date 07/02/02 11/15/02 Orig. of Change CKN CKN New Data Sheet Reordered Pin Description table Changed all 3.3V references to 3.45V Changed RI_FS min. spec to 60 KOhms Changed note 4 Inserted max. spec for Edge Rates Reduced min. spec for Edge Rates on 1.8V and 1.675V outputs Inserted phase noise specifications Created separate specs for Jitter, depending on output voltage Correctly specified CF in Table 1 Added tPU row to the Recommended Operating Conditions table Updated Switching Characteristics table Added CY22313LF ordering information and corresponding note Removed "PRELIMINARY" Rephrased Note 18 to provide clarity on marking Corrected the Lead Free Coding in the Ordering Information table Description of Change
*B *C *D *E
121773 125454 127393 239051
02/17/03 05/19/03 06/12/03 See ECN
CKN CKN RGL RGL
Document #: 38-07434 Rev. *E
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