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 STS9NH3LL
N-channel 30V - 0.018 - 9A - SO-8 Low gate charge STripFETTM III Power MOSFET
General features
Type STS9NH3LL

VDSS 30V
RDS(on) 0.022
ID 9A
Optimal RDS(on) x Qg trade-off @ 4.5V Conduction losses reduced Switching losses reduced SO-8
Description
This application specific Power MOSFET is the third generation of STMicroelectronics unique "single feature sizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STS9NH3LL Marking S9NH3LL Package SO-8 Packaging Tape & reel
July 2006
Rev 1
1/12
www.st.com 12
Contents
STS9NH3LL
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS9NH3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC=25C Drain current (pulsed) Total dissipation at TC = 25C Operating junction temperature Storage temperature Value 30 16 9 6 36 2.5 -55 to 150 Unit V V A A A W C
PTOT TJ Tstg
1. Pulse width limited by safe operating area
Table 2.
Symbol Rthj-amb(1)
Thermal data
Parameter Thermal resistance junction-ambient max Value 50 Unit C/W
1. When mounted on 1 inch FR-4 board, 2oz Cu (t<10sec.)
3/12
Electrical characteristics
STS9NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS= 0 VDS = Max rating VDS = Max rating @ 125C VGS = 16V VDS= VGS, ID = 250A VGS= 10V, ID= 4.5A VGS= 4.5V, ID= 4.5A 1 0.018 0.020 0.022 0.025 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
Table 4.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS =10V, ID = 4.5A Min. Typ. 8.5 857 147 20 7.0 2.5 2.3 10 Max. Unit S pF pF pF nC nC nC
VDS =25V, f=1MHz, VGS=0
VDD= 15V, ID = 9A VGS = 4.5V, (see Figure 14)
1. Pulsed: pulse duration=300s, duty cycle 1.5%
4/12
STS9NH3LL
Electrical characteristics
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15V, ID= 4.5A, RG= 4.7, VGS= 4.5V (see Figure 13) VDD=15V, ID= 4.5A, RG= 4.7, VGS= 4.5V (see Figure 13) Min. Typ. 12 14.5 Max. Unit ns ns
Turn-off delay time Fall time
23 8
ns ns
Table 6.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 4.5A, VGS=0 ISD= 9A, di/dt = 100A/s, VDD = 15V, Tj=150C (see Figure 18) 15 5.7 0.76 Test conditions Min. Typ. Max. 9 36 1.5 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
5/12
Electrical characteristics
STS9NH3LL
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STS9NH3LL Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized breakdown voltage vs temperature
7/12
Test circuit
STS9NH3LL
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/12
STS9NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com
9/12
Package mechanical data
STS9NH3LL
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
10/12
STS9NH3LL
Revision history
5
Revision history
Table 7.
Date 24-Jul-2006
Revision history
Revision 1 Initial release. Changes
11/12
STS9NH3LL
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