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U2789B-AFS
2000 MHz / 200 MHz Twin PLL
Description
U2789B is a low power twin PLL manufactured with TEMIC's advanced UHF process. The maximum operating frequency is 2000 MHz and 200 MHz respectively. It features a wide supply voltage range from 2.7 to 5.5 V. Prescaler and power down function for both PLL's is integrated. Applications are wireless telephones, e.g. DECT phones.
Features
D Very low current consumption (typical 3 V/12 mA) D Supply voltage range 2.7 V - 5.5 V D Maximum input frequency PLL1: 2000 MHz, D D D D D
PLL2: 200 MHz 2 pins for separate power down functions Output for PLL lock status Prescaler 32/33 for PLL1 and 8/9 for PLL2 SSO20 package ESD protected according to MIL-STD 833 method 3015 cl.2
Benefits
D Low current consumption leads to extended talk time D Twin PLL saves costs and space D One foot print for all TEMIC twin PLL's saves designin time
Block Diagram
1 VS analog VS digital DGND AGND 4 2 6 15 Control functions NC 8 15 bit latch Lock select 10 Lock Port2 Ports Power down Test 9 14 20 5I/Port 0 HPD1/Port1 HPD2/Port4 Port3
7 bit latch 1 Refi 7 7 bit reference divider 1 12 bit latch 1 RFi1 5 32/33 Prescaler 1 12 bit main divider 1 Phase detector 1 Charge pump 1 3 17 CP1 VScp
Clock Data Enable
11 3 bit 12 13 Load control
15 bit Shift register
Pump bias
19
Iset
10 bit latch 2 RFi2 16 8 / 9 Prescaler 2 10 bit main divider 2
Phase detector 2
Charge pump 2
18
CP2
96 11793
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
1 (8)
Target Specification
U2789B-AFS
Ordering Information
Extended Type Number U2789B-AFS U2789B-AFSG3 Package SSO20 SSO20 Remarks Rail, MOQ 830 pcs. Tape and reel, MOQ 4000 pcs.
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol Function 5I/Port 0 5I - Control input / o.c.output VS digital Power supply digital section CP 1 Charge pump output of synthesizer 1 VS analog Power supply analog section RFi 1 RF divider input synthesizer GNDD Ground for digital section Refi Reference oscillator input NC Not connected HPD 1/ Hardware power down input of Port 1 synthesizer 1 / o.c.output Lock/ Lock output / o.c.output / Port 2 testmode output Clock 3-wire-bus: serial clock input Data 3-wire-bus: serial data input Enable 3-wire-bus: serial enable input HPD 2/ Hardware power down input of Port 4 synthesizer 2 / o.c.output GNDA Ground for analog section RFi 2 RF divider input synthesizer 2 VScp Charge pump supply voltage CP 2 Charge pump output of synthesizer 2 Iset Reference pin for charge pump currents Port 3 o.c.output
5I/Port 0 VS digital CP 1 VS analog RFi 1 GNDD Refi NC HPD1/Port 1
1 2 3 4 5 6 7 8 9
20 Port 3 19 Iset 18 CP 2 17 VScp 16 RFi 2 15 GNDA 14 HPD2/Port 4 13 Enable 12 Data 11 Clock
96 11796
Lock/Port 2 10
Absolute Maximum Ratings
Parameters Supply voltage Pins 2, 4 and 17 Input voltage Pins 1, 3, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20 Junction temperature Storage temperature range Symbol VS, VScp Vi Tj Tstg Value 6 0 to VS 125 - 40 to + 125 Unit V V C C
Operating Range
Parameters Supply voltage Pins 2, 4 and 17 Ambient temperature range Symbol VS, VScp Tamb Value 2.7 to 5.5 - 40 to + 85 Unit V C
2 (8)
Target Specification
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
U2789B-AFS
Thermal Resistance
Junction ambient Parameters SSO20 Symbol Rthja Value 140 Unit K/W
Electrical Characteristics
Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified
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Parameters DC Supply Supply current Supply current CP Test conditions Symbol IS ICP Min. Typ. 12 1 Max. Unit mA A VS = 3 V VCP = 5 V, PLL in lock condition PLL 1 Input voltage Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter PLL 2 Input voltage p g fRFi1 = 400 - 2000 MHz VRFi1 SPSC SM SS 20 5 0 200 127 31 mVRMS 32/33 fRFi2 = 50 MHz fRFi2 = 100 - 200 MHz VRFi2 40 20 8/9 5 0 127 7 22 100 5 1.5 0 -5 -5 127 V V MHz mVRMS 200 200 mVRMS Scaling factor prescaler SPSC Scaling factor main SM counter Scaling factor swallow SS Reference input External reference input AC coupled sinewave Refi frequency External reference input AC coupled sinewave Refi amplitude Reference counter SR Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I) High input level ViH Low input level ViL High input current IiH Low input current IiL Logic output levels (Port 0, 1, 2, 3, 4, Lock) Leakage current VOH = 5.5 V IL Saturation voltage IOL = 0.5 mA VSL Charge pump output (Rset = tbd.) Source current VCP VScp/2 PLL1 Isource 5I = L PLL2 5I = H PLL2 Sink current VCP VScp/2 PLL1 Isink 5I = L PLL2 5I = H PLL2 Leakage current IL VCP VScp/2 0.4 5 5 5 0.4 -1 -0.2 -1 1 0.2 1
mA mA mA
V mA
x x x
mA pA
1)
RMS voltage at 50 W
"100
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
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Target Specification
U2789B-AFS
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire-bus (Clock, Data and Enable). After setting enable signal to low condition, the data status is transfered bit by bit on the rising edge of the clock signal into the shift register, starting with the MSB-bit. After the Enable signal returns to high condition the programmed information is loaded according to the addressbits (last three bits) into the addressed latch. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable low condition. In powerdown mode the 3-wire-bus remains active and the IC can be programmed. Data is entered with the most significant bit first. The leading bits deliver the divider or control information. The trailing three bits are the address field. There are five different addresses used. The trailing address bits are decoded upon the rising edge of the Enable signal.
Bit Allocation
MSB
Bit 1 D14 Bit 2 D13 Bit 3 D12 Bit 4 D11
PLL1 M6
LSB
Bit 5 D10 M5 Bit 6 D9 M4 Bit 7 D8 M3 Bit Bit 8 9 data bits D7 M2 D6 M1
PLL1/2 R6 PLL2 M6
Bit 10 D5 M0 R5 M2 LPA
Bit 11 D4 S4 R4 M1 P4
Bit 12 D3 S3 R3 M0 P3
Bit 13 D2 S2 R2 S2 P2
Bit 14 D1 S1 R1 S1 P1 SPD 2
Bit 15 D0
PLL1 S0 PLL1/2 R0 PLL2 S0
Bit Bit Bit 16 17 18 address bits A2 0 0 0 1 A1 0 1 1 0 A0 1 0 1 1
Test
5IP
TRI 2
TRI 1
PS2
PS1
M5 H2P
M4 H1P
M3 LPB
P0 SPD 1
5I
1
1
0
Scaling Factors
PGD of PLL1:
S0 ... S4: These bits are setting the swallow counter SS. SS = S0*20 + S1*21 + ... + S3*23 + S4*24 allowed scalling factors for SS: 0 ... 31, SS < SM These bits are setting the main counter SM. SM = M0*20 + M1*21 + ... + M5*25 + M6*26 allowed scalling factors for SM: 5 ... 127 Total scalling factor of the programmable counter: Condition: SS < SM SPGD = (32*SM) + SS
PGD of PLL2:
S0 ... S2: These bits are setting the swallow counter SS. SS = S0*20 + S1*21 + S2*22 allowed scalling factors for SS: 0 ... 7, SS < SM These bits are setting the main counter SM. SM = M0*20 + M1*21 + ... + M5*25 + M6*26 allowed scalling factors for SM: 5 ... 127 Total scalling factor of the programmable counter: Condition: SS < SM SPGD = (8*SM) + SS
M0 ... M6:
M0 ... M6:
SPGD:
SPGD:
RFD of PLL1 and PLL2:
R0 ... R6: These bits are setting the reference counter SR. SRFD = R0*20 + ... + R5*25 + R6*26 allowed scalling factors for SR: 5 ... 127
4 (8)
Target Specification
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
U2789B-AFS
Serial Programming Bus
Control bits:
P0 ... P4: LPA, LPB: o.c. output ports (1 = high impedance) selection of P2 output or locksignal LPA LPB function of pin 10 0 0 o.c. output P2 0 1 locksignal of synthesizer 2 1 0 locksignal of synthesizer 1 1 1 wiredor locksignal of both synthesizer selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD)
H1P, H2P: 5IP:
selection of P0 output or high current switching input for the charge pump current of synthesizer 2 (0 = Port / 1 = charge pump 2 current switch input) phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers) PS-PLL1/2 = 1 CP1/2 Isink Isource 0 PS-PLL1/2 = 0 CP1/2 Isource Isink 0
PS1, PS2:
fR > fP fR < fP fR = fP
SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup) 5I: software switch for the charge pump current of synthesizer 2 (0 = low current / 1 = high current)
TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate) TEST: enables counter testmode (0 = disabled / 1 = enabled) TEST 1 1 1 1 LPA 1 1 0 0 LPB 0 0 1 1 PS1 1 0 x x PS2 x x 1 0 Testsignal at pin 10 RFD1 PGD1 RFD2 PGD2
Power down: When the power down mode (hardware or software) is activated, the ICs charge pump outputs are set into tristate condition before the device is powered down. To operate the software power down mode the following condition must be set: HXP = 0; power up and power down will be set by SPDX = 1 (on) and SPDX = 0 (off). To operate the hardware power down mode the following condition must be set: HXP = 1; SPDX = 1; power up and power down will be set by high and low state at the hardware power down pins 9/14. High current of charge pump synthesizer 2 is active when 5I = 1 and if 5IP = 1 the charge pump current control input pin 1 is in high state.
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
5 (8)
Target Specification
Application Circuit
U2789B-AFS
6 (8)
5I / P0 47u 12 C2 R1 C1 C2 51 10n 18 18 10n 51 HPD2 / PORT4 HPD1 / PORT1 ENABLE 10n DATA CLOCK LOCK / PORT2 / TEST
94 9621
VS VCO
10n R C1
P3
R1
VS
12
47u
10n
12 12
VCO1 10n 10n 18 18 18
47u
10n
VCO2 10n 10n
VScp
47u
18 RF2 10n
Target Specification
RF1
CRYSTAL OSC. INPUT
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96
51
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Dimensions in mm
Clock High Time Clock Low Time Clock Period Set Up Time Data to Clock Hold Time Data to Clock Hold Time Clock to Enable Enable High Time Set Up Time Enable to Clock Enable Clock tSEC tCH tCL tCH tCL tPER tSDC tHDC tHCE tEL tSEC tSDC tHDC tHCE tEH > 400 > 400 > 800 > 100 > 400 > 400 > 200 > 4000 ns ns ns ns ns ns ns ns
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TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96 Package: SSO20 Data
Timing Diagram Serial Bus
Target Specification
U2789B-AFS
7 (8)
U2789B-AFS
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
8 (8)
Target Specification
TELEFUNKEN Semiconductors Rev. A1, 22-Jul-96

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