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MMDF3N04HD
Preferred Device
Power MOSFET 3 Amps, 40 Volts
N-Channel SO-8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSTM devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided * Avalanche Energy Specified
N-Channel D
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V(BR)DSS 40 V
RDS(on) TYP 80 mW @ TBD
ID MAX 3.0 A
MARKING DIAGRAM
SO-8, Dual CASE 751 Style 11 1
8
D3N04H ALYW
D3N04H = Specific Device Code A = Assembly Location L =Wafer Lot Y = Year W = Work Week
PIN ASSIGNMENT
Source-1 G S Gate-1 Source-2 Gate-2 1 2 3 4 8 7 6 5 Drain-1 Drain-1 Drain-2 Drain-2
Top View
ORDERING INFORMATION
Device MMDF3N04HDR2 Package SO-8 Shipping 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 3
Publication Order Number: MMDF3N04HD/D
MMDF3N04HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C (Note 1) Drain Current- Continuous @ TA = 70C (Note 1) Drain Current- Pulsed Drain Current (Note 3) Total Power Dissipation @ TA = 25C (Note 1) Linear Derating Factor (1) Total Power Dissipation @ TA = 25C (Note 2) Linear Derating Factor (2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting T J = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 4.0 mH, VDS = 40 Vdc) Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg EAS 162 Value 40 40 20 3.4 3.0 40 2.0 16 1.39 11.11 - 55 to 150 Unit Vdc Vdc Vdc Adc Apk Watts mW/C Watts mW/C C mJ
THERMAL RESISTANCE
Rating Thermal Resistance - Junction to Ambient, PCB Mount (Note 1) - Junction to Ambient, PCB Mount (Note 2) Symbol RqJA RqJA Typ. - - Max. 62.5 90 Unit C/W
1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on minimum recommended FR-4 or G-10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature.
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.4 Adc) (VGS = 4.5 Vdc, ID = 1.7 Adc) (Cpk 2.0) (Notes 4 & 6) VGS(th) 1.0 - (Notes 4 & 6) RDS(on) - - (Note 4) gFS 2.0 55 79 4.5 80 100 - Mhos 2.0 4.9 3.0 - Vdc mV/C mW (Cpk 2.0) (Notes 4 & 6) V(BR)DSS 40 - IDSS - - IGSS - 0.015 0.15 0.013 2.5 10 500 nAdc - 4.3 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge
Ciss (VDS = 32 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Coss Crss
- - -
450 130 32
900 230 96
pF
td(on) (VDD = 20 Vdc, ID = 3.4 Adc, VGS = 10 Vdc, RG = 6 W) (Note 4) tr td(off) tf td(on) (VDD = 20 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc, RG = 6 W) (Note 4) tr td(off) tf QT (VDS = 40 Vdc, ID = 3.4 Adc, VGS = 10 Vdc) (Note 4) Q1 Q2 Q3
- - - - - - - - - - - -
9.0 15 28 19 13 77 17 20 13.9 2.1 3.7 5.4
18 30 56 38 26 144 34 40 28 - - -
ns
ns
nC
SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 3.4 Adc, VGS = 0 Vdc) (Note 4) (IS = 3.4 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.4 Adc, VGS = 0 Vdc, 3 4 Ad Vd dIS/dt = 100 A/ms) (Note 4) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. Max limit - Typ 6. Reflects typical values. Cpk = 3 x SIGMA VSD - - trr ta tb QRR - - - - 0.87 0.8 27 20 7.0 0.03 1.5 - - - - - mC ns Vdc
Reverse Recovery Time
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MMDF3N04HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 2.7 V 6 TJ = 25C 3.7 V I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 1.5 VDS 10 V TJ = 25C
VGS = 10 V
3.9 V 4.5 V 4.3 V 4.1 V
3.5 V
100C 25C TJ = -55C
3.3 V 3.1 V 2.9 V 1.4 1.6 1.8 2
0
0.2
0.4
0.6
0.8
1
1.2
2
2.5
3
3.5
4
4.5
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 ID = 3.4 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.1 0.095 0.09 0.085 0.08 0.075 0.07 0.065 0.06 0.055 0.05 0 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS) 10 V VGS = 4.5 TJ = 25C
Figure 3. On-Resistance versus Gate-to-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On-Resistance versus Drain Current and Gate Voltage
2.0 VGS = 10 V ID = 3.4 A I DSS , LEAKAGE (nA) 1.5
100 VGS = 0 V TJ = 125C 10 100C
1.0
1
25C
0.5
0 -50
-25
0
25
50
75
100
125
150
0.1 0 5 10 15 20 25 30 35 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (C)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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MMDF3N04HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 VDS = 0 V Ciss 900 C, CAPACITANCE (pF) VGS = 0 V
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
600
Crss
Ciss
300 Coss Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MMDF3N04HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 20 V ID = 3.4 A VGS = 10 V TJ = 25C
9 VDS
30
100 t, TIME (ns)
6
VGS
20
10
3
Q1 Q3
Q2
ID = 3.4 A TJ = 25C
td(off) tf tr td(on)
10
0
0
4
8 Qg, TOTAL GATE CHARGE (nC)
12
0 16
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
3.5 3.0 IS, SOURCE CURRENT (AMPS) 2.5 2.0 1.5 1.0 0.5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 0.9 TJ = 25C VGS = 0 V
high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
Figure 10. Diode Forward Voltage versus Current
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MMDF3N04HD
di/dt = 300 A/ms I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) 1 ms 10 ms 1 dc EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) VGS = 20 V SINGLE PULSE TC = 25C
reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
160 ID = 9 A 120
10
80
0.1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100
40
0.01 0.1
0
25
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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MMDF3N04HD
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.1 0.2 0.1 0.05 0.02 0.01 0.01 Chip Junction
0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W
0.0253 F
0.1406 F
0.5064 F
2.9468 F
177.14 F
0.001 1.0E-05
SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02
Ambient 1.0E+03
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
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MMDF3N04HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process.
0.060 1.52
0.275 7.0
0.155 4.0
0.024 0.6
0.050 1.270
inches mm
SO-8 POWER DISSIPATION The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RqJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows:
PD = TJ(max) - TA RqJA
into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C - 25C = 2.0 Watts 62.5C/W
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values
The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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MMDF3N04HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 -189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
STEP 4 HEATING ZONES 3 & 6 "SOAK"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
160C
STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MMDF3N04HD
PACKAGE DIMENSIONS
SO-8 CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8.
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MMDF3N04HD
MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC). Company. Thermal Clad is a registered trademark of the Bergquist
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MMDF3N04HD/D

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