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Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET FEATURES * 'Trench' technology * Low on-state resistance * Fast switching * High thermal cycling performance * Low-profile surface mount package * Logic level compatible PHN1011 SYMBOL d QUICK REFERENCE DATA VDSS = 25 V ID = 11 A g RDS(ON) 11 m (VGS = 10 V) RDS(ON) 13.5 m (VGS = 5 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a surface mounting plastic package using 'trench' technology. The combination of very low on-state resistance and low switching losses make this device the optimum choice in high speed computer motherboard d.c. to d.c. converters. The PHN1011 is supplied in the SOT96-1 (SO8) surface mounting package PINNING PIN 1-3 4 5-8 DESCRIPTION SOT96-1 (SO8) 8 7 6 5 source gate drain pin 1 index 1 2 3 4 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (tp 10 s) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Ta = 25 C Ta = 70 C Ta = 25 C Ta = 25 C Ta = 70 C MIN. - 55 MAX. 25 25 15 20 11 9 44 2.5 1.6 150 UNIT V V V V A A A W W C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted, FR4 board, t 10 sec Surface mounted, FR4 board TYP. 150 MAX. 50 UNIT K/W K/W June 1999 1 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 10 A VGS = 5 V; ID = 5 A VGS = 5 V; ID = 5 A; Tj = 150C Forward transconductance VDS = 25 V; ID = 10 A Gate source leakage current VGS = 5 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 150C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 25 A; VDD = 15 V; VGS = 5 V MIN. 25 22 1 0.6 12 - PHN1011 TYP. MAX. UNIT 1.5 9 11 36 10 0.05 26 6 9.4 7 50 82 59 1 3 1700 475 300 2 2.3 11 13.5 23 100 10 500 15 75 120 75 V V V V V m m m S nA A A nC nC nC ns ns ns ns nH nH pF pF pF VDD = 15 V; ID = 25 A; VGS = 10 V; RG = 5 Resistive load Drain leads to centre of die Source leads to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 C, tp 10 s MIN. IF = 10 A; VGS = 0 V IF = 10 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V TYP. MAX. UNIT 0.95 83 0.1 11 44 1.2 A A V ns C June 1999 2 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHN1011 Normalised Power Derating, Ptot (%) 100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 Ambient temperature, Ta (C) 100 Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2 10 0.1 0.05 0.02 1 P D 0.1 single pulse D = tp/T tp T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta) Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Drain Current, ID (A) VGS = 10 V 45 4.5 V 3V 40 35 5V Tj = 25 C Normalised Current Derating, ID (%) 50 120 100 80 30 2.8 V 60 40 25 2.6 V 20 15 2.4 V 2.2 V 5 20 0 0 20 40 60 80 100 120 140 160 10 2V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 0 Ambient temperature, Ta (C) Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); conditions: VGS 5 V Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID tp = 10 us 100 us 10 1 ms 10 ms 100 ms D.C. Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS 100 Drain-Source On Resistance, RDS(on) (Ohms) 0.1 2.2 V 0.09 0.08 0.07 0.06 2.8V 2.4 V 2.6 V Tj = 25 C 1 0.05 0.04 3V 0.1 0.03 0.02 0.01 10V 5V VGS =4.5 V 0.01 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 Fig.3. Safe operating area. Ta = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS June 1999 3 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHN1011 Drain current, ID (A) 50 45 40 35 30 25 VDS > ID X RDS(ON) Threshold Voltage, VGS(TO) (V) 2.25 2 1.75 1.5 typical 1.25 1 minimum maximum 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Gate-source voltage, VGS (V) 150 C Tj = 25 C 0.75 0.5 0.25 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj Transconductance, gfs (S) VDS > ID X RDS(ON) 45 40 35 150 C 30 25 20 15 10 5 0 0 5 10 15 20 25 Drain current, ID (A) 30 35 40 Tj = 25 C Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Drain current, ID (A) VDS = 5 V 1.0E-02 50 1.0E-01 1.0E-03 minimum 1.0E-04 typical maximum 1.0E-05 1.0E-06 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V Normalised On-state Resistance Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss 1000 Coss Crss 100 -60 -40 -20 0 20 40 60 80 100 Junction temperature, Tj (C) 120 140 160 180 0.1 1 10 Drain-Source Voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz June 1999 4 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET PHN1011 Source-Drain Diode Current, IF (A) Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 25A Tj = 25 C VDD = 15 V 50 VGS = 0 V 45 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 Gate charge, QG (nC) 35 40 45 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) Tj = 25 C 150 C Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj June 1999 5 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET MECHANICAL DATA SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PHN1011 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 Fig.15. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". June 1999 6 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHN1011 This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1999 7 Rev 1.100 |
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