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| CYT9174 Description The CYT9174 regulator is designed to convert voltage supplies ranging from 1.6V to 6V into a desired output voltage, which is adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to 2.0A of current while regulating an output voltage to within 2% (DDR 1 or DDR 2) or less. The CYT9174, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed back-plane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus on-chip thermal shutdown make the circuit tolerant of the output fault conditions. Features Support Both DDR 1 (1.25VTT) and DDR 2 (0.9VTT) Requirements SOP-8 Packages Capable of Sourcing and Sinking Current 2.0A Current-limiting Protection Thermal Protection Current-shoot-through protection Integrated Power MOSFETs Generates Termination Voltages for SSTL-2 High Accuracy Output Voltage at Full-Load Adjustable Vout by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output Application DDR Memory Termination Active Termination Buses Supply Splitter Pin Configuration Pin Description Pin Name VIN Pin function Power Input Ground Gate Drive Voltage Reference Voltage input and Chip Enable VOUT Output Voltage U Block Diagram GND VCNTL REFEN VCNTL Current Limiting Sensor VIN REFEN Thermal CNTL VOUT GND All contents are subject to change without prior notice 1 CYT9174 Absolute Maximum Rating (1) Parameter Input Voltage Power Dissipation ESD Rating Storage Temperature Range Lead Temperature (Soldering, 5 sec.) Package Thermal Resistance Symbol VIN PD -TS TLEAD JC Value 6 Internally Limited 3 -65 to 150 Unit V -KV C 260 C 15.7 C/W Electrical Characteristics VIN=2.5V, VCNTL=3.3V, VREFEN=1.25V, COUT=10F (Ceramic)), TA=25C, unless otherwise specified Parameter Output Offset Voltage (2) Load Regulation (DDR 1/2) Input Voltage Range (DDR 1/2) Current In Shutdown Mode Symbol VOS |VLOAD| VIN VCNTL ISHDN Test Conditions IOUT = 0A IL : 0A2.0A IL : 0A-2.0A Keep VCNTLVIN on operation power on and power off sequences VREFEN 0.2V, RL = 180 Short Circuit Protection Min -20 --1.6 -- Typ -5 0.5 0.5 2.5/1.8 3.3 Max 20 2 2 -6 Units mV % V -- 1 90 A Current limit Quiescent Current ILIMIT IQ IL=2.0A Over Temperature Protection --- 2.5 1.4 -3 A mA Thermal Shutdown Temperature Thermal Shutdown Hysterresis TCASE 3.3V VCNTL 5 V Guaranteed by design Shutdown Function -- 100 -C -- 30 -- Shutdown Threshold Trigger Output=High Output=Low 0.8 -- --- -0.2 V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN All contents are subject to change without prior notice 2 CYT9174 Application Information Internal parasitic diode Avoid forward-bias internal parasitic diode, VOUT to VCNTL, and VOUT to VIN, the VOUT should not be forced same voltage respect to ground on this pin while the VCNTL or VIN is disappeared. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition to item1, the capacitor and voltage divider form the low-pass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. Thermal Consideration CYT9174 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continuous normal load conditions however, the maximum junction temperature rating of 150C must not be exceeded. Higher continuous currents or ambient temperature require additional heatsinking. Heat sinking to the IC package must consider the worst case power dissipation which may occur. It should also be noted that with the VCNTL equal to 5V, the point of thermal shutdown will be degraded by approx. 20C compared to the VCNTL equipped with 3.3V. It is highly recommended that to use the 3.3V rail acting as the VCNTL so as to minimize the thermal concern of the CYT9174 in the SOP-8 package. RN RN1 REFEN Layout Consideration The CYT9174 regulator is packaged in thermally enhanced plastic SOP-8 package. This small footprint package is unable to convectively dissipate the heat generated when the regulator is operating at high current levels. In order to control die operating temperatures, the PC board layout should allow for maximum possible copper area at the VCNTL pins of the CYT9174. The multiple VCNTL pins on the SOP-8 package are internally connected, but lowest thermal resistance will result if these pins are tightly connected on the PC board. This will also aid heat dissipation at high power levels. If the large copper around the IC is unavailable, a buried layer may be used as a heat spreader, Use via to conduct the heat into the buried or backside of PCB layer. The via should be small enough to retain solder when the board is wave-soldered. Terminator Resis R0 BUS(0) BUS(1) BUS(2) BUS(3) BUS(4) BUS(5) BUS(6) BUS(7) BUS(8) BUS(9) CYT9174 VOUT R1 R2 R3 R4 R5 CYT9174 VOUT R6 R7 R8 R9 BUS(N+1) BUS(N) All contents are subject to change without prior notice 3 CYT9174 Application Diagram R1 = R2 = 100K, RTT = 50/33/25 COUT, min = 10F(Ceramic) + 1000F under the worst case testing condition RDUMMY = 1K as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F All contents are subject to change without prior notice 4 CYT9174 Outline Drawing SOP-8 DIMENSIONS INCHES MM MIN MAX MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.050 BSC 0.0075 0.0098 0.1890 0.1968 0.2284 0.2440 0.1497 0.1574 1.35 1.75 0.10 0.25 0.33 0.51 1.27 BSC 0.19 0.25 4.80 5.00 5.80 6.20 3.80 4.00 1 2 D 8 7 6 B1 B DIMN A A1 B B1 C D H E 3 4 5 A1 E H A C All contents are subject to change without prior notice 5 |
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