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Semiconductor
August 1997
NOT
N FOR DED 1178 N MME ee HI S ECO R
EW
IG DES
NS
HI1260
Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter
Features
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit * Maximum Conversion Speed . . . . . . . . . . . . . . . 35MHz * RGB 3-Channel Input/Output * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Digital Input Voltage . . . . . . . . . . . . . . . . . . . .TTL Level * Output Voltage Full Scale (Typ) . . . . . . . . . . . . . . 1VP-P * Low Power Consumption (Typ) . . . . . . . . . . . . .360mW * Direct Replacement for Sony CXA1260
Description
The HI1260 is a triple 8-bit, high-speed, bipolar D/A converter designed for video band use. It has three separate, 8-bit pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. For lower CMOS power consumption, refer to the HI1178.
Ordering Information
PART NUMBER HI1260JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.12 x 12-S
Applications
* Digital TV * Graphics Display * High Resolution Color Graphics * Video Reconstruction * Instrumentation * Image Processing * I/Q Modulation
Pinout
HI1260 (MQFP) TOP VIEW
DGND NC DGND R1 NC
R4 R3
R8
R7
G1 G2 G3 G4 G5 G6 G7 G8 B1 B2 B3 B4
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
R6 R5
R2
NC NC NC ROUT NC GOUT NC BOUT NC AVCC NC VREF
DGND DVCC
B7 B8
CLK
NC NC
NC
B5
B6
AGND
VSET
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
4112.1
10-1
HI1260 Functional Block Diagram
DGND 37 33 ROUT R1 39 R2 40 R3 41 R4 42 R5 44 R6 45 R7 46 R8 47 G1 1 G2 2 G3 3 G4 4 G5 5 G6 6 G7 7 G8 8 B1 9 B2 10 2 B3 11 B4 12 B5 13 B6 14 6 B7 15 R B8 16 INPUT BUFFER (B) 6 R 2R 2R R CLOCK BUFFER 27 AVCC DECODER 3 3 CURRENT SWITCH (B) R R 2R 2R R R R 2R INPUT BUFFER (G) 6 DECODER 2 3 CLOCK SYNCHRONIZING CIRCUIT R 2R 2R 2R 2R 2R R 29 BOUT INPUT BUFFER (R) 6 6 R R 2R 2R R R 3 R CURRENT SWITCH (G) 6 R R R R 31 GOUT CURRENT SWITCH (R) DECODER 2 3 3 R R R R R 2R 2R 2R
-+
INTERNAL REFERENCE VOLTAGE SOURCE 25 VREF
18 CLOCK
20 DVCC
23 AGND
24 VSET
10-2
HI1260 Pin Descriptions
NUMBER 1 to 16 39 to 42 44 to 47 SYMBOL R1 to R8 G1 to G8 B1 to B8 EQUIVALENT CIRCUIT
DVCC 20
DESCRIPTION Digital Input pin. From pins 39 to 42 and from 44 to 47 are for RED. R1 is MSB and R8 is LSB. From pins 1 to 8 are for GREEN. G1 is MSB and G8 is LSB. From pins 9 to 16 are for BLUE. B1 is MSB and B8 is LSB.
39 - 42 44 - 47 1 - 16 37 DGND
18
CLK
DVCC 20
Clock Input pin.
18
37 DGND
20 17 21 to 22 23 24
DVCC NC
Digital VCC . Vacant pin (no connection).
AGND VSET
AVCC 27 54K
Analog GND. Bias Input pin. Normally, apply 0.87V. See "Note on use."
24
23
25
VREF
AVCC 27
Internal Reference Voltage Out pin, 1.2V (Typ). A pull-down resistor is necessary externally. See "Notes on use."
25 20p 23 AGND
10-3
HI1260 Pin Descriptions
NUMBER 26 27 28 SYMBOL NC AVCC NC (Continued) EQUIVALENT CIRCUIT DESCRIPTION Vacant pin (no connection). Analog VCC . Vacant pin but connect to AVCC (Note 1).
AVCC 27 RO 29
29
BOUT
Analog Output pin for BLUE.
23 AGND
30
NC
Vacant pin but connect to AVCC (Note 1).
AVCC 27 RO 31
31
GOUT
Analog Output pin for GREEN.
23 AGND
32
NC
Vacant pin but connect to AVCC (Note 1).
AVCC 27 RO 33
33
ROUT
Analog Output pin for RED.
23 AGND
34 To 36
NC
Vacant pin but connect to AVCC (Note 1). Digital GND. Vacant pin (no connection).
19, 37, 43 48 NOTE:
DGND NC
1. Pins 30, 32, 34 and 36 are vacant, but in order to reduce interference between the individual RGB outputs, connect them to AVCC .
10-4
HI1260
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 7V Input Voltage (Digital) VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC VCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Input Voltage (VSET Pin), VSET . . . . . . . . . . . . . . . . . . -0.3V to VCC Output Voltage (Analog), VOUT . . . . . . . . . . . . . . VCC -2.1V to VCC Output Current (Analog), IOUT . . . . . . . . . . . . . . . . . . -3mA to 10mA (VREF Pin), IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Allowable Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVCC , DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V AVCC - DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 0.2V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.0.5V Digital Input Voltage H Level, VIH , VCLKH . . . . . . . . . . . . . . . . . . . . . . . . .2.0V to DVCC L Level, VIL , VCLKL . . . . . . . . . . . . . . . . . . . . . . . . . DGND to 0.8V VSET Input Voltage, VSET . . . . . . . . . . . . . . . . . . . . . . . 0.7V to 1.0V VREF Pin Current, IREF . . . . . . . . . . . . . . . . . . . . . . . -3mA to 0.4mA Clock Pule Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Monotony Differential Linearity Error Integral Linearity Error Maximum Conversion Speed Full Scale Output Voltage
TA = 25oC, AVCC = DVCC = 5.0V, AGND = DGND = 0.0V SYMBOL RSL MNT DLE ILE fMAX VOFS FSR VOFFSET RO ID VSET - AGND = 0.87V RL > 10k IREF = -400A VI = DVCC VI = DGND VCLK = DVCC VCLK = DGND VSET = AGND = 0.87V IREF = -400A VSET - AGND = 0.87V RL > 10k FS = Full Scale VSET - AGND = 0.87V RL > 10k CL < 20pF TEST CONDITIONS NOTES MIN -0.5 -0.4 35 Note 3 Note 4 0.85 0 -40 270 54 TYP 8 Guarantee 1.0 4 -6 340 72 MAX 0.5 4 1.15 8 0 420 90 UNITS Bit LSB % of FS MSPS VP-P % mV mA
RGB Output Voltage Full Scale Ratio Output Zero Offset Voltage Output Resistance Consumption Current
Digital Data Input Current
H Level L Level
Upper 2 Bits Lower 6 Bits Upper 2 Bits Lower 6 Bits H Level L Level
IIH(U) IIH(L) IIL(U) IIL(L) ICLKH ICLKL ISET VREF tS tH
-10 -10 -10 -5 1.08 12 3
1.2 0.6 0 0 3 0 -0.3 1.20 -
20 10 10 10 30 10 0 1.32 -
A A A A A A A V ns ns
Clock Input Current
VSET Input Current Internal Reference Voltage Set-Up Time Hold Time
NOTES: 3. AVCC - V0 . VO FS ( G ) VO FS ( B ) VO FS ( R ) 4. Maximum value among 100 x ----------------------- - 1 ,100 x ----------------------- - 1 , or 100 x ----------------------- - 1 . VO FS ( G ) VO FS ( B ) VO FS ( R )
10-5
HI1260
TABLE 1. INPUT CORRESPONDING TABLE INPUT CODE MSB 1 1 1 1 * * * 1 0 0 0 * * * 0 0 0 0 0 0 0 0 0 0 1 1 1 LSB 1 VCC + VOFFSET * * * 0 VCC + VOFFSET -0.5V * * * 0 VCC + VOFFSET -1.0V OUTPUT VOLTAGE
Standard Circuit Design Data
PARAMETER Crosstalk Among R, G and B
TA = 25oC, AVCC = DVCC = 5.0V, AGND = DGND = 0.0V TEST CONDITIONS D/A OUT: 1VP-P RL > 10k CL < 20pF fDATA = 7MHz fCLK = 14MHz See Figure 5 VSET - AGND = 0.87V RL > 10k fCLK = 1MHz Digital Ramp Output See Figure 6 VSET -AGND = 0.87V See Figure 4 Note 5 NOTES MIN TYP -40 MAX -35 UNITS dB
SYMBOL CT
Glitch Energy
GE
-
30
-
pV/s
Rise Time Fall Time Settling Time NOTE:
tr tf tSET
Note 6 Note 6
-
5.5 5.0 1.6
-
ns ns ns
5. Observe the glitch which is generated when the digital input varies as follows: 0 0 1 1 1 1 1 1 - 0 1 0 0 0 0 0 1 1 1 1 1 1 1 - 1 0 0 0 0 0 1 0 1 1 1 1 1 1 - 1 1 0 0 0 0 6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.
0 0 0
0 0 0
Test Circuits and Waveforms
19, 37, 43 DVCC D1 D2 D1 - D8 8 (R) D1 - D8 8 (G) D1 - D8 8 (B) DGND 39 - 42 44 - 47 1-8 9 - 16 33 31 29 27 25 24 23 CLK TTL LEVEL CLK HI1260 18 20 ROUT GOUT BOUT AVCC VREF VSET + 3K V V
D8
-
33F
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUIT
10-6
HI1260 Test Circuits and Waveforms
(MSB) OUT D1 D2 8-BIT COUNTER (TTL OUTPUT)
(Continued)
D1 - D8 8 (R) D1 - D8
39 - 42 44 - 47 1-8 33 31 9 - 16 29 27 24 23 18 20 HI1260
19, 37, 43 DIGITAL RAMP WAVEFORM GENERATION ROUT GOUT BOUT OSCILLOSCOPE RIN = 1M CIN - 10PF BW = 20MHz
(LSB) D8
8 (G) D1 - D8 8 (B)
IN
VSET +
12.5K V
-
33F CLK MCLK f = 35 MSPS TTL LEVEL RECTANGULAR WAVE CLK AGND DGND
2ns TO 10ns D1 TO D8 AVCC DVCC
TIMING BETWEEN CLK AND DATA
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
D1 - D8 DVCC 8 (R) 8 (G) 8
39 - 42 44 - 47 1-8 33 31 9- 16 29 27 25 24 23
19, 37, 43
ROUT GOUT BOUT AVCC VREF VSET 33F V 3K V
(B)
CLK TTL LEVEL CLK
18 20 HI1260
FIGURE 3. OUTPUT VOLTAGE FULL SCALE PRECISION, RGB OUTPUT VOLTAGE FULL SCALE RATIO, AND OUTPUT ZERO OFFSET VOLTAGE TEST CIRCUITS
10-7
HI1260 Test Circuits and Waveforms
OBSERVE DATA WAVEFORM WITH AN OSCILLOSCOPE RIN = 1M BW = 200MHz D1 - D8 8 8 CO-AXIAL CABLE (1m) 8 50 47 (R) 1-8 (G) 9 - 16 (B) 31 330 51 COAXIAL CABLE 50 BOUT 29 330 27 VSET + 51 COAXIAL CABLE 50 33 330 51 COAXIAL CABLE 50 GOUT
(Continued)
HI1260 39 - 42 44 - 47 19, 37, 43 (1m) COAXIAL CABLE ROUT OBSERVE CLK WAVEFORM WITH AN OSCILLOSCOPE RIN = 1M BW = 200MHz
(
)
(
)
24 23 (TTL) 18
1/ 2
12.5K
-
33F 20
DIVIDER
1.2K COAXIAL CABLE (1m) OBSERVE CLK WAVEFORM WITH AN OSCILLOSCOPE RIN = 1M BW = 200MHz
f = 35MHz TTL LEVEL PULSE GENERATOR 8082A (YHP)
47
50
(
)
AGND f = 35 MSPS TTL LEVEL RECTANGULAR WAVE
DGND
AVCC
DVCC
D DELAY ADJUSTMENT
PULSE GENERATOR 8082A (YHP)
FIGURE 4. SETUP TIME, HOLD TIME, AND RISE AND FALL TIME TEST CIRCUITS
D1 - D8 f = 7MHz TTL LEVEL RECTANGULAR WAVE 8 (R) 8 (G) 8
1/
39 - 42 44 - 47 1-8 33 31 9 - 16 29
19, 37, 43 50 EXIT ROUT GOUT BOUT P6202 (TEKTRONIX) 27 24 23 AVCC VSET + FET PROVE SPECTRUM ANALYZER
(B)
28, 30, 32 34 - 36
2
DIVIDER
-
12.5K 33F
CLK MCLK f = 14 MSPS TTL LEVEL RECTANGULAR WAVE
18 20 HI1260
NOTES: The following notes cover the measurement methods in case the measuring crosstalk of G R: 7. Apply the data to G only and measure the power of the frequency component of the data at ROUT . 8. Apply the data to R only and measure the power of the frequency component of the data at ROUT . 9. Take the difference of the above two powers. The unit is in dB. FIGURE 5. CROSSTALK AMONG R, G AND B TEST CIRCUIT
10-8
HI1260 Test Circuits and Waveforms
(MSB) OUT D1 D2 8-BIT COUNTER (TTL OUTPUT)
(Continued)
D1 -D8 8 (R) D1 -D8
39 - 42 44 - 47 1-8 33 31 9 - 16 29 27 25 24 23 18 20 HI1260
19, 37, 43 DIGITAL RAMP WAVEFORM GENERATION ROUT GOUT BOUT
(LSB) D8
8 (G) D1 -D8 8 (B) 100PF
IN
VREF VSET + 3K V 33F
-
MCLK f = 1 MSPS TTL LEVEL RECTANGULAR WAVE
CLK
CLK
AGND
DGND
5ns TO 300ns D1 TO D8 AVCC DVCC
TIMING OF CLK AND DATA
FIGURE 6. GLITCH ENERGY TEST CIRCUIT
Timing Diagram
t1 t12 t2 t3 t34 t4 tPW1 tPW0 CLK tX DATA tH tH 100% 90% tY
VTH = 1.5V
VTH = 1.4V tS tS 0% 10% VTH: THRESHOLD LEVEL
D/A OUT 10% 0% 90% 100%
tr
tf
At the time t = tx , the data of individual bits are switched and thereafter, when the CLK becomes L H at t = t2 , the D/A OUT is varied synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. (In this case, fetching of the data is carried out at the fall of the CLK (at the time when t = T12).)
At the time t = TY , the data of individual bits are switched and thereafter, when the CLK becomes L H at t = t4 , the D/A OUT is synchronous with it. That is, the D/A OUT is synchronous with the rise of the CLK. (In this case, fetching of the data is carried out at the fall of CLK (at the time when t = t4 ).)
FIGURE 7.
10-9
HI1260 Typical Performance Curves
OUTPUT VOLTAGE FULL SCALE (VP-P) OUTPUT ZERO OFFSET VOLTAGE (mV) TA = 25oC AVCC = DVCC = 5.0V RL > 10k 0
2.0
DEVIATION RANGE 1.0
B -10 G
0
1.0 VSET - AGND (V)
2.0
-20 0
TA = 25oC AVCC = DVCC = 5.0V RL > 10k 1.0 VSET - AGND (V)
R
2.0
FIGURE 8. OUTPUT VOLTAGE FULL SCALE vs VSET - AGND
FIGURE 9. OUTPUT ZERO OFFSET VOLTAGE vs VSET - AGND
OUTPUT VOLTAGE FULL SCALE (mVP-P)
0 OUTPUT ZERO OFFSET VOLTAGE (mV) VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF/3) IREF = -400A AVCC = DVCC = 5.0V RL > 10k -5
1000
950
VSET IS CREATED BY RESISTANCE DIVISION OF VREF (VSET = 2VREF/3) IREF = -400A AVCC = DVCC = 5.0V RL > 10k 0 20 40 60 80
-20
-10
-20
0
20
40
60
80
AMBIENT TEMPERATURE (oC)
AMBIENT TEMPERATURE (oC)
FIGURE 10. OUTPUT VOLTAGE FULL SCALE vs AMBIENT TEMPERATURE
FIGURE 11. OUTPUT ZERO OFFSET VOLTAGE vs AMBIENT TEMPERATURE
0 OUTPUT VOLTAGE FULL SCALE (VP-P) OUTPUT OFFSET VOLTAGE (mV)
1000
-5
950 TA = 25oC VSET - AGND = 0.8V RL > 10k 4 5 SUPPLY VOLTAGE (V) 6
TA = 25oC VSET - AGND = 0.8V RL > 10k -10 4 5 SUPPLY VOLTAGE (V) 6
FIGURE 12. OUTPUT VOLTAGE FULL SCALE vs SUPPLY VOLTAGE
FIGURE 13. OUTPUT ZERO OFFSET VOLTAGE vs SUPPLY VOLTAGE
10-10
HI1260 Typical Performance Curves
(Continued)
INTERNAL REFERENCE VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
1.20
1.20
1.15
IREF = -400A AVCC = DVCC = 5.0V
1.15 TA = 25oC IREF = -400A 4 5 SUPPLY VOLTAGE (V) 6
-20
0
20
40
60
80
AMBIENT TEMPERATURE (oC)
FIGURE 14. INTERNAL REFERENCE VOLTAGE vs AMBIENT TEMPERATURE
FIGURE 15. INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE
0
-20 CROSSTALK (dB)
-40 TA = 25oC OUTPUT VOLTAGE FULL SCALE 1VP-P fCLK = 2fDATA AVCC = DVCC = 5.0V RL > 10k, CL < 20PF PINS 30, 32, 34 AND 36 ARE CONNECTED TO AVCC 10 DATA FREQUENCY (MHz) 20
-60
-80
-100
FIGURE 16. CROSSTALK AMONG R, G AND B vs DATA FREQUENCY
10-11
HI1260 Typical Application Circuit
19, 37, 43
DATA (TTL LEVEL)
(R) 8 (G) 8 (B) 8
39 - 42 44 - 47 1-8
33
ROUT
+ GOUT R
-
R LPF ROUT
31 9 16 28, 30, 32 29 34, 35, 36 27 25 24 23
+ BOUT R
-
LPF
GOUT
+
-
LPF BW = 16MHz
BOUT
VREF VSET + 3K R IS MATCHING RESISTANCE FOR LPF AGND DGND AVCC DVCC
-
33F
CLK (TTL LEVEL)
CLK
18 HI1260
20
FIGURE 17.
Notes On Use
* Setting of Pin 24 (VSET) The full scale of the D/A output voltage changes by applying voltage to pin 24 (VSET). When load is connected to pin 25 (VREF), DC voltage of 1.2V is issued and the said voltage is dropped to 0.87V by resistance division. When the 0.87V is applied to pin 24 (VSET), the D/A output of 1VP-P can be obtained. Satisfy the standard of the setup time (tS) and hold time (tH) indicated in the electrical characteristics. As to the reaming of tS and tH , see the timing chart. Moreover, the clock pulse width is desired to be as indicated in the recommended operating condition.
5.0
25 24 23
VREF R1 VSET R2 R
RESISTANCE (k)
1.0
AGND
0.3
FIGURE 18. EXAMPLE OF USE
Adjustment Method The resistance R is determined in accordance with the recommended operating condition of IREF (Current flowing through resistance R). See R vs IREF of Figure 19. The calculation expression is as follows: R = VREF/IREF . Adjust the volume so that the RGB output voltage full scale becomes 1.0V. (At this point, it becomes R1:R2 = 2:5). * Phase Relationship Between Data and Clock In order to obtain the desired characteristics as a D/A converter, it is necessary to set the phase relationship correctly between the externally applied data and clock.
0.1 0.1 0.2 1 PIN CURRENT IREF (mA) 5
FIGURE 19. RESISTANCE vs VREF PIN CURRENT
* Regarding the Load of D/A Output Pin Receive the D/A output of the next stage with high impedance. In other words, perform so that it becomes as follows: RL > 10k CL < 20pF The temperature characteristics indicated in the characteristics diagram has been measured under this condition.
10-12
HI1260
However, when it is made to RL 10k the temperature characteristics may change considerably. In addition, when it is made to CL 20pF, the rise and fall of the D/A output become slow and will not operate at high speed. * Noise Reduction Measures As the D/A output voltage is a minute voltage of approximately 4mV per one step, ingenuity is required in reducing the noise entering from the outside of the IC as much as possible. Therefore, use the items given below as reference. When mounting onto the printed board, allow as much space as possible to the ground surface and the VCC surface on the board and reduce the parasitic inductance and resistance. It is desirable that the AGND and DGND be separated in the pattern on the board. It is similar with AVCC and DVCC . As shown in the diagram below, for example, it is recommended that the wiring to the electric supply of AGND and DGND as also AVCC and DVCC be conducted separately, and then making AGND and DGND as also AVCC and DVCC in common right near the power supply respectively. Inset in parallel a 47F tantalum capacitor and a 100pF ceramic capacitor between the VCC surface on the printed board and the nearmost ground surface (A of diagram below). It is also desirable to insert the above between the VCC surface near the pin of the IC and the ground surface (B of diagram below). They are bypass capacitors to prevent bad effects from occurring to the characteristics when the power supply voltage fluctuates due to the clock, etc. It is recommended to reduce noise which overlaps the D/A output by inserting a capacitor of over 0.1F between pin 23 (AGND) and pin 24 (VSET).
CXI260Q-Z
B DGND AVCC
A POWER SUPPLY
DVCC PRINTED BOARD
AGND +5V 0V
FIGURE 20.
10-13

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