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| IW4034B 8-STAGE STATIC BIDIRECTIONAL PARALLEL/ SERIAL INPUT/OUTPUT BUS REGISTER High-Voltage Silicon-Gate CMOS The IW4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/ B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). ORDERING INFORMATION Data inputs include 16 bidirectional parallel data lines of which IW4034BN Plastic the eight A data lines are inputs (3-state outputs) and the B data IW4034BDW SOIC lines are outputs (inputs) dependung on the signal level on the TA = -55 to 125 C for all A/B input. In addition, an input for SERIAL DATA is also packages provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply PIN ASSIGNMENT LOGIC DIAGRAM PIN 24=VCC PIN 12= GND 1 IW4034B MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 10 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 PD r Dissipation per Output Transistor 100 mW Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IW4034B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V -55C 25C 125 Unit C V 3.5 3.5 3.5 VIH Minimum High- VOUT= 0.5 V or VCC - 0.5V 5.0 7 7 7 Level Input VOUT= 1.0 V or VCC - 1.0 V 10 VOUT= 1.5 V VCC - 1.5V 11 11 11 Voltage 15 V 1.5 1.5 1.5 VIL Maximum Low - VOUT= 0.5 V or VCC - 0.5V 5.0 3 3 3 Level Input VOUT= 1.0 V or VCC - 1.0 V 10 VOUT= 1.5 V VCC - 1.5V 4 4 4 Voltage 15 V 4.95 4.95 4.95 VOH Minimum High- VIN=GND or VCC 5.0 9.95 9.95 9.95 Level Output 10 Voltage 15 14.95 14.95 14.95 V 0.05 0.05 0.05 VOL Maximum Low- VIN=GND or VCC 5.0 0.05 0.05 0.05 Level Output 10 0.05 0.05 0.05 Voltage 15 IIN Maximum Input VIN= GND or VCC 18 0.1 0.1 1.0 A Leakage Current in High- 18 IOZ Minimum Three Output 0.4 0.4 12.0 A State State Leakage Impedance VIN= GND or VCC Current VOUT= GND or VCC 150 5 VIN= GND or VCC 5 ICC Maximum 5.0 A 300 10 10 Quiescent Supply 10 600 20 20 Current 15 3000 100 100 (per Package) 20 mA IOL Minimum Output VIN= GND or VCC 0.36 0.51 0.64 Low (Sink) UOL=0.4 V 5.0 0.9 1.3 1.6 Current 10 UOL=0.5 V 2.4 3.4 4.2 15 UOL=1.5 V mA IOH Minimum Output VIN= GND or VCC -1.6 -1.15 -2 5.0 High (Source) UOH=2.5 V 5.0 -0.64 -0.51 -0.36 Current UOH=4.6 V -0.9 -1.3 -1.6 10 UOH=9.5 V -2.4 -3.4 -4.2 15 UOH=13.5 V 3 IW4034B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input tr=tf=20 ns) Symbol fmax tPHL, tPLH Parameter Maximum Clock Frequency (Figure 2) Maximum Propagation Delay, A(B) Parallel Data In to B(A) Parallel Data Out; Serial to Parallel Data Out (Figures 1,2) Maximum Propagation Delay, A/B or AE to "A" Output (Figure 3) VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55 25C 125 C C 1 2 2 2.5 5 5 3.5 7 7 1400 700 700 480 240 240 340 170 170 400 160 120 200 100 80 400 160 120 200 100 80 7.5 800 320 240 400 200 160 Unit MHz ns tPLZ, tPHZ, tPZL, tPZH tTHL, tTLH Maximum Output Transition Time, Any Output (Figures 1,2) CIN Maximum Input Capacitance ns ns pF TIMING REQUIREMENTS(CL=50pF, RL=200 k, Input tr=tf=20 ns) Guaranteed Limit VCC Symbol Parameter V 25C 125 C 55C 320 160 160 tsu Minimum Setup Time, Serial Data to 5.0 120 60 60 Clock (Figure 4) 10 80 40 40 15 100 50 50 tsu Minimum Setup Time, Parallel Data to 5.0 60 30 30 Clock (Figure 4) 10 40 20 20 15 100 50 50 th Minimum Hold Time, Clock to Data 5.0 30 15 15 (Figure 4) 10 20 10 10 15 700 350 350 tw Minimum Pulse Width, AE, P/S, A/S 5.0 280 140 140 (Figure 5) 10 160 80 80 15 500 250 250 tw Minimum Pulse Width, Clock (Figure 2) 5.0 200 100 100 10 140 70 70 15 30 15 15 tr ,tf Minimum Input Rise or Fall Time, Clock 5.0 30 15 15 (Figure 2) 10 30 15 15 15 Unit ns ns ns ns ns ns 4 IW4034B TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION "A" Enable P/S A/B A/S Operation* L L L X Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs Disabled L L H X Serial Mode, Synch. Serial Data Input, "B" Parallel Data Output L H L L Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled L H L H Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled L H H L Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data Outputs, Synch. Data Recirculation L H H H Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data Outputs, Asynch. Data Recirculation H L L X Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output H L H X Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output H H L L Parallel Mode; "B" Synch. Parallel Data Input, "A" Parallel Data Output H H L H Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data Output H H H L Parallel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data Output H H H H Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data Output * Outputs change at positive transition of clock in the serial mode and when the A/S control input is "low" in the parallel mode. During transfer from parallel to serial operation A/S should remain low in oder to prevent DS transfer into Flip Flops. X = Don't Care PARALLEL OPERATION A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow. The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low. SERIAL OPERATION A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed). The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high). 5 IW4034B FLIP-FLOP TRUTH TABLE Inputs CLS Output Q L L INVALID CONDITION L H H INVALID CONDITION CLM D L L L X H H H X = don't care Figure 1. Asynchronous operation Figure 2. Synchronous operation Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms 6 IW4034B TIMING DIAGRAM 7 IW4034B EXPANDED LOGIC DIAGRAM Steering logic diagram Register stage logic diagram (1/8 stages) 8 |
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