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Freescale Semiconductor Advance Information
Document Number: MC33899 Rev. 2.0, 6/2007
Programmable H-Bridge Power IC
The 33899 is designed to drive a DC motor in both forward and reverse shaft rotation under pulse-width modulation (PWM) control of speed and torque. A current mirror output provides an analog feedback signal proportional to the load current. A serial peripheral interface (SPI) is used to select slew rate control, current compensation limits and to read diagnostic status (faults) of the HBridge drive circuits. SPI diagnostic reporting includes open circuit, short circuit to VIGNP, short circuit to ground, die temperature range, and undervoltage on VIGNP.
33899
PROGRAMMABLE H-BRIDGE POWER IC
Features * Drives Inductive Loads in a Full H-Bridge Configuration VW SUFFIX (Pb-FREE) * Current Mirror Output Signal (Gain Selectable via External 98ASH70693A Resistor) 30-PIN HSOP * Short Circuit Current Limiting * Thermal Shutdown (Outputs Latched Off Until Reset via SPI) ORDERING INFORMATION * Internal Charge Pump Circuit for the Internal High-Side MOSFETs Temperature * SPI-Selectable Slew Rate Control and Current Limit Control Device Package Range (TA) * Overtemperature Shutdown * Outputs Can Be Disabled to High-Impedance State MC33899VW/R2 -40C to 125C 30 HSOP * PWM-able up to 11 kHz @ 3.0 A * Synchronous Rectification Control of the High-Side MOSFETs * Low RDS(ON) Outputs at High Junction Temperature (< 165 m @ TA = 125C, VIGNP = 6.0 V) * Outputs Survive Shorts to -1.0 V * Pb-Free Packaging Designated by Suffix Code VW
VDDL +5.0 V VIGNP
33899
VIGNP VCC VDDQ CSNS REDIS CRES VCCL FWD REV PWM EN1 S0 RS EN2 CS SCLK D1 D0 LSCMP GND S1
MCU
Figure 1. 33899 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGNP
CRES
Charge Pump To Gate Drives M1 M3 S1 Current Sense, Limitation, and Mirror
VCC VCCL CSNS
+3.3 V Internal Regulator
S0 M2 Gate Drives M4 PWM Override
REDIS
LSCMP FWD REV PWM EN1 EN2 VDDQ SCLK CS DI DO
Direction and PWM Control
Baseline Slew Rate Set
RS
Command, Fault, and Temperature Register
Temperature Sense and Shutdown
GND
Figure 2. 33899 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
Tab VDDQ DO DI SCLK
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRES REDIS VIGNP VIGNP S0 S0 GND NC LSCMP EN2
CSNS VCC VCCL REV FWD PWM RS VIGNP VIGNP S1 S1 GND NC NC EN1
Tab
Figure 3. 33899 Pin Connections Table 1. 33899 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number 1 2 3 4 5 6 7 Pin Name VDDQ DO DI SCLK CS CRES REDIS Formal Name Logic Level Output Bias SPI Data Out SPI Data In SPI Serial Clock Input Chip Select (Active Low) Charge Pump Automatic Output ReEnable Disable Definition Sets VOH level of DO output and LSCMP. SPI control data output pin from the IC to the MCU. SPI control data input pin from the MCU to the IC. The SCLK input is the clock signal input for synchronization of serial data transfer. This pin is an input connected to a chip select output of an MCU. This pin connects an external capacitor, which is the storage reservoir for the internal charge pump. This input pin is a connection to a capacitor that determines the default time the output will be turned off when the low-side current comparator is tripped, if PWM has not commanded it. The typical value with a 0.1 F is 100 s. If shorted, the feature is disabled. This input pin is the primary H-Bridge power input. Note: Not reverse voltage protected. These output pins drive the bi-directional motor and must be connected together on the PC board. These pins must be connected on the PC board to the exposed pad. These pins have no internal connections. This output pin pulses high anytime the low-side current comparator is tripped. These input pins determine the mode of the IC; namely, sleep, standby, and run. These output pins drive the bi-directional motor and must be connected together on the PC board.
8, 9, 22, 23 10, 11 12, 19 13, 17, 18 14 15 16 20, 21
VIGNP S0 GND NC LSCMP EN2 EN1 S1
Protected Ignition Voltage Bridge Output 0 to Load Ground No Connect Low-Side Comparator Master Enable 2 Master Enable 1 Bridge Output 1 to Load
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PIN CONNECTIONS
Table 1. 33899 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number 24 25 26 27 28 29 30 Tab/Pad Pin Name RS PWM FWD REV VCCL VCC CSNS Thermal Interface / GND Formal Name Slew Rate Control PWM Input Forward Input Reverse Input 3.3 V Input 5.0 V Input Current Sense Exposed Pad Thermal Interface Definition This input pin is connected to a resistor that sets slew timing. This input pin is used to set the motor switching and frequency duty cycle. This input pin, along with the reverse input pin REV, determines the direction of current flow in the H-Bridge. This input pin, along with the forward input pin FWD, determines the direction of current flow in the H-Bridge. 3.3 V input source. 5.0 V input source. Output of current amplifier. The exposed pad, a thermal interface for sinking heat from the device, is a highcurrent GND connection and must be connected to GND (pins 12 and 19).
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Protected Power Supply Voltage Logic Supply Voltage Logic Output Bias Voltage VCCL Supply Voltage Input / Output Voltage (FWD, REV, EN1, EN2, PWM, CS, DI, SCLK, DO, CSNS, LSCMP, RS, REDIS) Motor Outputs Charge Pump Voltage ESD Voltage (1) Human Body Model Machine Model THERMAL RATINGS Operating Temperature(2) Ambient Junction Storage Temperature Thermal Resistance, Junction to Ambient
(3)
Symbol
Value
Unit
VIGNP VCC VDDQ VCCL VI / O VS0, VS1 VCRES VESD1 VESD2
- 0.3 to 40 - 0.3 to 7.0 - 0.3 to 7.0 - 0.3 to 5.0 - 0.3 to 7.0 - 0.5 to 40 - 0.3 to 50
V V V V V V V V
2000 200
C TA TJ TSTG RJA RJC T SOLDER - 40 to 125 - 40 to 150 - 65 to 150 18 <0.5 220 C C/W C/W C
Thermal Resistance, Junction to Case (Exposed Pad) Peak Package Reflow Temperature During Solder Mounting (4)
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. 4. The junction temperature is the primary limiting parameter. The module thermal design must provide a low enough thermal impedance to keep the junction temperature within limits for all anticipated power levels and ambient temperatures. RJA is referenced to JEDEC standard 2s2p thermal evaluation board at 1W total device power dissipation in still air. Deviations from this standard will produce corresponding changes in the actual thermal performance. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics at - 40C TJ +150C, 4.75 V VCC 5.25 V, 3.14 V VCCL 3.47 V, 2.97 V VDDQ 5.25 V, 6.0 V VIGNP 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT VIGNP Operating Voltage VIGNP Operating Current VIGNP = 14.5 V, H-Bridge Disabled, EN1 = EN2 = 5.0 V VIGNP Sleep Current EN1 = EN2 = 0 V Undervoltage Shutdown Threshold Overvoltage Shutdown Threshold VCC Operating Voltage VCC Operating Current @ 5.0 V VCC Sleep Current EN1 = EN2 = 0 V VCCL Operating Voltage VCCL Operating Current @ 3.3 V VCCL Sleep Current EN1 = EN2 = 0 V VDDQ Operating Voltage VDDQ Operating Current VDDQ Sleep Current EN1 = EN2 = 0 V POWER-ON RESET Power-ON Reset Threshold VCC Rising Power-ON Reset Threshold VCCL Rising Power-ON Reset Hysteresis CHARGE PUMP CRES Voltage (MOSFETs 1 and 3 or 2 and 4 ON) ICRES = - 0.1 mA VIGNP = 6.0 V 9.5V VIGNP 26.5 V CONTROL INPUTS Input Low Voltage EN1, EN2, PWM, CS, SCLK, DI, FWD, REV Input High Voltage EN1, EN2, PWM, CS, SCLK, DI, FWD, REV VIH 2.0 - - VIL - - 0.8 V V VCRES 14 VIGNP + 10 - - - 45 V VPOR HYS VCCLPOR 2.50 0.2 - - 2.95 0.5 V VCCPOR 3.9 - 4.7 V V VIGNP UV VIGNP OV IVIGNP - 3.4 27 4.75 - - - - - - 145 4.2 32 5.25 5.0 V V V mA A - - - - 25 3.47 3.0 V mA A - - - - 2.0 5.25 200 V A A - - 50 VIGNP IVIGNP - - 10 A 6.0 - 26.5 V mA Symbol Min Typ Max Unit
VCC
IVCC IVCC
VCCL
IVCCL IVCCL
3.14 -
VDDQ
IVDDQ IVDDQ
2.97 -
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics at - 40C TJ +150C, 4.75 V VCC 5.25 V, 3.14 V VCCL 3.47 V, 2.97 V VDDQ 5.25 V, 6.0 V VIGNP 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CONTROL INPUTS (CONTINUED) Input Leakage Current -- Digital Inputs SCLK, DI: VIN = 0 V Input Bias Current EN1, EN2, FWD, REV, PWM: VIN = 5.0 V
CS: VIN = 0 V
Symbol
Min
Typ
Max
Unit
IIN - 5.0 - 5.0
A A
IDWN IUP
27 - 70
- -
70 - 27
DATA OUTPUT Data Output Low Voltage IOL = 1.6 mA Data Output High Voltage IOH = - 800 A Data Out Tri-State Leakage POWER OUTPUT Breakdown Voltage S0, S1, VIGNP: I = 100 A ON-Resistance (Each Output FET) IOUT = 3.5 A, VIGNP = 6.0 V Body Diode Forward Voltage (All 4 Output Diodes) (6) ENx = 0 V, IOUT = 3.0 A, TJ = 150C ENx = 0 V, IOUT = 3.0 A, TJ = 23C ENx = 0 V, IOUT = 3.0 A, TJ = -40C OFF-State Output Bias VCC = 5.0 V, EN1 = EN2 = 0 V, S0 Shorted to S1 (Through Motor) OFF-State Output Leakage (between SO and S1) VCC = 0 V, EN1 = EN2 = 0 V, RL = 600 , VIGN = 16 V VCC = 5.0 V, EN1 = EN2 = 0 V, RL = 600 , VIGN = 18 V Fault Threshold (OFF State) (EN1 = EN2 = 0 V) Measured at S1 Measured at S0 CURRENT SENSE Current Sense Zero FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V, IS1/S0 = 0 A Current Sense Ratio: kCSNS = IS1/S0 / ICS (FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V) IS1/S0 = - 0.4 A IS1/S0 = - 1.6 A IS1/S0 = - 6.0 A(7) kCSNS kCSNS kCSNS 250 340 - - - 400 500 435 - ICSZ - - 0.2 mA VFAULT_THR1 VFAULT_THR2 0.65 VCC 0.15 VCC - - 0.85 VCC 0.35 VCC ILEAK - - - - 100 100 V VBIAS 0.2 VCC - 0.6 VCC A VF - - - - - - 1.0 1.4 1.8 V RDS(ON) - - 165 V VBVDS 40 - - m V ILEAK VDO_OH VDDQ - 0.5 - 5.0 - - - 5.0 A VDO_OL - - 0.4 V V
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics at - 40C TJ +150C, 4.75 V VCC 5.25 V, 3.14 V VCCL 3.47 V, 2.97 V VDDQ 5.25 V, 6.0 V VIGNP 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CURRENT SENSE (CONTINUED) Current Sense Saturation Voltage FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V, RCSNS= 10 k High-Side Current Limit DI Bit 4 and Bit 3 = 00 DI Bit 4 and Bit 3 = 01 DI Bit 4 and Bit 3 = 10 DI Bit 4 and Bit 3 = 11 Low-Side Current Limit DI Bit 4 and Bit 3 = 00 DI Bit 4 and Bit 3 = 01 DI Bit 4 and Bit 3 = 10 DI Bit 4 and Bit 3 = 11 Low-Side Current Limit Comparator DI Bit 4 and Bit 3 = 00 DI Bit 4 and Bit 3 = 01 DI Bit 4 and Bit 3 = 10 DI Bit 4 and Bit 3 = 11 Current Limit Current Comparator Differential DI Bit 4 and Bit 3 = 00 DI Bit 4 and Bit 3 = 01 DI Bit 4 and Bit 3 = 10 DI Bit 4 and Bit 3 = 11 LSCMP Output Voltage IOL = 100 A IOH = -100 A REDIS Current Pullup Current Source Pulldown Current Sink REDIS Threshold Voltage Where Low-Side MOSFET Turns On Voltage Where Low-Side MOSFET Turns Off Hysteresis THERMAL Thermal Shutdown (6), SPI Bits = 11 Thermal Hysteresis (6) Temperature Warning (6), SPI Bits = 01 Temperature Warning Hysteresis (6) TLIM THYS TWARN TWARN(HYS) 157.5 3.0 132.5 3.0 - - - - 172.5 10 147.5 10 C C C C IREDIS_sc IREDIS_sk VREDIS_THR 3.6 3.35 0.15 - - - 4.4 4.15 0.35 -160 1.0 - -70 5.0 A mA V VLSCMP_OL VLSCMP_OH - - - 0.1 ICURLIM ILSCMP ILSCMP 3.2 4.2 5.0 7.5 1.0 1.0 1.0 1.0 - - - - 3.0 3.0 3.0 3.0 5.2 6.4 7.5 10.6 A - - - - V
(5) (5)
Symbol
Min
Typ
Max
Unit
VCSNS_SAT IHSLIM
VCC - 0.2 5.8 7.2 8.0 10.0
-
VCC + 0.2 10.2 11.9 13.5 17.9
V A
- - - -
ILSLIM 5.3 6.4 7.4 10.0 - - - - 8.6 10.0 11.0 15.0
A
A
VDDQ-0.5
VDDQ
Notes 5. Production test at 125C is at VIGNP 18 V. Operation to 26.5V is guaranteed by design. 6. 7. Guaranteed by characterization in the development phase. Parameter not tested. Design Information, not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics at - 40C TA 125C, 4.75 V VCC 5.25 V, 6.0 V VIGNP 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic PWM Frequency (8) PWM / Output Duty Cycle Accuracy Frequency = 10 kHz, RS = 10 k, Slew Time = 1X, Duty cycle = 50% Short Circuit Filter (S0 and S1) Minimum PWM Low Pulse Width (8) Low-Side Comparator One Shot Pulse Duration After a Low-Side Comparator Trip Low-Side Comparator Blank Time Blanking Time After a Low-Side Comparator Pulse Overtemperature Shutdown Filter (time before Die Temp bit is set), (8) Enable Lead Time (8) Enable Lag Time (8) Delay Until Output Shuts Off Short Circuit Detection or EN1 Falling or EN2 Falling Until H-Bridge Disables Dead Timer (9) Time Between High-Side MOSFET and Low-Side MOSFET Transition Open Load Fault Delay Duration of Fault Condition Until Fault Gets Latched In Overvoltage Shutdown Filter Time from VIGNP > VOV to MOSFET Output Disable Sleep Recovery Time(8)(9)(10) Slew Time S0 and S1(11) (Output Load = 5.0 mH and 1.6 , 30% to 70%, VIGNP = 14.5 V) Slew Mode = 1X RS= 50 k RS = 10 k, Short Slew Mode = 2X RS = 50 k RS = 10 k, Short Slew Mode = 4X RS = 50 k RS = 10 k, Short 5.0 1.2 - - 12.8 3.0 2.8 0.5 - - 6.3 1.5 1.6 0.2 - - 3.2 0.8 Symbol Min - Typ - Max 11 Unit kHz % -4.5 - - - 4.5 11 0.2 s s s 5.0 - 10 s 5.0 - - - - 10 13.5 - - s ns ns s - - 5.0 s 1.0 - 3.0 s 200 - 400 s 100 - 150 200 - s s
f PWM
OUTACC
t SCF
PWMMIN
5.0 -
t LSC t LSCB t OTF
t LEAD t LAG 5.0 140 50
t SODLY t DEAD t FDO t OVS t SLEEP
S0 / S1RS -
Notes 8. Design information. 9. Guaranteed by characterization in the development phase. Parameter not tested. 10. Sleep recovery time is the time from EN going high until the outputs are ready to respond to input. This time is dependent on the recovery time of VCCL and VCCL_POR. The recommended value for the VCCL capacitor is designed to permit initialization of internal logic prior to clearing of the POR condition (See + 3.3 V Input (VCCL) on page 12). 11. By design, if the RS input is left open, the slew time is the same as when shorted to GND. However, this is a high-impedance input and will be susceptible to external noise sources unless terminated appropriately. It is highly recommended to terminate this pin with either a ground or one of the program resistors .
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics at - 40C TA 125C, 4.75 V VCC 5.25 V, 6.0 V VIGNP 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI CHARACTERISTICS (12) Transfer Frequency (13) SCLK Period (13) SCLK High Time (13) SCLK Low Time (13) DI Input Setup Time (13) DI Input Hold Time (13) DO Access Time DO Disable Time (14) DO Output Valid Time DO Output Hold Time (13) No Capacitor on DO Rise Time (14) Fall Time (14)
CS Negated Time (13)
Symbol
Min
Typ
Max
Unit
f OP t SCLK t SCLK_HS t SCLK_LS t DI(SU) t DI(HOLD) t DO(ACC) t DO(DIS) t DO(VALID) t DO(HOLD)
dc 160 56 56 16 20 - - -
- - - - - - - - -
6.25 - - - - - 116 100 116
MHz ns ns ns ns ns ns ns ns ns
0 tR tF t CSN C IN - - - - 500
20 - - -
- 60 30 - ns ns ns pF
Input Pins Input Capacitance (8) DI SCLK
- -
20 20
Notes 12. All SPI timing is performed with a 100 pF load on DO unless otherwise noted. 13. Design information. 14. Guaranteed by characterization.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
t LAG
t CSN
CS
t LEAD t SCLK_HS t SCLK
SCLK
t SCLK_LS t DO(ACC) t DO(VALID) t DO(HOLD) t DO(DIS)
DO
MSB OUT
DATA
LSB OUT
t R, t F
DON'T CARE
t DI(SU)
t DI(HOLD)
DI
MSB IN
DATA
LSB IN
Figure 4. SPI Timing Diagram
5.0V
VENx
0.8V tSODLY
2.0V
tENDLY
VS0-S1
@100mA
Figure 5. Shut Off and Enable Delay
S0/S1RS
S0/S1RS 70% 30%
VS0-S1
70% 30%
Figure 6. Slew Time Measurement
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33899 is a programmable H-Bridge, power integrated circuit (IC) designed to drive DC motors or bi-directional solenoid controlled actuators, such as throttle control or exhaust gas recirculation actuators. It is particularly well suited for the harsh environment found in automotive power train systems. The key characteristic of this versatile driver is configurability. The selectable slew rate permits the customer to choose the slew rate needed for performance and noise suppression. The Serial Peripheral Interface (SPI) allows the system microprocessor to clear the fault register, select a programmable current limit and select the slew rate. A unique fault restart feature allows the part to be configured to maintain limited functionality even in the presence of some faults. The 33899 is designed to drive a bi-directional DC motor using pulse-width modulation (PWM) for speed and torque control. A current mirror output provides an analog feedback signal proportional to the load current. SPI diagnostic reporting includes open circuit, short-to-battery, short-toground, die temperature range and under voltage.
FUNCTIONAL PIN DESCRIPTION VIGNP INPUT (VIGNP)
VIGNP is the primary power input for the H-Bridge. The input voltage is 0 V to 26.5 V (40 V during a load dump transient). This pin must be externally protected against application of a reverse voltage (through an external inverted N-channel MOSFET, diode, or switched relay).
OUTPUT POLARITY CONTROL (FWD/REV INPUTS)
The FWD and REV inputs determine the direction of current flow in the H-Bridge by directing the PWM input to one of the low-side MOSFETs (refer to Table 5). When a change in the current direction is commanded via the microprocessor, the PWM must switch from one low-side MOSFET to the other without shoot-through current in the HBridge. The gate voltage of the low-side MOSFETs must drop below and remain below the gate threshold voltage for the "dead time" before either of the high-side MOSFETs is commanded on. At no time are the high-side and low-side MOSFETs simultaneously on at the same side of the HBridge. The FWD and REV inputs have 50 A pull-downs to ground that disable all the outputs should an open circuit condition occur. Table 5. FWD / REV Truth Table
FWD 0 0 1 1 REV 0 1 0 1 Current Direction Off Reverse Forward Off
+ 5.0 V INPUT (VCC)
+5.0 V power input is required to power the internal analog circuitry and the +3.3 V internal regulator.
+ 3.3 V INPUT (VCCL)
A +3.3 V internal regulator powers the internal digital circuitry. The internal supply cannot be used as a power source by any other IC in the system. This output can be overdriven by an external supply. The internal supply requires a 0.47 F capacitor on this output to insure proper startup sequencing when coming out of sleep mode.
LOGIC BIAS INPUT (VDDQ)
VDDQ supplies the level shifted bias voltage for the logic level outputs designed to be read by the microprocessor. This pin will apply the logic supply voltage to DO and LSCMP making the output logic levels compliant to logic systems from 3V to over 5V.
ENABLE INPUTS (EN1, EN2)
Logic [0] in either of the Enables (EN1 or EN2) disables all four of the output drivers (refer to Table 6). While either EN1 or EN2 is at logic [1], the 33899 is still capable of detecting open circuit and short circuit faults on all of the outputs interfacing with the external load(s). The EN1 and EN2 inputs have 50 A pull-downs to ground that disable the outputs when open circuit conditions occur. Table 6. Enable Truth Table
EN1 0 EN2 0 Status Disabled (Sleep Mode)
OUTPUTS (S1 AND S0)
The S1 and S0 outputs drive the bi-directional DC motor. Each output has two internal N-channel MOSFETs connected a half-bridge configuration between VIGNP and ground. Only one internal MOSFET is on at any one time for each output. The FWD, REV, and PWM inputs control the state of the H-Bridge. The turn on / off slew times are determined by the selected RS resistor value and the SPI slew time register contents (refer to Table 8, page 22).
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
EN1 0 1 1
EN2 1 0 1
Status Disabled (Standby Mode) Disabled (Standby Mode) Enabled (Run Mode)
INPUT CONTROL OF H-BRIDGE (PWM)
The PWM input pin controls the sequencing of the PWM'ing high-side and low-side MOSFETs. A logic [1] commands the appropriate low-side MOSFET (M2 or M4) ON and the appropriate high-side MOSFET (M1 or M3) OFF. A logic [0] commands the appropriate low-side MOSFETs (M2 or M4) OFF and the appropriate high-side MOSFETs (M1 or M3) ON. The high- and low-side MOSFETs that are PWM'ed are determined by the commanded direction (FWD or REV).
If a shorted condition exists, the particular output MOSFET will be latched off after 5.0 s to 10 s. Subsequent PWM edges will retry to turn on the same MOSFET. Only when a thermal fault is reached are all outputs latched off until the clear fault bit is set by the microprocessor. Any PWM high-tolow-to-high pulse that is shorter than 500 ns keeps the lowside MOSFET from starting to turn off. The rising edge of this short pulse re-enables the low-side MOSFET if the pulse width is at least 200 s long (if a short circuit latch-off had occurred during the previous positive PWM pulse). The PWM input has a 50 A pull-down to ground that disables all the outputs should an open circuit condition occur.
High Side FET Body Diode
S0
S1
Load Current
Low Side FET Body Diode Both High Side FET's ON until next PWM Rising Edge
Current in Load reverses polarity
Forward Current
Reverse Current
PWM
FWD
REV Figure 7. 33899 Operation in Current Reversal
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
LOAD CURRENT FEEDBACK (CSNS)
The load current sense circuit mirrors a sample of the load current back to the microcontroller via the CSNS pin. It supplies a current that is 1/400th of the load current (see Equation 1). An analog multiplexer routes the enabled highside current to the CSNS pin. An external resistor connected to the CSNS pin (RCSNS) sets current to voltage gain. The circuit operates properly in the presence of high-frequency noise. An external capacitor may be necessary to provide filtering. VCSNS = IOUT 400
HIGH-SIDE AND LOW-SIDE SLEW TIME CONTROL (RS)
The turn-on and the turn-off slew times on S0 and S1 (both low- and high-side drive outputs) are adjustable from 5.0 s (50 k RS) to 1.0 s (10 k RS) to reduce high-frequency harmonic energy in the vehicle's wiring harness. In addition, slew time control is programmable to be either 1X, 2X, or 4X (via the SPI) to lower power dissipation at elevated die temperatures. The characteristics of the turn-on and turn-off voltage are linear, with no discontinuities, during the output driver state transitions. If the RS pin detects an impedance of less than 5.0 k to ground or greater than 1.0 M to ground, it defaults to the fastest slew time of 1.0 s.
. RCSNS
Eq. 1
Note This output is clamped so that it will not exceed VCC.
LOW-SIDE COMPARATOR ONE SHOT OUTPUT (LSCMP)
The LSCMP output pin pulses high for 5 s to 10 s any time the low-side comparator is tripped. Then the output goes low during a 5 s to 10 s blanking time. If another low-side comparator trip event is detected during the blanking time, another 5 s to 10 s pulse high occurs immediately after the blanking interval.
CHARGE PUMP RESERVOIR CAPACITOR (CRES)
The charge pump provides an output voltage over the full operating VIGNP range that is sufficient to drive the output MOSFETs and ensure that the output RDS(ON) specifications are met. An external reservoir capacitor of 0.1 F is recommended. The charge pump operates at approximately 2.0 MHz to 4.0 MHz in order to prevent interference with AM entertainment radio.
LS Current Comparator 5 - 10 s PWM > 40 s LSCmp The REDIS min duration = 25 s, so CREDIS must be > 1 nF Iload 5 - 10 s
5 - 10 s Pulse Out
5 - 10 s Blank Time
5 - 10 s Pulse Out
Figure 8. LS Current Comparator One Shot
AUTOMATIC OUTPUT RE-ENABLE DISABLE (REDIS)
The REDIS input pin automatically re-enables the low-side MOSFET once the REDIS input voltage exceeds 4.0 V. An external capacitor (CREDIS) determines the time interval (see Equation 2). Once a low-side current comparator is tripped, a 120 A current source linearly charges the capacitor until either the next rising edge of PWM or the 4.0 V trip level is achieved. This re-enables the low-side output MOSFET and
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discharges the capacitor to 0 V. This feature is disabled by grounding this input. dt = CREDIS . dv I C . 4.0 V = 120 A Eq. 2
As per the above equation, a 2.2 nF capacitor will provide a nominal 75 s time interval.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
LS Current Comparator Iload PWM
4 VDC REDIS t = 33.3 * C (nF) s tmin = 25 s t = 33.3 * C (nF) s tmin = 25 s
Reset to 0 VDC
Reset to 0 VDC
Figure 9. Re-enable after a Low Side Current Comparator Trip
LOW-SIDE CURRENT COMPARATOR VS. CURRENT LIMIT LEVELS
There are two different current limit thresholds for the lowside MOSFETs: current comparator and current limit. Current comparator is the normal commanded switching current. Current limit is for fault protection. The inductance of the load results in just the current comparator tripping. Once the low-side current comparator has tripped and filter time expired, the low-side MOSFET turns off and the high-side MOSFET subsequently turns on for normal current re-circulation in the load. If an actual hard short to either VIGNP or ground on the S0/S1 outputs is encountered, the current limit kicks in and prevents large current spikes from VIGNP (or to ground) to occur. The threshold level of the current comparator vs. the high- and low-side current limits is given in the Static Electrical Characteristics table, page 8. As backup protection, there is a linear overcurrent controller to limit current spike during timer operations.
is placed in a high impedance state and the Fault register reloaded (latched) with the current filtered status data. To allow sufficient time to reload the Fault register, the CS pin must remain low for a minimum of t CSN prior to going high again. By design, the CS input is immune to spurious pulses of 50 ns or shorter. (DO may come out of tri-state, but no status bits are cleared and no control bits are changed.) The CS input has a 50 A current source to VCC, which pulls this pin to VCC if an open circuit condition occurs. This pin has TTL-level compatible input voltages, which allows proper operation with microprocessors using a 3.0 V to 5.0 V supply.
SERIAL CLOCK (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has TTL-level compatible input voltages, which allow proper operation with microprocessors using a 3.3 V to 5.0 V supply. When CS is asserted, both the microprocessor and the 33899 latch input data on the rising edge of SCLK. The SPI master typically shifts data out on the falling edge of SCLK, while the 33899 shifts data out on the falling edge of SCLK to allow more time to drive the DO pin to the proper level.
SERIAL PERIPHERAL INTERFACE (SPI)
The 33899 has a serial peripheral interface consisting of Chip Select (CS), Serial Clock (SCLK), Serial Data Out (DO), and Serial Data In (DI). This device is configured as a SPI slave and is daisy-chainable (single CS for multiple SPI slaves).
SERIAL DATA OUTPUT (DO)
The DO is the SPI data out pin. When CS is asserted (low), the MSB is the first bit of the word transmitted on DO and the LSB is the last bit of the word transmitted on DO. After all 8 bits of the fault register are transmitted, the DO output sequentially transmits the digital data that was just received on the DI pin. This allows the processor to distinguish a shorted DI pin condition. The DO output continues to transmit
CHIP SELECT (CS)
The CS is a low = true input that selects this device for serial transfers. On the falling edge of CS, the DO pin is released from tri-state mode, and all status information is latched in the SPI shift register. While CS is asserted, register data is shifted into the DI pin and shifted out of the DO pin on each subsequent SCLK. On the rising edge of CS, the DO pin
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
the input data from the DI input until CS eventually transitions from a logic [0] to a logic [1]. The DO output pin is in a high impedance condition unless CS is low, at least one enable pin is high and VCC and VCCL are within the normal operating range. When active, the output is "rail to rail", depending on the voltage at the VDDQ pin.
SERIAL DATA INPUT (DI)
The DI input takes data from the microprocessor while CS is asserted (low). The MSB is the first bit of each word received on DI and the LSB is the last bit of each word received on DI. The 33899 serially wraps around the DI input bits to the DO output after the DO output transmits its fault flag bits. The first 8 bits before CS goes high are latched into the Control register. Any bytes transmitted before the last 8 bits are just wrapped around to the DO output and are not used by the 33899 (see Figure 10). This pin has TTL-level compatible input voltages, which allow proper operation with microprocessors using a 3.3 V to 5.0 V supply.
CS
CS*
DI/ DI/ SCLK SCLK
Not Used (1 Byte) Not Used (1 Byte)
DO DO
DI Control Register (1 Byte) DI Control Register (1 Byte)
Fault/Temp Data (1 Byte) Fault/Temperature Data (1 Byte)
1st DI Byte FirstDI Byte
Figure 10. SPI Operation with Extended CS
LOGIC OUT BIAS (VDDQ)
The VDDQ input pin provides the bias voltage for the data out buffer and LS Comparator. It must be connected to the
same power supply that is used by the microprocessor's SPI I / O.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION Voltage Regulation Charge Pump H-Bridge Output Drivers S0 - S1
Current Sense Temperature Sense
Analog Control and Protection SPI Interface Command and Fault Registers PWM Controller Direction Control
MCU Interface and Output Control
Figure 11. Functional Block Diagram
INTRODUCTION H-BRIDGE OUTPUT DRIVERS (S0 AND S1)
The 33899 Power IC provides the means to efficiently drive a DC motor in both forward and reverse shaft rotation via a monolithic H-Bridge comprising low RDS(ON) N-channel MOSFETs and integrated control circuitry. The switching action of the H-Bridge can be pulse-width modulated to obtain both torque and speed control, with PWM frequencies up to 11 kHz supported with minimal switching losses. The outputs comprise four Power MOSFETs configured as a standard H-Bridge, controlled by the PWM input and the FWD and REV inputs. high-side current sense is available to the MCU as an analog current proportional to the load current. Each MOSFET has over-temperature protection circuitry that disables the device. A thermal warning sets a flag in the SPI register when the device is approaching a protection limit.
MCU INTERFACE AND OUTPUT CONTROL
The SPI and control logic signals are compatible with both 5V and 3.3V logic systems. The SPI provides programmable control of output slew rate and current limits. The status register makes detailed diagnostics available for protective and warning functions. The output drivers are controlled by the input signals EN1, EN2, FWD, REV, and PWM. The low-side and high-side MOSFETs connected to S0 are controlled by the PWM input when FWD is a logic [1] and REV is a logic [0]. The low-side MOSFET connected to S1 is idle in this state. The high-side MOSFET connected to S1 is statically ON in the forward direction. The low-side and highside MOSFETs connected to S1 are controlled by the PWM input when FWD is a logic [0] and REV is a logic [1]. The lowside MOSFET connected to S0 is idle in this state. The highside MOSFET connected to S0 is statically ON in the reverse direction. To reduce power during the recirculation period, the upper recirculation MOSFET is turned on synchronously with the OFF-time of the low-side MOSFET.
ANALOG CONTROL AND PROTECTION
The 33899 has integrated voltage regulators which supply the logic and protection functions internally. This reduces the requirements for external supplies and insures the device is safely controlled at all times when battery voltage is applied. An integrated charge pump provides the required bias levels to insure the output MOSFETs turn fully ON when commanded. Each MOSFET provides feedback to the protection circuitry by way of a current sensor. Each sense signal is compared with programmable over-current levels and produces an immediate shutdown in case of a high current short circuit. The low-side current sense is also capable of producing a current limiting PWM to reduce overload conditions as determined by the programmable limits. The
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
The PWM input is connected to the system microprocessor and provides for control of the four MOSFET outputs. The PWM duty cycle range is 0% to 100%; however, open load detection circuits require a minimum off-time.
The 33899 holds all outputs off if both FWD and REV are either logic [0]s or logic [1]s. Figure 12 depicts inputs versus outputs in forward mode operation.
VIGNP + VF S0 RDS(ON) * ILOAD VIGNP RDS(ON) * ILOAD
Load Current
PWM INPUT M1 GATE
M2 GATE Dead Time
M3 is "ON" M4 is "OFF"
Figure 12. 33899 Operation in Forward Mode
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES Short-to-GND or Short-to-VIGNP Fault Filtering
The 33899 has a short-to-GND and short-to-VIGNP digital fault filter. After a single fault occurrence, another 7 shorts consecutive with PWM must be detected before the bit is latched into the fault register. under the device, which provides a thermal path to the case of the module.
Output Synchronous Rectification Control
The 33899 uses synchronous rectification to reduce the power dissipation during the recirculation period. In order to prevent shoot-through current, the 33899 has a dead time circuit that turns on the upper recirculation MOSFET after the lower gate voltage falls below the threshold voltage and turns it off before the lower gate voltage rises above the threshold voltage.
Short to -1.0 V on Output Devices
The 33899 can survive a short to -1.0 V through a 300 m impedance (10 kHz to 1000 kHz) and a direct short to - 0.5 V on all I/Os that exit the module. A shorted output to these voltages does not impact correct fault diagnostics for the effected channel or any other normal operation of the 33899. This feature applies to the SO and S1 outputs as well.
Output Overvoltage Shutdown
The 33899 disables all MOSFET outputs when VIGNP is above the overvoltage shutdown threshold for a time period greater than t OVS (refer to Dynamic Electrical Characteristics table, page 9).
Loss of Module Ground
Loss of ground condition at the parts level denotes that all pins of the 33899 see very low impedance to ignition. In the application, a loss of ground condition results in all I/O pins floating to ignition voltage VIGNP, while all externally referenced I/O pins are at worst case pulled to ground.
Output Avalanche Protection
An inductive fly-back event, namely when the outputs are suddenly disabled and VIGNP is lost, could result in electrical overstress of the drivers. To prevent this the VIGNP input to the 33899 should not exceed 40 V during a fly-back condition. A zener clamp and/or an appropriately valued capacitor are common methods of limiting the transient.
Loss of Module Ignition Supply
Loss of ignition condition at the parts level denotes that the power input pins of the 33899 see infinite impedance to the ignition supply voltage (depending on the application) but there is some undefined impedance from these pins to ground.
Power-ON Reset (POR)
On power-up, the VCC and VCCL supplies to the 33899 typically increase to 5.0 V and 3.3 V, respectively, within 0.3 ms to 3.0 ms. The 33899 has power-ON reset (POR) circuitry that monitors both the VCC and VCCL voltages. When either voltage falls below its POR threshold, the S0 and S1 outputs are driven to the inactive state. When both voltages rise above the POR threshold, the outputs are enabled. During POR none of the outputs momentarily glitches ON. The contents of all SPI registers (both DI and DO) are cleared on each power-ON reset cycle. See + 3.3 V Input (VCCL) on page 12 for part requirements to guarantee normal operation.
Output Driver Load(s)
The 33899 is capable of driving any PWM'ed inductive load of up to 3.5 A of continuous average current (at a maximum frequency of 11 kHz) with current feedback capability. The 33899 drives ETC (Electronic Throttle Control) motors. The typical characteristics of the ETC motor are as follows: *Resistance 1.25 to 2.4 (lumped resistance due to actuator, harness, and connectors) over the temperature range. *Inductance 800 H at 1000 Hz over the temperature range.
Fault Detection
Open load detection is performed in the OFF state, and short circuit fault detection is performed while the H-Bridge circuit(s) are enabled (see Figure 13, page 20). However, the user can determine whether an open circuit has caused the output current to go to 0 A via the CSNS output. All valid faults are latched into the SPI Fault register and cleared when a logic [1] is written to the FLTCLR bit by the system microprocessor (refer to Table 8, page 22).
Output Power Density
The die area for the output MOSFETs provides an adequate thermal resistance to limit junction temperature to 150C when the device is operated at 11 kHz, 3.5 A continuous average current, and a 2.0 ms nominal transition time. This applies to FR4 PC board with a metal pedestal
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
EN1 EN2 VCC
12 k S1 0.75 VCC OF
pulled down internally to ground. In a normal load state, the low impedance (relative to the internal pull-ups/pull-downs) will force both load connections to about 0.5 VCC. S1 is compared with an internal reference of 0.75 VCC nominally, while S0 is compared to an internal reference of 0.25 VCC nominally. Table 7 indicates what status the load will be in based on the combination of the outputs of these two comparators. Table 7. OFF-State Fault Detection
SGFON SGF
S1 < 0.75 VCC
S0 > 0.25 VCC < 0.25 VCC < 0.25 VCC > 0.25 VCC
Load Status Normal Load Short to Ground Open Load Short to VIGNP
0.25 VCC S0 12 k SBFON
Fault Timer
SBF
< 0.75 VCC > 0.75 VCC > 0.75 VCC
Note SGFON and SBFON are ON-State Fault.
Figure 13. OFF-State Fault Detection Diagram In the full or half H-Bridge mode an open, short to ignition, or short to GND latches the appropriate SPI fault bits until the FLTCLR bit is set. Any additional faults that occur prior to setting FLTCLR will be ignored.
Fault Detection During OFF State
Fault detection for both the high-side and low-side outputs is done during the OFF state, when either the EN1 or EN2 pin is a logic [1], by analyzing the states of both the high-side and low-side outputs interacting to the external load. S1 is pulled up internally via a high-impedance pullup to VCC, while S0 is
Once any of the above faults are indicated for a period of time exceeding the OFF-state fault timer, the fault bit will be latched into the SPI Fault register. The OFF-state fault timer is started when either the EN1 or EN2 pin transitions from a logic [1] to a logic [0] (both inputs previously logic [1]) or from a logic [0] to a logic [1] (both inputs previously logic [0]). The OFF-state filter time is substantially longer than the ON-state to allow energy in the load to dissipate. False open state faults may be set when the outputs are shut down and the load current (reverse polarity only) takes more than the OFFstate filter time to decay to zero. The microprocessor should clear the open state fault SPI bit and read the Fault register again under this condition.
Load Current (Reverse Polarity)
S0
S1
EN1
S0/S1 are at 2.5 VDC, No SPI Bits Set Wake Up, Open Fault Timer Starts tFDO tFDO
Open Fault Timer Starts
Goo Back to Sleep
EN2
Current in Load < 0, Erroneous Open Fault SPI Bit Set
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Fault Detection During ON State
While the H-Bridge circuit is in operation (i.e., when a highside MOSFET is ON), the 33899 is capable of detecting both shorts to VIGNP and shorts to ground. A short will cause the appropriate MOSFETs to current limit. The current limit is active for numerous retry periods until an overtemperature condition is reached, at which time all outputs are turned OFF. All ON-state faults must be present for a period of time that exceeds the fault time before the 33899 will consider them valid. Once they are valid, they are latched until the SPI has reported these faults to the microcontroller via the DO pin and a logic [1] is written to the FLTCLR bit.
In order for the user to be certain that all detectable ONstate faults have been reported, a minimum ON time is required for the low-side MOSFET. For example, if the PWM frequency is 11 kHz, ON-state fault detection would not be guaranteed for duty cycles of less than 11%.
Thermal Shutdown
The H-Bridge has thermal protection circuitry. A thermal fault sets the thermal shutdown bits (and any other faults that may be present at that time) and latches off. The H-Bridge will remain disabled until the microprocessor sets the FLTCLR bit (refer to Table 8, page 22).
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND REGISTER DESCRIPTION SPI Control Register Definition
An 8-bit SPI allows the system microprocessor to clear the Fault register, select a programmable current limit, and select a 1X, 2X, or 4X slew rate. The SPI Control Register bit definitions are shown in Table 8. Note At POR, all bits in the register are cleared to 0s.
Table 8. SPI Control Register Bit Definitions
8 (MSB) FLTCLR 7 Not Used 6 Not Used 5 Not Used 4 Current Limit 3 Current Limit 2 Slew Time 1 (LSB) Slew Time
Bit 8: FLTCLR: 0 = Retain faults; 1 = Clear faults Bit 7: Not used Bit 6: Not used Bit 5: Not used Bits 4 - 3: Set Low Side Current Comparator Limits 00 = 4.0 A 01 = 5.0 A 10 = 6.0 A 11 = 8.5 A Bits 2 - 1: Slew Time 00 = 1X 01 = 2X 10 = 4X 11 = 4X
SPI Fault Register Definition
The fault diagnostic capability consists of one internal 8-bit Fault register. Table 9 shows the content of the Fault register. The output load status of the H-Bridge circuit is reported via the output DO SPI bits. In addition to output fault information, die temperature warnings and overtemperature conditions are reported.
An SPI read cycle is limited by a CS logic [1] to logic [0] transition, followed by 8 SCLK cycles to shift the fault register bits out the DO pin. The rising edge of CS sets DO in a high impedance mode and clears the fault latches if the FLTCLR bit is set. The thermal fault is immediately set again if the fault condition is still present. Accurate fault reporting can only be obtained by reading the DO line at intervals greater than the fault timer. A thermal fault will be latched as soon as it occurs. Note At POR, all bits in the register are cleared to 0s.
Table 9. SPI Fault Register Bit Definitions
8 (MSB) ShVIGNP 7 ShGnd 6 Open Fault 5 Overvoltage or Undervoltage 4 LS Comparator 3 EN1, EN2 Status 2 Die Temp 1 (LSB) Die Temp
Bit 8: Short to VIGNP: 0 = No fault; 1 = S1 or S0 shorted to VIGNP (Low-Side Linear Current Limit has tripped) Bit 7: Short to Ground: 0 = No fault; 1 = S1 or S0 shorted to GND (High-Side Linear Current Limit has tripped) Bit 6: Open Fault: 0 = No fault; 1 = S1 or S0 is Open Circuited Bit 5: Overvoltage or Undervoltage: 0 = No fault; 1 = Overvoltage/undervoltage fault Bit 4: Low-Side Comparator: 0 = No trip; 1 = Tripped Bit 3: XOR function of EN1, EN2 inputs. 0 = (EN1 same logic level as EN2). 1 = (EN1 not same logic level as EN2). Bits 2 - 1: Die Temperature 00 = T < 140C 01 = 140C < T < Overtemperature Shutdown 10 = Not Defined 11 = Overtemperature Shutdown (Latched Off)
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
VW SUFFIX 30-PIN HSOP 98ASH70693A ISSUE A
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
VW SUFFIX 30-PIN HSOP 98ASH70693A ISSUE A
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 6/2006
DESCRIPTION OF CHANGES * Initial Release
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MC33899 Rev. 2.0 6/2007

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