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E2F0007-18-11 Semiconductor
Semiconductor MSM9405
IrDA Communication Controller
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GENERAL DESCRIPTION
The MSM9405 is a communication controller conforming to IrDA, the international standard for infrared data communication. The device covers the IrDA physical specifications Ver.1.0 and 1.1. Since the device performs some of the functions concerning communication protocol control, the load on the software (firmware) for protocol control can be reduced. By combining the device with another microcontroller and an infrared transceiver module, a device provided with IrDA-compliant communication function can be configured.
FEATURES
* Data transfer rates IrDA 1.0 IrDA 1.1 : 2400, 9600 bps; 19.2, 38.4, 57.6, 115.2 kbps : 0.576, 1.152, 4 Mbps
* Detection/removal for beginning of frame and end of frame (IrDA 1.0, 1.1) Insertion for beginning of frame and end of frame (IrDA 1.0, 1.1) * Generation/check for CRC (IrDA 1.0, 1.1) * Host interface 8-bit data bus DMA transfer Interrupt Address Control signal
: : : : :
D0-D7 DREQ, DACK, TC INTR A0-A3 CS, RD, WR
* Infrared module control signal : SD * Built-in 32-byte transmit-receive FIFOs * Power down mode * Built-in oscillator circuit * Crystal oscillation frequency : 18.432 MHz (other than 4 Mbps data rate) : 48 MHz (when 4 Mbps data rate used) * Operating voltage (VDD) : 2.7 to 3.6 V
* Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM9405MB)
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VDD
8
Control/Status
SD
GND
Register
D0-7 Flag Detection/ Removal Circuit DEC UART
8
DMA
Semiconductor
BLOCK DIAGRAM
Control Circuit
A0-3
CS HDLCDEC Removal Circuit Flag Detection/
TCC/RCC
RD RX_ 4 PPMPreamble/Flag Detection/ Removal Circuit
Microcontroller I/F
IrDA Demodulator CRC DEC
IRIN-A IRIN-B
WR
Receive Shift
INTR 8 Flag Insertion Circuit UART ENC
Register (RSR)
RESET
PWDN 8 HDLCENC TX_ CRC
8
Transmit-Receive FIFO
(328bit)
TC
Flag Insertion Circuit IrDA 4 PPMENC Preamble/Flag/ Insertion Circuit Modulator IROUT
Transmit Shift Register
DREQ
DMA
(TSR)
I/F
DACK
XIN
OSC
Baud Rate
MSM9405
XOUT
Generator
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TEST
Semiconductor
MSM9405
PIN CONFIGURATION (TOP VIEW)
VDD D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 CS RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XIN XOUT TEST IRIN-A IRIN-B IROUT SD TC DREQ DACK PWDN RESET INTR WR GND
30-Pin Plastic SSOP
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Semiconductor
MSM9405
PIN DESCRIPTIONS
Function Transceiver Module Interface Pin 27 26 Symbol IRIN-A IRIN-B Type I I Description Receive signal input A. (2.4 kbps to 4 Mbps)*1 Receive signal input B. (0.576 to 4 Mbps) When connecting this device to a transceiver module, tie this pin high or low if the number of the receive signal output pins that the module has is only one.*1 25 24 IROUT SD O O Transmit signal output. Active high. Transceiver module control signal output. Becomes active when PWDN is set low.*1 This pin must be left open if connecting this device to a transceiver module having no shutdown pins. Microcontroller Interface 9-2 13-10 14 15 17 18 DMA Controller Interface Others 22 21 23 20 D0-D7 A0-A3 CS RD WR INTR DREQ DACK TC PWDN I/O I I I I O O I I I Data input-output. Register address inputs. Chip select input. Active low. When low, read and write signals are enabled. Read signal input. Active low. Write signal input. Active low. Interrupt request signal output. Active low. DMA Request signal output. *1 DMA acknowledge signal input. *1 DMA transfer end signal input. Active low. Power down control. Active low. When set low, oscillation stops and the device enters power down (low supply current) mode. 19 28 30 29 1 16 RESET TEST XIN XOUT VDD GND I O I O -- -- System reset input. Active low. When set low, the internal registers are initialized. Test. Must be left open. Crystal connect. Crystal connect. Power supply. Ground.
*1 Either active high or active low can be selected depending on the register setting.
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Semiconductor
MSM9405
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VI PD TSTG Condition -- -- -- -- Rating -0.5 to +4.0 -0.5 to +6.0 230 -55 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Temperature Crystal Oscillation Frequency Symbol VDD Top fOSC Condition -- -- -- Range 2.7 to 3.6 -20 to +70 18.432 MHz 200 ppm or 48 MHz 100 ppm Unit V C --
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, Ta = -20 to +70C) Parameter "H" Input Voltage "L" Input Voltage Input Leakage Current "H" Input Voltage "L" Input Voltage Input Leakage Current "H" Output Voltage "L" Output Voltage "H" Output Voltage "L" Output Voltage Supply Current Supply Current (during Power Down) Symbol VIH VIL ILI VIH VIL ILI VOH VOL VOH VOL IDD IDPN Condition -- -- VI = VDD/0 V -- -- VI = VDD/0 V IO = -4 mA IO = 4 mA IO = -4 mA IO = 4 mA -- When PWDN = "L" Min. Typ. Max. Unit 2.2 0 -- 2.2 0 -- 2.4 -- 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5.5 0.8*1 1 5.5 0.8*1 10 -- 0.4 -- 0.4 20 -- V mA V mA V V mA mA IROUT, INTR, DREQ VDD VDD D0-D7 Applicable Pin IRIN-A, IRIN-B, PWDN A0-A3, CS, RD, WR, TC, RESET, DACK
*1 1.0 V when VDD = 3.0 to 3.6 V
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Semiconductor AC Characteristics
MSM9405
(VDD = 2.7 to 3.6 V, Ta = -20 to +70C) Parameter Read Pulse Width Read Data Delay Time Read Data Hold Time Read/Write Recovery Time CS Setup Time CS Hold Time Write Address Hold Time Write Pulse Width Write Data Setup Time Write Data Hold Time Write Address Setup Time Interrupt Clear Time DACK Pulse Width DACK Setup Time DREQ Clear Time DACK Hold Time (during Read) DACK Hold Time (during Write) TC Pulse Width TC Setup Time TC Hold Time SIR Pulse Width SIR Data Rate Tolerance MIR Pulse width MIR Data Rate Tolerance FIR Single Pulse Width FIR Data Rate Tolerance FIR Double Pulse Width Reset Pulse Width Symbol trpw trdd trdh trcv tcss tcsh twah twpw twds twdh twas tintr tdak tacs tdrqr tachr tachw ttcw ttcs ttch tspw SDRT tmpw MDRT tfpw FDRT tfdpw trstw Condition -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver -- Min. 120/70 -- 0 60 60 0 0 120/70 60 -10 -10 -- 60 10 -- -5 10 50 0 0 -- 0.9 -- -- -- 100 -- -- -- 70 -- -- -- 195 70 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.63 -- -- -- 218 -- -- -- 125 -- -- -- 250 -- -- Max. -- 60 20 -- -- -- -- -- -- -- -- 120/70 -- -- 120/70 -- -- -- -- -- -- -- 0.87 2.0 -- -- 0.1 0.2 -- 165 0.01 0.1 -- 285 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms % % ns ns % % ns ns % % ns ns ns *1 *1 *1 Note *1 *2 *3
*1 120 ns when crystal oscillation frequency = 18.432 MHz, 70 ns when crystal oscillation frequency = 48 MHz *2 That which occurs latest of the following is to be used for the data delay time (trdd) : the change of the state of A0-A3, the change from CS high to low, and the change from RD high to low. *3 That which occurs first of the following is to be used for the read data hold time (trdh) : the change of the state of A0-A3, the change from CS low to high, and the change from RD low to high. 6/30
Semiconductor * Read timing
trdd trpw CS trdd trpw A0-A3 trpw RD trcv trdh trdh
MSM9405
trdd D0-D7
trdh
tintr INTR
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Semiconductor * Write timing
tcss CS tcsh
MSM9405
twas A0-A3 twpw WR
twah
trcv
twds D0-D7
twdh
tintr INTR
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Semiconductor * DMAC access timing 1
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "0" MemoryAEM9405
MSM9405
CS tdrqr
DREQ (Active low) tdak trcv
DACK
trpw RD
trcv
twds D0-D7
twdh
M9405AEMemory
CS tdrqr DREQ (Active low) tdak trdh
trcv
DACK
twpw WR trdd D0-D7 trdh
trcv
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Semiconductor * DMAC access timing 2
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "1" M9405AEMemory
MSM9405
DREQ (Active high)
tdrqr
DACK tacs RD trcv trdd D0-D7 trdh trpw tachr
MemoryAEM9405
DREQ (Active high)
tdrqr
DACK tacs WR trcv twds D0-D7 twdh twpw tachw
WR ttcs ttcw ttch
TC
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Semiconductor * DMAC access timing 3
DMA_EN = "1", DMA_SL1 = "1", DMA_SL0 = "1" or "0" M9405AEMemory tdrqr DREQ trdd trpw CS trdd trpw A0-A3 trpw RD trdd D0-D7 trdh trdh trdh
MSM9405
MemoryAEM9405 tdrqr DREQ tcss CS twas A0-A3 twpw WR twds D0-D7 twdh twah tcsh
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Semiconductor
MSM9405
* Infrared interface timing
tspw SIR
tmpw MIR
tfpw FIR
tfdpw
* Reset timing
trstw RESET
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Semiconductor
MSM9405
FUNCTIONAL DESCRIPTION
Modes There are four modes provided by the MSM9405 for IrDA communication. Communication with IrDA1.0 is in SIR mode or Extended-SIR mode, while communication with IrDA1.1 is in MIR mode or FIR mode. In SIR mode, the MSM9405 has the necessary UART feature for IrDA communication. The Extended-SIR mode is an original feature of the MSM9405. In this mode, BOF/EOF insertion and CRC calculation/check are performed by the MSM9405. Therefore, the burden to the CPU can be reduced compared with IrDA1.0 communication using ordinary UART. Moreover, the Extended-SIR mode allows DMA transfer even in IrDA1.0 communication. In MIR mode, IrDA1.1 communication at up to 1.152 Mbps is possible. The FIR mode supports 4 Mbps transfer for IrDA1.1. Features of each mode are as follows: MSM9405 Modes Comparison
mode SIR Extended-SIR MIR FIR Transfer rate 2.4 to 115.2 kbps 2.4 to 115.2 kbps 0.576, 1.152 Mbps 4 Mbps BOF SW HW HW HW CRC SW HW HW HW EOF SW HW HW HW CE insertion/ "0" insertion/ removal SW HW -- -- removal -- -- HW --
Preamble insertion/removal
-- -- -- HW
Sending/Receiving Switching Method
CE : Control Escape Byte SW : Software HW : Hardware
Mode switching between sending and receiving is made using the TX_EN and RX_EN bits in the ICR1 (Infrared Control Register 1). For sending, writing "1" in TX_EN puts the MSM9405 in the sending mode. Writing "1" in RX_EN puts the MSM9405 in the receiving mode. If "0" is written to both TX_EN and RX_EN bits, the MSM9405 does not perform sending/receiving but enters the idle state. Each register can be set even during the idle state. Data to be sent can be written in advance to the FIFO during the idle state. If "1" is written to both TX_EN and RX_EN, the MSM9405 is put in the receiving mode. DMA Transfer The MSM9405 allows DMA transfer. The DMA transfer mode covers the single transfer mode and demand transfer mode, but not the block transfer mode. When a DMA controller with TC output is used for sending, the DMA controller and MSM9405 automatically perform highspeed transfer if the maximum frame length is specified for TFL and the transfer data length for the TC counter of the DMA controller. The timing when the DREQ signal is asserted is as follows: During receiving, DREQ is asserted when data in the FIFO is at or above the receiving threshold level or time-out occurs. If all of the received data in the FIFO is read, DREQ is deasserted. During sending, DREQ is asserted when data in the FIFO is lower than the sending threshold level. Sent data is written and DREQ is deasserted when the FIFO becomes full or TXE_EV occurs.
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Semiconductor Time-out
MSM9405
The MSM9405 outputs an interrupt request or DMA request depending on the register setting when the following time-out occurs even if the received data is below the receiving threshold level: The condition causing time-out in MIR or FIR mode is: At least 1-byte data is in the receiving FIFO and 69.5 ms has passed after data is written from the receiving shift register to the FIFO. During this period, the CPU or DMA controller does not read the FIFO data. The condition causing time-out in SIR or Extended SIR mode is: At least 1-byte data is in the receiving FIFO and time (Tout) has passed after data is written from the receiving shift register to the FIFO. During this period, the CPU or DMA controller does not read the FIFO data. Tout = 4 8 1/baud rate baud rate: Transfer rate (2.4 to 115.2 kbps) Register Map The MSM9405 contains 14 registers, of which 13 are available. Each register can be selected with the register address assigned from 0h through Ch. Various setting options are provided for each register to allow optimum communication. The registers are listed below. The register table is given on the next page.
A3-A0 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah 9h Ah Bh 0h Bh Ch Fh R/W Register Name R W R/W R R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W RDR TDR ENR EIR LSR ICR1 ICR2 MSR DSR FCR TFL (L) TFL (H) TCC (L) TCC (H) MDS (L) MDS (H) RST (L) RST (H) TEST *1 *1 *1 *1 *2 *2 *2 *2 Receive data register Transmit data register Interrupt enable register Interrupt event and status indication register Status register Transmit-receive control register BOF count setting register Register for setting a transfer mode and a data rate and selecting a crystal to be used DMA mode setting register FIFO threshold setting register Transmit frame-length setting register (low-order byte) Transmit frame-length setting register (high-order byte) Transmitter current-count register (low-order byte) Transmitter current-count register (high-order byte) Maximum data size setting register (low-order byte) Maximum data size setting register (high-order byte) Receiver frame length stack register (low-order byte) Receiver frame length stack register (high-order byte) Used for test. Description
*1 Whether TFL or TCC is read depends on the setting of the CTEST bit in the MSR register. *2 Whether MDS or RST is read depends on the setting of the CTEST bit in the MSR register. 14/30
Semiconductor
MSM9405
Register Table
Add 0 Register name TDR/RDR Mode R/W all SIR 1 ENR Ex-SIR MIR FIR SIR 2 EIR Ex-SIR MIR FIR SIR 3 LSR Ex-SIR MIR FIR SIR 4 ICR1 Ex-SIR MIR FIR SIR 5 ICR2 Ex-SIR MIR FIR 6 7 8 9 A B C F MSR DSR FCR TFL (L) TCC (L) TFL (H) TCC (H) MDS (L) RST (L) MDS (H) RST (H) TEST all all all all all all all all all all all all R/W R/W R/W R/W R R/W R R/W R R/W R R/W DRS2 * RXTH3 TFL7 TCC7 * * MDS7 RST7 * * TEST7 DRS1 * RXTH2 TFL6 TCC6 * * MDS6 RST6 * * TEST6 DRS0 * RXTH1 TFL5 TCC5 * * MDS5 RST5 * * TEST5 XT_SL * RXTH0 TFL4 TCC4 * * MDS4 RST4 * * TEST4 R/W CTEST SD_INV IRIN _SL RXINV R/W MS_EN TCC_EN * CRC_ INV FCLR IR_PLS * SBF3 MBF3 * * * TXTH3 TFL3 TCC3 TFL11 TCC11 MDS3 RST3 MDS11 RST11 TEST3 * * S_EOT * SBF2 MBF2 * * DMA_ SL1 TXTH2 TFL2 TCC2 TFL10 TCC10 MDS2 RST2 MDS10 RST10 TEST2 RX_EN TX_EN R FLV5 FLV4 FLV3 FLV2 FLV1 FLV0 IR_DET TOUT R TXE_EV TXL_EV RXH/T _EV EOF_EV * MLE_EV * CE_EV OE_EV R/W TXE_IE TXL_IE RXH/T _IE EOF_IE R/W Function of each bit Bit7 TDR7 /RDR7 Bit6 TDR6 /RDR6 Bit5 TDR5 /RDR5 Bit4 TDR4 /RDR4 * MLE_IE Bit3 TDR3 /RDR3 Bit2 TDR2 /RDR2 * CE_IE OE_IE Bit1 TDR1 /RDR1 Bit0 TDR0 /RDR0 FE_IE AS_IE ECE_IE FE_EV AS_EV ECE_EV
* SBF1 MBF1 * IRSL1 DMA_ SL0 TXTH1 TFL1 TCC1 TFL9 TCC9 MDS1 RST1 MDS9 RST9 TEST1
* SBF0 MBF0 * IRSL0 DMA_ EN TXTH0 TFL0 TCC0 TFL8 TCC8 MDS0 RST0 MDS8 RST8 TEST0
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Semiconductor Registers * TDR: Transmit Data Register (Write Only) RDR: Receive Data Register (Read Only) (Address = 0h)
MSM9405
The TDR (Transmit Data Register) and RDR (Receive Data Register) are used to read/write data directly upon receiving/sending the data. The TDR and RDR share the same address. When data is written in the sending mode or during the idle state, the TDR works as the top of the FIFO and 1-byte data can be written to the FIFO. When data is read in the receiving mode, the RDR works as the bottom of the FIFO and 1-byte data in the FIFO can be read. Serial-to-parallel conversion is performed by the RSR. Parallel-to-serial conversion is performed by the TSR. Reading from the TDR or writing to the RDR is invalid. The contents of the FIFO and TDR/RDR are cleard by writing "1" to FCLR in the ICR1 register. The TSR and RSR cannot be cleared. * ENR: Enable Register (Address = 1h) The ENR (Enable Register) is used to control enabling/disabling various interrupts on the MSM9405. Each of eight bits corresponds to each of eight interrupts provided on the MSM9405. Each of eight interrupts can be independently controlled by each bit. When the system is reset, all bits are reset to "0". By writing "1" to the bit corresponding to the desired interrupt, the specified interrupt is enabled.
ENR 7
ENR 6
ENR 5
ENR 4
ENR 3
ENR 2
ENR 1
ENR 0 FE_IE (Enable = "1") AS_IE (Enable = "1") ECE_IE (Enable = "1") OE_IE (Enable = "1") CE_IE (Enable = "1") MLE_IE (Enable = "1") EOF_IE (Enable = "1") RXH/T_IE (Enable = "1") TXL_IE (Enable = "1") TXE_IE (Enable = "1")
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Semiconductor
MSM9405
ENR bit mode.
Table bit This bit works as FE_IE in SIR or Extended-SIR mode, as AS_IE in MIR mode, and as ECE_IE in FIR - FE_IE (Framing Error Interrupt Enable) (SIR mode/Extended-SIR mode): This bit enables/disables
ENR[0]
interrupt when an FE (Framing Error : Stop bit not detected) has occurred. - AS_IE (Abort Sequence Interrupt Enable) (MIR mode): This bit enables/disables interrupt when an abort sequence has been received. - ECE_IE (Encode Error Interrupt Enable) (FIR mode): This bit enables/disables interrupt when an encode error has occurred. OE_IE (Overrun Error Interrupt Enable) : This bit enables/disables interrupt when an OE (Overrun
ENR[1]
error : Error that occurs when the FIFO is full upon receiving and the next character is completely received by the RSR) has occurred. CE_IE (CRC Error Interrupt Enable) : This bit enables/disables interrupt when a CE (CRC Error) has
ENR[2]
occurred. This bit is valid in either Extended-SIR, MIR, or FIR mode. In SIR mode, this bit must be set to "0" (disable). MLE_IE (Maximum Length Error Interrupt Enable) : This bit enables/disables interrupt when an MLE
ENR[3]
(Maximum Length Error: Error that occurs when a frame exceeding the maximum data size set by the MDS is received) has occurred. EOF_IE (End Of Frame Interrupt Enable) : This bit enables/disables interrupt when the last byte in
ENR[4]
the frame's data field has been detected in either Extended-SIR, MIR, or FIR mode. In SIR mode, this bit must be set to "0" (disable). RXH/T_IE (Receiver High-Data-Level/Timeout Interrupt Enable) : This bit enables/disables interrupt when the received data is at or above the receiving threshold level or time-out has occurred. TXL_IE (Transmitter Low-Data-Level Interrupt Enable) : This bit enables/disables interrupt when the sent data is below the sending threshold level. TXE_IE (Transmitter Empty Interrupt Enable) : This bit enables/disables interrupt when both the FIFO and the TSR have become empty upon sending.
ENR[5] ENR[6] ENR[7]
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Semiconductor
MSM9405
* EIR: Event Identification Register (Read Only) (Address = 2h) The EIR (Event Identification Register) indicates factors of various interrupts on the MSM9405. Each of eight bits corresponds to each interrupt bit assignment set on the ENR. The EIR works as the status register even if the interrupt is disabled. When an event occurs, each corresponding bit is set to "1". When the system is reset, all bits are reset to "0".
EIR 7
EIR 6
EIR 5
EIR 4
EIR 3
EIR 2
EIR 1
EIR 0 FE_EV (Framing Error = "1") AS_EV (Abort Sequence = "1") ECE_EV (Encode Error = "1") OE_EV (Overrun Error = "1") CE_EV (CRC Error = "1") MLE_EV (Maximum Length = "1") EOF_EV (EOF = "1") RXH/T_EV (RX High-Data-Level/Timeout = "1") TXL_EV (TX Low-Data-Level = "1") TXE_EV (TX Empty = "1")
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Semiconductor
MSM9405
EIR bit
Description This bit works as FE_EV in SIR or Extended-SIR mode, as AS_EV in MIR mode, and as ECE_EV in FIR mode. When the CPU reads the EIR contents, this bit is set to "0".
EIR[0]
- FE_EV (Framing Error Event) (SIR mode/Extended-SIR mode): The bit is set to "1" when FE occurs. - AS_EV (Abort Sequence Event) (MIR mode): The bit is set to "1" when an abort sequence is received. - ECE_EV (Encode Error Event) (FIR mode): The bit is set to "1" when ECE occurs. OE_EV (Overrun Error Event): When OE occurs, this bit is set to "1". When the CPU reads the EIR contents, OE_EV is set to "0". The RSR characters are not transferred to the FIFO but overwritten. CE_EV (CRC Error Event): When a CRC error occurs, this bit is set to "1". When the CPU reads the EIR, this bit is set to "0". This bit is valid in either Extended-SIR, MIR, or FIR mode. This bit is not used in SIR mode. MLE_EV (Maximum Length Error Event): When MLE occurs, this bit is set to "1". When the CPU reads the EIR, this bit is set to "0". EOF_EV (End Of Frame Event): This bit is valid in either Extended-SIR, MIR, or FIR mode. When the last byte in the frame's data field reaches the bottom of the FIFO in receiving mode, EOF_EV is set to "1". When the CPU reads the EIR, this bit is set to "0". In SIR mode, this bit is not used. RXH/T_EV (Receiver High-Data-Level/Timeout Event): When received data in the FIFO is at or above the receiving threshold level or time-out occurs, RXH/T_EV is set to "1". The condition for setting RXH/T_EV to "0" depends on the following two cases :
EIR[1]
EIR[2]
EIR[3]
EIR[4]
EIR[5]
If received data in the FIFO is at or above the receiving threshold level : Received data is read. When received data in the FIFO is below the threshold level, this bit is set to "0". If time-out occurs : After received data in the FIFO is read, this bit is set to "0". TXL_EV (Transmitter Low-Data-Level Event): When sent data in the FIFO is below the sending
EIR[6]
threshold level, this bit is set to "1". When sent data is written and sent data in the FIFO is at or above the threshold level, this bit is set to "0". TXE_EV (Transmitter Empty Event): When both FIFO and TSR are empty in sending mode, this bit is set to "1". When the CPU reads the EIR, this bit is set to "0".
EIR[7]
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Semiconductor * LSR: Line Status Register (Read Only) (Address = 3h)
MSM9405
The LSR (Line Status Register) indicates various statuses of the MSM9405 that is running. When the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be written.
LSR 7
LSR 6
LSR 5
LSR 4
LSR 3
LSR 2
LSR 1
LSR 0 TOUT (Timeout = "1") IR_DET (SIR Pulse detect = "1") FLV (Byte number in FIFO)
LSR bit LSR[0] LSR[1] LSR[2-7]
Description TOUT (FIFO Timeout): When time-out occurs in the FIFO during receiving, this bit is set to "1". When received data is read from the FIFO, TOUT is set to "0". IR_DET (SIR Pulse detect) : This bit is set to "1" when a pulse having a width of tspw (SIR pulse width upon receiving). It is set to "0" when the CPU reads the LSR. FLV (FIFO Level): These bits indicate the number of data items in the FIFO with a value of 0 to 32.
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Semiconductor * ICR1: Infrared Control Register 1 (Address = 4h)
MSM9405
The ICR1 (Infrared Control Register 1) is used to set various environment so that the MSM9405 can perform IrDA communication under proper conditions. When the system is reset, all bits of ICR1 are set to "0".
ICR1 7
ICR1 6
ICR1 5
ICR1 4
ICR1 3
ICR1 2
ICR1 1
ICR1 0 TX_EN ("1": Transmit Enable) RX_EN ("1": Receive Enable) S_EOT ("1": Set End Of Transmission) IR_PLS ("1": Send Interaction Pulse) FCLR ("1": FIFO Clear) CRC_INV ("1": Send Inverted CRC Enable) TCC_EN ("0": TCC off, "1": TCC on) MS_EN ("1": Automatic mode Select)
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Semiconductor
MSM9405
ICR1 bit ICR1[0]
Description TX_EN (Transmit Enable): When "1" is written to this bit, the sending mode is selected. When "0" is written to this bit, sending terminates when data remaining in the FIFO has all been sent. In this case, the TXE interrupt does not occur. RX_EN (Receive Enable): When "1" is written to this bit, the receiving mode is selected. When "0" is written to this bit, the device enters receive end mode. S_EOT (Set End Of Transmission): This bit is valid in Extended-SIR, MIR, or FIR mode. When "1" is written to this bit, the data written to the FIFO next time is recognized as the end of frame, and
ICR1[1]
ICR1[2]
immediately after it, the data added with CRC and EOF is sent as a frame. After a frame is sent, this bit is automatically set to "0". To use S_EOT, TFL must be set to the maximum value or TCC must be unused with TCC_EN = "0". This bit is not used in SIR mode. IR_PLS (Send Interaction Pulse): This bit is valid in MIR or FIR mode. When "1" is written to this bit, an approximately 2-ms serial infrared interaction pulse is sent immediately after the frame being sent. After a frame is sent, this bit is automatically set to "0". This bit is not used in SIR mode and Extended-SIR mode. FCLR (FIFO Clear): When "1" is written to this bit, the FIFO (including the TDR and RDR) is made
ICR1[3]
ICR1[4]
empty. The FIFO threshold level does not change. The TSR and RSR are not cleared. When the FIFO is made empty, this bit is automatically set to "0". CRC_INV (Invert Transmitter CRC): This bit is valid in Extended-SIR, MIR, or FIR mode and is not used in SIR mode. When "1" is written to this bit, transmission is interrupted if TXE (Transmitter Empty) occurs. The inverted CRC and EOF are automatically added to the frame that caused TXE, then the frame is sent. Writing "0" to this bit disables this function. TCC_EN (TCC Enable): This bit is valid in Extended-SIR, MIR, or FIR mode. When this bit is set to
ICR1[5]
ICR1[6]
"1", the TCC is enabled. When TCC_EN is set to "0", the TCC is disabled. To use S_EOT, the TFL must be set to the maximum value or the TCC must be disabled with TCC_EN = "0". MS_EN (Mode Select Enable): When "1" is written to this bit, the MSM9405 performs the following operation depending on the mode. After the operation is completed, this bit is automatically set to "0". If the MSM9405 is in FIR mode: 1. The SD pin is set to "H", and the Tx pin to "H".
ICR1[7]
2. Approximately 300 ns later, the SD pin is set to "L". 3. Approximately 300 ns later, the Tx pin is set to "L". If the MSM9405 is in SIR, Extended-SIR, or MIR mode: 1. The SD pin is set to "H", and the Tx pin to "L". 2. Approximately 300 ns later, the SD pin is set to "L". 3. The Tx pin is held in the "L" level for approximately 300 ns.
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Semiconductor * ICR2: Infrared Control Register 2 (Address = 5h)
MSM9405
The ICR2 (Infrared Control Register 2) is used to set various environment so that the MSM9405 can perform IrDA communication under proper conditions. When the system is reset, all bits of ICR2 are set to "0".
ICR2 7
ICR2 6
ICR2 5
ICR2 4
ICR2 3
ICR2 2
ICR2 1
ICR2 0 SBF (SIR Beginning Flags) MBF (MIR Beginning Flags) RXINV ("1": Signal Invert) IRIN_SL ("0": Single Input "1": Double Input) SD_INV ("0": SD Active High "1": SD Active Low) CTEST ("0": TCC/RST "1": TFL/MDS)
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Semiconductor
MSM9405
IRC2 bit
Description These bits work as the SBF when Extended-SIR mode is selected, and as the MBF when the MIR mode is selected. This function is disabled in SIR mode and FIR mode. SBF (SIR beginning Flags): These bits determine the number of BOFs to be added during sending in Extended-SIR mode as shown below. MBF (MIR Beginning Flags): These bits determine the number of BOFs to be added during sending in MIR mode as shown below. Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIR BOFs 1 2 3 4 5 7 9 13 17 25 49 49 49 49 49 49 MIR BOFs 2 3 4 5 8 12 16 24 24 24 24 24 24 24 24 24
ICR2[0-3]
RXINV (IRIN Signal Invert): This bit is used to select active low or active high of the receive signal. ICR2[4] RXINV = "0": Active low RXINV = "1": Active high IRIN_SL (IRIN Select): This bit determines how the receive signal input pin is used. ICR2[5] IRIN_SL = "0": Only the input from the IRIN-A pin (2.4 kbps to 4 Mbps) is accepted. IRIN_SL = "1": An input from IRIN-A or IRIN-B is automatically selected depending on the transfer rate. (A: 2.4 to 115.2 kbps, B: 0.576 to 4 Mbps) SD_INV (SD Signal Invert): This bit changes the polarity (active high/low) of the SD pin output on ICR2[6] the MSM9405. SD_INV = "0": Active high ("H" output during shutdown) SD_INV = "1": Active low ("L" output during shutdown) ICR2[7] CTEST (Counter Test): Normally this bit is set to "0". When TFL/TCC and MDS/RCC are read after "1" is written to this bit, the TFL and MDS values can be obtained.
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Semiconductor * MSR: Mode Select Register (Address = 6h)
MSM9405
The MSR is used to select various modes of the MSM9405. When the system is reset, each bit is set to the initial value.
MSR 7
MSR 6
MSR 5
MSR 4
MSR 3
MSR 2
MSR 1
MSR 0 IRSL0 (IrDA mode Select 0) IRSL1 (IrDA mode Select 1) Not Used XT_SL ("0": 48 MHz "1": 18.432 MHz) DRS (Data Rate Select)
MSR Bit The initial value is set to "00". IRSL1 MSR[0-1] 0 0 1 1 MSR[2-3] These bits are not used. IRSL0 0 1 0 1
Description IRSL (Infrared Mode Select): These bits are used to select the transfer mode as shown below. mode SIR Extended-SIR MIR FIR
XT_SL (Crystal Select): This bit determines the crystal to be used. MSR[4] The initial value is set to "0". XT_SL = "0": 48 MHz crystal is used XT_SL = "1": 18.432 MHz crystal is used DRS (Data Rate Select): These bits determine the transfer rate as shown below. The initial value is set to "001". Encoding 000 001 MSR[5-7] 010 011 100 101 110 111 SIR Data Rate 2400 bps 9600 bps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps reserved reserved MIR Data Rate 0.576 Mbps 1.152 Mbps reserved reserved reserved reserved reserved reserved FIR Data Rate reserved 4 Mbps reserved reserved reserved reserved reserved reserved
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Semiconductor * DSR: DMA Mode Select Register (Address = 7h)
MSM9405
The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When the system is reset, all bits of DSR are set to "0".
DSR 7 DSR 6 DSR 5 DSR 4 DSR 3 DSR 2 DSR 1 DSR 0 DMA_EN ("1": DMA mode) DMA_SL0 (DMA Select 0) DMA_SL1 (DMA Select 1) Not Used
DSR Bit is set to "0". When "1" is written to this bit, DSR[1-2] (DMA_SL0, DMA_SL1) setting is enabled and the DSR[0] MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert condition is met.) If DMA_EN = "0", DSR[1-2] (DMA_SL0, DMA_SL1) setting is disabled and DMA transfer is not performed. (DREQ is not asserted even if the DREQ assert condition is met.) DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC. DMA_SL1 0 DMA_SL0 0 Function DREQ becomes active low and DACK becomes active high. When the RD signal becomes active while DACK is active, the DMA read cycle (MemoryAEM9405) is selected. When the WR signal becomes active while DACK is active, the DMA write cycle (M9405AEMemory) is selected. While DACK is being asserted, address "0" (TDR/RDR) is accessed regardless of the status of A0 to A3. DSR[1-2] 0 1 DREQ becomes active high and DACK becomes active low. When the WR signal becomes active while DACK is active, the DMA read cycle (MemoryAEM9405) is selected. When the RD signal becomes active while DACK is active, the DMA write cycle (M9405AEMemory) is selected. While DACK is being asserted, address "0" (TDR/RDR) is accessed regardless of the status of A0 to A3. 1 1 0 1 DREQ becomes active low and DACK becomes active high. DACK is disabled. DREQ becomes active high and DACK becomes active low. DACK is disabled. DSR[3-7] These bits are not used. Description DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value
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Semiconductor FCR : FIFO Control Register (Address = 8h)
MSM9405
The FCR (FIFO Control Register) is used to set the threshold level of the FIFO to be used by the MSM9405 upon sending/receiving. The FCR setting is applied to both interrupt and DMA. When the system is reset, the FCR is set to the initial value.
FCR 7 FCR 6 FCR 5 FCR 4 FCR 3 FCR 2 FCR 1 FCR 0 TXTH (TX Threshold Select) RXTH (RX Threshold Select)
FCR bit The initial value is set to "0111". FCR (0-3) 0000 0001 0010 0011 0100 0101 FCR[0-3] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Description TXTH (Transmit Threshold Select): These four bits set the following 16 sending threshold levels. TX Threshold Level (Byte) 01 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30
RXTH (Receive Threshold Select): These four bits set the following 16 receiving threshold levels. FCR[4-7] The relationship between the FCR (4-7) value and receiveing threshold level is the same as the relationship between the FCR (0-3) and sending threshold level. The initial value is set to "0111".
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Semiconductor TFL : (Transmitter Frame Length Register TCC : Transmitter Current-Count Register (Address = 9, Ah)
MSM9405
The TFL (Transmitter Frame Length) and TCC (Transmitter Current-Count Register) are used to specify the length of the frame to be transferred for sending. The TFL and TCC shares the same address. Bits 0 to 7 of address 9h and bits 0 to 3 of address Ah (totally 12 bits) are used. Bit 0 of address 9h is the LSB. When the TFL/TCC value is read, the CTEST setting is reflected. If CTEST = "0", the TCC contents can be read. If CTEST = "1", the TFL contents can be read. When the TFL/TCC is written, the TFL value is rewritten. The TCC cannot be written. To use the TFL/TCC, write "1" to TCC_EN, and set the frame length in the TFL. The frame length to be set does not include the CE, FCS, BOF, and EOF. When "1" is written to TX_EN, the TFL value that has been set as the frame length is loaded to the TCC. When sending is started, the TCC value is decremented by 1 each time 1 byte is sent. When the TCC value becomes "0", the end of frame is assumed and the frame is automatically added with the CRC and EOF and sent. After one frame is sent, the TFL value is loaded again into the TCC when the BOF of the second frame is sent. The TFL/TCC initial value is set to 800h. MDS : Maximum Data Size Register RST : Receiver Frame Length Stack Register (Address = B, Ch) The MDS (Maximum Data Size Register) is used to set the maximum data size. The RST (Receiver Frame Length Stack Register) is used to stack the received frame length. The MDS and RST share the same address. Bits 0 to 7 of address Bh and bits 0 to 3 of address Ch (totally 12 bits) are used. Bit 0 of address Bh is the LSB. When the MDS/RST value is read, the CTEST setting is reflected. If CTEST = "0", the RST contents can be read. If CTEST = "1", the MDS contents can be read. When the MDS/RST is written, the MDS value is rewritten. The RST cannot be written. To use the MDS, set the maximum data size in the MDS in advance. The frame length to be set does not include the CE, FCS, BOF, and EOF in the Extended-SIR, MIR, and FIR modes. (However, it does include them in the SIR mode.) When receiving is started, the internal counter value is incremented by 1 each time one byte is received. If the internal counter value exceeds the MDS value during receiving, MLE occurs. The MDS initial value is set to 800h. When a frame is fully received and all the data in the received frame is taken out of the FIFO, the received frame length counted by the internal counter is stacked in the RST. This value is stored untill the next frame is fully received. The value stacked in the RST is maintained even if MSM9405 sending/receiving is switched. The RST initial value is set to 0h. TEST : Test Register (Address = Fh) This register is used for testing.
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Semiconductor
MSM9405
APPLICATION CIRCUIT
D0-D7 A0-A3 CS
Microcontroller
IRIN-A IRIN-B IROUT
RXD-A (RXD-B) TXD Infrared Transceiver Module
RD WR TC INTR DREQ DACK RESET PWDN XIN XOUT
MSM9405
SD
SD
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Semiconductor
MSM9405
PACKAGE OUTLINES AND DIMENSIONS
(Unit : mm)
Mirror finish
30-Pin Plastic SSOP
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