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| 0.35 m CMOS ON33 ON33 is an OR / NAND circuit providing the logical function Q = NOT [ (A+B+C).(D+E+F) ]. Truth Table A 0 X X X X X X X 1 1 1 B 0 X X X X 1 1 1 X X X C 0 X 1 1 1 X X X X X X D X 0 X X 1 X X 1 X X 1 E X 0 X 1 X X 1 X X 1 X F X 0 1 X X 1 X X 1 X X Q 1 1 0 0 0 0 0 0 0 0 0 Capacitance Pin A B C D E F Cap [pF] 0.018 0.018 0.018 0.017 0.016 0.015 Area 0.226 mils 2 146 m 2 Power 1.234 W/MHz Delay [ns] = tpd.. = f(SL, L) Output Slope [ns] = op_sl.. = f(SL, L) AC Characteristics: Tj = 25C with SL = Input Slope [ns] ; L = Output Load [pF] with L = Output Load [pF] Typical Process VDD = 3.3V AC Characteristics Rise Slope [ns] Load [pF] Delay A => Q Delay B => Q Delay C => Q Delay D => Q Delay E => Q Delay F => Q Slew A => Q Slew B => Q Slew C => Q Slew D => Q Slew E => Q Slew F => Q 0.1 0.015 0.29 0.27 0.21 0.23 0.21 0.14 1.09 1.09 1.08 0.99 0.99 0.97 0.15 0.75 0.72 0.66 0.69 0.67 0.61 2.55 2.54 2.54 2.44 2.44 2.45 0.015 0.33 0.39 0.43 0.23 0.3 0.34 1.46 1.51 1.53 1.35 1.41 1.43 2 0.15 0.76 0.84 0.89 0.7 0.77 0.82 2.72 2.75 2.79 2.61 2.65 2.68 0.015 0.38 0.34 0.28 0.36 0.32 0.26 0.64 0.54 0.46 0.65 0.55 0.45 0.1 0.15 0.79 0.74 0.69 0.77 0.72 0.66 1.56 1.46 1.37 1.56 1.47 1.36 0.015 0.6 0.55 0.47 0.71 0.65 0.56 1.01 0.89 0.79 1.1 0.98 0.84 Fall 2 0.15 1.01 0.97 0.91 1.14 1.1 1.04 1.78 1.68 1.58 1.87 1.77 1.67 April 2000 Page 1 of 1 Rev. N/C |
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