 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NT511740D5J 16MEG : x4 CMOS with Extended Data Out NT511740D5J DATA SHEET REV 1.0 May. 2000 1 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Contents Table of Contents.........................................................................................................................................................02 Description ...................................................................................................................................................................03 Features........................................................................................................................................................................03 Product Family ............................................................................................................................................................03 Pin Assignment............................................................................................................................................................04 Electrical Characteristics ............................................................................................................................................05 Absolute Maximum Ratings ......................................................................................................................................05 Recommended DC Operating Conditions .....................................................................................................................05 Capacitance ..........................................................................................................................................................05 DC Electrical Characteristics .....................................................................................................................................06 AC Characteristics .......................................................................................................................................................07 Timing Waveform.........................................................................................................................................................10 Read Cycle ...........................................................................................................................................................10 Write Cycle ...........................................................................................................................................................10 Read Modify Write Cycle ..........................................................................................................................................11 Fast Page Mode Read Cycle .....................................................................................................................................11 Fast Page Mode Write Cycle .....................................................................................................................................12 Fast Page Mode Read Modify Write Cycle ....................................................................................................................13 RAS -only Refresh Cycle ........................................................................................................................................13 CAS -before- RAS refresh ..................................................................................................................................14 Hidden Refresh Read..........................................................................................................................................15 Package Dimension .....................................................................................................................................................16 REV 1.0 May. 2000 2 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V ), refresh cycle (2K Ref), access time (-5 or -6), power consumption (Normal or Low power) and package type (SOJ) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 EDO Mode DRAM family is fabricated using NANYA's advanced CMOS process to realize high bandwidth, low power consumption and high reliability. It may be used as main memory unit for microcomputer, high level computer and personal computer . FEATURES * * * * * * * * * Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) TTL(5V) compatible inputs and outputs Single +5V 10% power supply (5V product) JEDEC Standard pinout CAS before RAS refresh, hidden refresh, RAS -only refresh capability Refresh : 2048 cycles / 32 ms Self-refresh capability (L-ver only) Multi-bit test mode capability Available in plastic SOJ packages PRODUCT FAMILY Family NT511740D5J - 50/5L NT511740D5J - 60/6L Access Time (Max.) tRAC 50ns 60ns tCAC 15ns 17ns tRC 84ns 104ns tHPC 20ns 25ns Active Power Dissipation 605mW 550mW Voltage 5V Package 26(24)-pin SOJ REV 1.0 May. 2000 3 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out PIN CONFIGURATION (TOP VIEW) NT511740D5J VCC DQ0 DQ1 W RAS NC 1 2 3 4 5 6 24 23 22 21 20 19 Vss DQ3 DQ2 CAS OE A9 A10 A0 A1 A2 A3 Vcc 7 8 9 10 11 12 18 17 16 15 14 13 A8 A7 A6 A5 A4 Vss 300mil 26(24)-pin SOJ Pin Name A0-A10 DQ0-DQ3 Vss RAS CAS W OE VCC NC Pin Function Address Inputs Data Input / Output Ground Row Address Strob Column Address Strob Read/Write Input Data Output Enable Power +5.0 V ( + 3.3V ) No Connection REV 1.0 May. 2000 4 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operation Temperature Symbol VIN,VOUT VCC IOS PD* Topr Rating -1.0 to +7.0 -1.0 to +7.0 50 1 0 to 70 Unit V V mA W C Storage Temperature Tstg -55 to 150 C *:Ta = 25C * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Voltage referenced to Vss, Ta = 0C to 70C ) Parameter Supply Voltage Ground Input High Voltage Symbol VCC VSS VIH Min. 4.5 0 2.4 -1.0 *2 Typ. 5.0 0 - Max. 5.5 0 Vcc+1.0 0.8 *1 Unit V V V V Input Low Voltage VIL *1 : Vcc +2.0V/20ns(5V), Pulse width is measured at Vcc *2 : -2.0V/20ns(5V), Pulse width is measured at Vss Capacitance ( Vcc = 5V, Ta = 25C, f = 1 MHZ ) Parameter Input Capacitance (A0-A11) Input Capacitance ( RAS , CAS , WE , OE Output Capacitance (DQ0-DQ3) ) Symbol CIN1 CIN2 CI/O Typ. Max. 5 7 7 Unit pF pF pF DC Characteristics (Recommended operating conditions unless otherwise noted.) Max Parameter Input Leakage Current (Any input 0 <= VIN <= VIN+0.5V, all other input pins not under test =0 Volt) 5V Output Leakage Current (Data out is disabled, 0 <= VOUT <= VCC) Output High Voltage Level (IOH= -5mA) Output Low Voltage Level (IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V REV 1.0 May. 2000 5 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out DC CHARACTERISTICS ( Continued ) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCS Power Don't care Normal L Don't care Don't care Normal L Don't care L L Speed -5 -6 Don't care -5 -6 -5 -6 Don't care -5 -6 Don't care Don't care Max 110 100 2 1 110 100 90 80 3 200 110 100 300 250 Units mA mA mA mA mA mA mA mA mA uA mA mA uA uA ICC1* : Operating Current ( RAS and CAS cycling @ t RC=min.) ICC2 : Standby Current ( RAS = CAS = W =VIH) ICC3* : RAS -only Refresh Current ( RAS =VIH, RAS cycling @ t RC=min.) ICC4* : Hyper Page Mode Current ( RAS =VIL, CAS Address cycling @ t HPC=min.) ICC5 : Standby Current ( RAS = CAS = W =VCC-0.2V) ICC6* : CAS-Before- RAS Refresh Current ( RAS , CAS cycling @ t RC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage (VIH)=VCC-0.2V, Input low voltage (VIL)=0.2V, CAS =0.2V, DQ=Don't care, t RC=125us(2K/L-ver) , t RAS=tRASmin~300ns ICCS : Self Refresh Current ( RAS = CAS =0.2V, W = OE =A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or open ) *Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS =VIL. In ICC4, address can be changed maximum once within one hyper page mode cycle time, t HPC. REV 1.0 May. 2000 6 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out AC CHARACTERISTICS (0C <= Ta <= 70C , See note 1,2) ; Test condition : VCC=5.0V 10%, VIH/VIL=2.4/0.8V, VOH/VOL=2.0/0.8V -50 Min 84 110 50 13 25 0 0 0 1 30 50 7 35 7 11 9 5 0 7 0 7 25 0 0 0 7 7 7 7 0 7 32 128 0 0 0 0 0 1 40 60 10 40 10 14 12 5 0 10 0 10 30 0 0 0 10 10 10 10 0 10 32 128 Max Min 104 135 60 15 30 -60 Max - Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (L-ver) Write command set-up time Symbol t RC t RWC t RAC t CAC t AA t CLZ t CEZ t OLZ tT t RP t RAS t RSH t CSH t CAS t RCD t RAD t CRP t ASR t RAH t ASC t CAH t RAL t RCS t RCH t RRH t WCH t WP t RWL t CWL t DS t DH t REF t REF t WCS Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns Notes 3,4,10 3,4,5 3,10 3 6,14 3 2 4 10 8 8 9 9 7 REV 1.0 May. 2000 7 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out AC CHARACTERISTICS Parameter CAS to W delay time RAS to W delay time (Continued ) Symbol t CWD t RWD t AWD t CPWD t CSR t CHR t RPC t CPA t HPC t HPRWC t CP t RASP t RHCP t OEA t OED t OEZ t OEH t WTS t WTH t WRP t WRH t DOH t REZ t WEZ t WED t OCH t CHO t OEP t WPE t RASS t RPS t CHS 12 3 7 7 10 10 10 5 0 0 10 5 5 7 7 100 90 -50 20 47 7 50 30 13 15 3 10 10 10 10 10 5 0 0 10 5 5 10 10 100 110 -50 100k -50 Min 30 67 42 47 5 10 5 28 25 56 10 60 35 15 100k Max Min 34 79 49 54 5 10 5 35 -60 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15,16,17 15,16,17 15,16,17 6,14 6 11 11 6 3 13 13 Notes 7 7 7 Column address to W delay time CAS precharge to W delay time CAS set-up time ( CAS -before- RAS refresh) CAS hold time ( CAS -before- RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper Page cycle) RAS pulse width (Hyper Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) REV 1.0 May. 2000 8 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh Cycles before proper device operation is achieved. 2. VIH(min) and VlL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the t RCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD >= tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS >= t WCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If t CWD >= t CWD(min), t RWD >= t RWD(min) and tAWD >= tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled Write Cycle and read-modify-write cycles. 9. Operation within the tRAD (max) limit insures that tRAD(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA . 10. These specifications are applied in the test mode. 11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These Parameters should specified in test mode cycles by adding the above value to the specified value in this data sheet. 12. tASC>= 6ns, Assume t T = 2.0ns 13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 14. If tRASS>= 100us, then RAS precharge time must use tRPS instead of tRP. 15. For RAS-only refresh and burst CAS -before- RAS refresh mode, 2048(2K) cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification.. 16. For distributed CAS -before- RAS with 15.6us interval CAS -before- RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. REV 1.0 May. 2000 9 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out TIMING WAVEFORM Read Cycle RAS V IH VIL tCRP tRCD tRAD tRAL tASR tRAH tASC tCAH tRAS tRC tRP tCRP tCSH tRSH tCAS CAS V IH VIL Address V IH VIL Row tRCS Column tRCH tRRH tAA tROH tOEA tREZ WE V IH VIL OE V IH VIL tCAC tRAC tOEZ tCEZ DQ V IH VIL Open tCLZ Valid Data-out "H" or "L" Write Cycle(Early Write) RAS VIH VIL tCRP tRCD tRAS tRC tRP tCRP tCSH tRSH tCAS tRAD tRAL CAS VIH VIL tASR tRAH tASC tCAH Address VIH VIL Row tWCS Column tCWL tWCH tWP WE VIH V IL tRWL OE VIH VIL tDS tDH Valid data-in DQ VIH VIL Open "H" or "L" REV 1.0 May. 2000 10 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Read Modify Write Cycle RAS VIH VIL tCRP tRCD tCAS tRAS tCRP tCSH tRSH tRWC tRP CAS VIH VIL tASR tRAH tASC tCAH Address VIH VIL Row tRAD Column tCWD tRWD tCWL tRWL tWP tAWD tRCS tOEA tOED tCAC tRAC tOEZ Valid Data-out tDS tDH Valid Data-in tOEH WE VIH VIL tAA OE VIH VIL DQ VIH VIL tCLZ "H" or "L" Fast Page Mode Read Cycle (Part-1) t RASP tR P RAS VIH VIL tHPC tCRP tRCD t CAS tRAD t CSH tASR tRAH tASC tCAH tASC tCAH tASC t CP tCAS tCP t RHCP CAS VIH VIL tCAS tCAH Address VIH VIL Row Column Column Column t RCS t RRH tCHO tOCH WE VIH VIL tRAC tAA tOEP tAA tOEP OE VIH VIL tOEA tCAC tCPA tCAC tDOH Valid Data-out Valid Data-out tAA tOEA tOEZ tCAC tOEZ Valid Data-out tOEA tREZ Valid Data-out DQ VIH VIL tCLZ "H" or "L" REV 1.0 May. 2000 11 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Fast Page Mode Read Cycle(Part-2) tRASP tRP tRHCP tCRP tHPC tCRP tRCD tCAS tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAH tC P tCAS tC P tCAS RAS VIH VIL CAS VIH VIL Address VIH VIL Row Column Column Column tRCS tRCS tRCH t RAC tAA tWPE tAA tAA tCPA tOEA tCAC tWEZ Valid Data-out tCAC Valid Data-out tCAC tDO H WE VIH VIL OE VIH VIL tCEZ Valid Data-out DQ VIH VIL tCLZ "H" or "L" Fast page Mode Write Cycle(Early Write) tRASP tRP RAS V IH VIL tHPC tCRP tRCD tCAS tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRSH tCP tCAS tCP tCAS tHPC CAS VIH VIL Address VIH VIL Row Column Column Column WE VIH VIL tWCS tWCH tWCS tWCH tWCS tWCH OE VIH VIL tDS tDH Valid Data-in tDS tDH tDS tDH DQ VIH VIL Valid Data-in Valid Data-in "H" or "L" REV 1.0 May. 2000 12 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Fast Page Mode Read Modify Write Cycle tRASP RAS VIH VIL tCRP tRCD tRWD tCP tCWD CAS VIH VIL tRAD tHPRWC tASR tRAH tASC tCAH Column tAWD t RCS tCWL tASC tCPA tCAH t CPWD tRWL Address VIH VIL Row Column tRCS tCWD WE VIH VIL t RAC tAA tAWD tDS tWP t AA tOEH tOEA tOED tCAC tOEZ Valid Data-out Valid Data-in tD S t WP OE VIH VIL tOEH tOEA tOED t DH tCAC tOEZ Valid Data-out t DH Valid Data-in DQ VIH VIL tCLZ tCLZ "H" or "L" RAS-only Refresh Cycle RAS V IH VIL tCRP tRAS t RC t RP tRPC CAS V IH VIL tASR tRAH Address V IH VIL tCEZ Row DQ IH V VIL Open Note:WE,OE="H" or "L" "H" or "L" REV 1.0 May. 2000 13 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out CAS before RAS Refresh Cycle tRP tRC tRAS t RP RAS VIH VIL tRPC t CP tCSR tCHR tRPC CAS VIH VIL tWR P tWRH tWRP WE VIH VIL tCEZ DQ VIH VIL Open Note:OE,Address="H" or "L" "H" or "L" Hidden Refresh Read Cycle t RAS tRC tR P tRAS tRC tRP RAS VIH VIL tCRP t RCD tRAD tRAH t ASR tASC t CAH t RSH tCHR CAS VIH VIL Address VIH VIL Row tRCS Column t RAL tRRH WE VIH VIL tAA tROH OE VIH VIL t CLZ tRAC tOEA tCAC tCEZ t REZ t OEZ DQ VIH VIL Open Valid Data-out "H" or "L" REV 1.0 May. 2000 14 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out Hidden Refresh Write Cycle t RAS tRC tR P tRAS tRC tRP RAS VIH VIL tCRP t RCD tRAD tRAH t ASR tASC t CAH t RAL t RSH tCHR CAS VIH VIL Address VIH VIL Row Column t RWL tWCS tWCH tWP WE VIH VIL OE VIH VIL tDS t DH DQ VIH VIL Valid Data-in "H" or "L" REV 1.0 May. 2000 15 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. NT511740D5J 16MEG : x4 CMOS with Extended Data Out PACKAGE DIMENSION 24/26-PIN PLASTIC SOJ (300mil) 17.27 17.01 7.75 7.49 8.60 8.34 PIN #1 INDEX 0.32 0.17 3.75 3.25 2.63 TYP. SEATING 0.95 TPY 1.27 0.50 0.38 0.81 MAX 6.98 6.48 0.635 MIN MAX NOTE : All dimensions in millimeters MIN or typical where noted. REV 1.0 May. 2000 16 (c) NANYA TECHNOLOGY CORP. NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice. |
Price & Availability of NT511740D5J
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |