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Ordering number : EN8928A
Bi-CMOS LSI
LV4147W
Overview
For LCD Panel Drive
Single Chip IC
The LV4147W is single chip IC for LCD panel drive.
Functions
* Analog block RGB Decoder/Driver * Digital block Timing Generator
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC1 max VCC2 max VDD max Allowable power dissipation Operating temperature Storage temperature Input pin voltage Pd max Topr Tstg VINA VIND VIND * : Mounted on a board : 30x30x1.6mm3, Analog input pin Digital input pin (Except pin 10, 11 and 12) Digital input pin (10, 11, 12pin) Conditions Analog LOW type Analog HIGH type Digital type Ta 75C * Mounted on a board. Ratings 6 12 4.5 350 -15 to +75 -40 to +125 -0.3 to VCC1 -0.3 to VDD+0.3 -0.3 to +4.5 Unit V V V mW C C V V V
glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
50907 TI PC B8-6537 No.8928-1/26
LV4147W
Operating Ratings at Ta = 25C
Parameter Recommended supply voltage Symbol VCC1 VCC2 VDD Operating voltage range VCC1op VCC2op VDDop Analog LOW type Analog HIGH type Digital type Analog LOW type Analog HIGH type Digital type Conditions Ratings 3.0 7.0 3.0 2.7 to 3.6 6 to 9.5 2.7 to 3.6 Unit V V V V V V
Input Signal Voltage
Parameter Recommended input signal voltage Y input signal Color Difference input signal Symbol Yin B-Yin R-Yin Sync chip - white 75% Color bar signal 75% Color bar signal Conditions Ratings 0.5 0.3 0.24 Unit Vp-p Vp-p Vp-p
Electrical DC Characteristics Unless otherwise specified, settings 1 and 2 must be made. Unless otherwise specified, VCC1 = 3.0V, VCC2 = VCCCOM = 7.0V, GND1 = GND2 = GNDCOM = 0, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0, Ta = 25C [Current Characteristics]
Parameter Current dissipation VCC1, analog LOW Current dissipation VCC2, analog HIGH Current dissipation VDD, logic IDD1 ICC2 Symbol ICC1 Conditions Enter SIG3 to (A), (D) and (E). Measure the current value of ICC1. Enter SIG3 to (A) Measure the current value of ICC2. Enter SIG3 to (A) Measure the current value of IDD11 and IDD21. IDD2 IDD1, IDD2, IDD3 = IDD11+IDD21 110,000 and 130,000 modes 180,000 mode 7 10 13 mA TRAP OFF TRAP ON Ratings min 18 20 2 typ 26 28 4 max 33 35 6 Unit mA mA mA
8.5
12
15.5
mA
[Digital block input/output characteristics]
Parameter L-level input voltage H-level input voltage H-level output voltage L-level output voltage Output transition time Symbol VIL VIH VOH1 VOL1 tTLH tTHL Cross point time difference T Load 50pF CKH1/CKH2 and CKV1/CKV2 and CKH3/CKH4 (See Fig. 4) CHK duty DTYHC Load 50pF Measure the duty of CKH1, CKH2, CKH3 and CKH4. (Note 1) Digital block input pins : LOAD, DATA, SCLK (Note 2) Digital block output pins : Pins 15 to 31, 33, 34 47 50 53 % Conditions Digital block input pin (Note 1) Digital block input pin (Note 1) IOH = -1.2mA (Note 2) IOL = 1.2mA (Note 2) Load 50pF (see Fig. 3) 0.7VDD VDD -0.2 0.3 30 30 10 Ratings min typ max 0.3VDD Unit V V V V ns ns ns
No.8928-2/26
LV4147W
Electrical AC Characteristics (1) Unless otherwise specified, the setting 1 and 2 must be made. Unless otherwise specified, VCC1 = 3.0V, VCC2 = VCCCOM = 7.0V, GND1 = GND2 = GNDCOM = 0, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0, Ta = 25C Unless otherwise specified, measure the non-inverted output of TP40, TP43, and TP45. [Y signal system]
Parameter Contrast characteristics, TYP Contrast characteristics, MIN Max. video gain Y signal frequency characteristics FTRPNT Symbol GCNTTP GCNTMN GV FTRPN0 Conditions Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Enter SIG3 to (A) and measure the ratio between the output amplitude (white to black) and input amplitude of TP43. Assume that the output amplitude of TP43 when SIG1 (0dB, 100kHz) is entered to (A) is 0dB. Change the input signal frequency to change and determine the frequency at which the output amplitude becomes -3dB. FTRPPL PAL 3.5 TRAP ON NTSC 3.0 TRAP OFF 6.0 MHz 19 21 23 dB -2 1 4.5 dB min 14 typ 16 max 18 unit dB
Picture quality adjustment variable amount 1 (TRAP OFF) 180,000 mode Picture quality adjustment variable amount 2 (TRAP OFF) 110,000 and 130,000 modes Picture quality adjustment variable amount 3 (TRAP ON) 110,000 and 130,000 modes Picture quality adjustment variable amount 4 (TRAP ON) 180,000 mode Y signal input/output delay rate
GSHP1X GSHP1N GSHP2X GSHP2N GSHP3X GSHP3N GSHP4X GSHP4N TDYTRN TDYTRP
Assume that the output amplitude of TP43 when SIG6 (100kHz) is entered in (A) is 0dB. Determine the output amplitude ratio of the input SIG6 (2.5MHz). Assume that the output amplitude of TP43 when SIG6 (100kHz) is entered in (A) is 0dB. Determine the output amplitude ratio of the input SIG6 (1.8MHz). Assume that the output amplitude of TP43 when SIG6 (100kHz) is entered in (A) is 0dB. Determine the output amplitude ratio of the input SIG6 (1.8MHz). Assume that the output amplitude of TP43 when SIG6 (100kHz) is entered in (A) is 0dB. Determine the output amplitude ratio of the input SIG6 (2.0MHz). Enter SIG8 to (A). Measure the delay time from the input signal 2T pulse peak to the peak of TP43 non-inverted output. TRAP OFF TRAP ON
MAX MIN MAX MIN MAX MIN MAX MIN
11
14 -3 0
dB
11
14 -1 2
dB
8
11 -5 -2
dB
6
9 -6 -3 400 450
dB
200 250
300 350
ns ns
[Color difference signal system]
Parameter Color difference input color adjustment GEXCMN Symbol GEXCMX Conditions Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB, 100kHz) to (D) and assume that the output amplitude (100kHz) of TP40 when COL = 128 is VCOCOL = 0 is VC2. Assume also that the output amplitude of TP40 when SIG1 is -10dB and COL = 255 is VC1. Calculate as follows : GEXCMX = 20log (VC1 / VCO) +10 GEXCMN = 20log (VC2 / VC0) Color difference balance VEXCBL Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB, 100kHz) to (D) and (E). Assume that the output amplitude (100kHz) of TP40 is VB and that (100kHz) of TP45 is VR. Calculate as follows : VEXCBL = VR / VB Continued on next page. 0.8 1.0 1.2 -20 -15 dB Ratings min +3 typ +5 max Unit dB
No.8928-3/26
LV4147W
Continued from preceding page. Parameter Color difference input balance adjustment R GEXRMN Color difference input balance adjustment B GEXBMN GEXBMX Symbol GEXRMX Conditions Input SIG4 (VL = 0mV) to (A) and SIG1 (-6dB, 100kHz) to (D) and (E). Assume that the output amplitude (100kHz) of TP45 and that (100kHz) of TP40 when TINT = 128 are VRO and VB0 respectively. The output amplitude of TP45 and that of TP40 when TINT=255 are VR1 and VB1 respectively. Assume also that the output amplitude of TP45 and that of TP40 when TINT = 0 are VR2 and VB2 respectively. Then, calculate as follows : GEXRMX = 20log (VR1 / VR0) GEXRMN = 20log (VR2 / VR0) GEXBMX = 20log (VB1 / VB0) GEXBMN = 20log (VB2 / VB0) G- matrix characteristics VEXGBN Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB, 100kHz) to (D). Assume that the output amplitude (100kHz) of TP40 is VEXGBP VEXB and that of TP43 is VEXBG. Calculate as follows ; VEXGB = VEXBG / VEXB VEXGR Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB, 100kHz) to (E). Assume that the output amplitude (100kHz) of TP45 is VEXR and that of TP43 is VEXRG. Calculate as follows ; VEXGR = VEXRG / VEXR 0.46 0.51 0.56 PAL 0.17 0.20 0.23 NTSC 0.23 0.26 0.29 +2 +2 +3 +3 -5 -2 dB dB dB Ratings min typ -5 max -2 Unit dB
[RGB signal system]
Parameter RGB signal and PCD output DC voltage Symbol VOUT Conditions Enter SIG4 (VL = 0mV) to (A) and adjust BRIGHT of serial bus to set TP43 output to 3Vp-p. Then, measure the DC voltage of TP38, TP40, and TP43. RGB signal and PCD output DC voltage difference VOUT Determine the maximum value of difference of measured values of TP40, TP43, and TP45 of VOUT as described in the above item. User brightness change rate UBRTMX Measure the change rate of the black level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and U-BRT is changed from 128 to 255. UBRTMN Measure the change rate of the white level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and U-BRT is changed from 128 to 0. Brightness change rate BRTMX Measure the change rate of the black level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and BRT is changed from 128 to 255. BRTMN Measure the change rate of the white level of TP40, TP43, and TP45 outputs when SIG2 is entered to (A) and BRT is changed from 128 to 0. Antipole output change rate COMMX COMMN Sub-brightness R change rates SBBRTR Enter SIG2 to (A), and measure the TP38 output amplitude when COM = 255. Enter SIG2 to (A), and measure the TP38 output amplitude when COM = 0. Enter SIG4 (VL = 0mV) to (A) and measure the difference between the black level of TP45 output when R-BRT = 128 and the black level of output when R-BRT = 0 and R-BRT = 255. Continued on next page. 1.3 1.7 V 1.5 Vp-p 4.6 Vp-p -2.5 -2.0 V 2.0 2.5 V -3 -2.0 V 2.0 3.0 V 0 120 mV Ratings min 3.3 typ 3.5 max 3.7 Unit V
No.8928-4/26
LV4147W
Continued from preceding page. Parameter Sub-brightness B change rates Symbol SBBRTB Conditions Enter SIG4 (VL = 0mV) to (A) and measure the difference between the black level of TP40 output when B-BRT = 128 and the black level of output when B-BRT = 0 and 255. Gain difference between RGB signals Sub-contrast R change rate SBCNTR GRGB Determine the level difference of non-inverted output amplitude (white to black) of TP40, TP43, and TP45 when SIG3 is entered to (A). Measure the non-inverted output (white to black) of TP45 for the non-inverted output (white to black) of TP43 when SIG3 is entered to (A) and when R-CNT = 0 and R-CNT = 255. Sub-contrast B change rate SBCNTB Input SIG3 to (A) and measure the difference of the level for B-CNT = 0 and 255 from the TP40 non-inverted output (white-black) when B-CNT = 128. RGB inverted/non-inverted gain difference GINV Determine the difference of inverted output amplitude for the non-inverted output amplitude (white to black) of TP40, TP43, and TP45 when SIG3 is entered to (A). Black level potential difference between RGB signals VBL Determine the difference between highest and lowest black levels for inverted and non-inverted outputs of TP40, TP43, and TP45 when SIG3 is entered to (A). Gamma gain GL GM GH Enter SIG7 to (A) and set the amplitude (black to white) of non-inverted output of TP43 to 3.5Vp-p with CONT and set the level to 1.5V through BRIGHT adjustment.Measure VG1, VG2, and VG3 and calculated as follows : GL = 20log (VG1/0.0357) GM = 20log (VG2/0.0357) GH = 20log (VG3/0.0357) (See Fig. 5) 1 adjustment variable range V1MN V1MX Enter SIG7 to (A) and set the TP43 output (black to black) to 3Vp-p through BRIGHT adjustment. Read the gain change point at 1 = 0, 1 = 255 by referring to the IRE level of input signal : V1MN for 1 = 0 V1MX for 1 = 255 2 adjustment variable range V2MN V2MX Enter SIG7 to (A) and set the TP43 output (black to black) to 3Vp-p through BRIGHT adjustment. Read the gain change point at 2 = 0, 2 = 255 by referring to the IRE level of input signal : V1MN for 2 = 0 V1MX for 2 = 255 PCD transition time tCOMH tCOML RGB output whitelimiter level VWLIMN VWLIMX Enter SIG3 to (A) and set the output amplitude of TP38 to 3Vp-p. Measure tCOMH for rise and tCOML for fall. Load : 20000pF Enter SIG2 to (A) and measure the amplitude of the white side limiter level of inverted / non-inverted TP38, 40, 43, and 45 output. VWLIMX when WLIM = 15 and VWLIMN when WLIM = 0. RGB output black limiter variable range VBLIMX VBLIMN Enter SIG2 to (A) and measure the amplitude of the black side limiter level of inverted/non-inverted TP43 output. VBLIMX for BLIM = 255 and VBLIMN for BLIM = 0 White limiter DC voltage Black limiter DC voltage VWLIM VBLIM Enter SIG4 (VL = 0mV) to (A) and measure the DC voltage of TP40, TP43, and TP45. Input SIG4 (VL = 350mV) to (A) and adjust BLIM to set the output of TP43 and TP40 to 3Vp-p. Measure the DC voltage of TP 40, TP43, and TP45. 3.3 3.3 3.5 3.5 3.7 3.7 V V 4.5 2 Vp-p Vp-p 4 2.2 1.5 1.5 3 3 s s Vp-p Vp-p 100 0 IRE IRE 100 0 IRE IRE 23.0 12.0 18.0 26.0 15.0 22.0 29.0 18.0 26.0 dB dB dB 300 mV -0.5 0 0.5 dB 2.0 dB 2.0 dB -0.6 0 0.6 dB Ratings min 1.3 typ 1.7 max Unit V
No.8928-5/26
LV4147W
[Filter characteristics]
Parameter TRAP attenuation amount Symbol ATRAPN ATRAPP Conditions Input SIG1 (0dB, 3.58MHz and 4.43MHz) in (A) and measure the TP43 output with a spectrum analyzer. Assuming that the TP43 amplitude in the TRAP ON mode is 0dB, determine the attenuation in the COMP input mode. R-Y, B-Y LPF characteristics DEMLPF Input SIG4 (VL = 150mV) in (A) and SIG1 (100kHz) in (B). In this case, assume that the amplitude of 100kHz component of TP40, TP45 output is 0dB. Change the SIG1 frequency at which the output amplitude of TP40, TP45 becomes -3dB. 1.2 1.6 1.9 MHz NTSC PAL Ratings min typ -15 -15 max -20 -20 Unit dB dB
[Sync separation, TG system]
Parameter Input sync signal width sensitivity Symbol WSSEP Conditions Enter SIG4 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm synchronization with the TP24 HD output. Narrow WS of SIG5 from 4.7s and determine WS at which synchronization between the input and TP24HD output is lost. Sync separation input sensitivity VSSEP Enter SIG4 (VL = 0mV, WS = 4.7s, VS variable) to (A) and confirm synchronization with the TP24 HD output. Reduce VS of SIG4 from 143mV and determine VS at which synchronization between the input and TP24HD output is lost. Sync separation output delay rate TDSYL TDSYH Enter SIG4 (VL = 0mV, WS = 4.7s, and VS = 143mV) to (A) and measure the delay rate from TP6RPD output. Assume that TDSYL is for a period from fall of input HSYNC to fall of RPD output and that TDSYH is for the period up to rise of RPD output. Horizontal pull-in range HPLLN HPLLP Enter SIG4 (VL = 0 mV, WS = 4.7s, and VS = 143mV, horizontal frequency variable) to (A) and confirm synchronization with TP24 HD output. Change the horizontal frequency of SIG5 and determine the frequency fH at which synchronization is established from the condition in which input / output synchronization is lost. Calculate as follows : HPLLN = fH-15734 HPLLP = fH-15625 NTSC PAL 500 500 Hz Hz 300 4.7 500 5.0 700 5.3 ns s 40 60 mV Ratings min 2.0 typ max Unit s
No.8928-6/26
LV4147W
[External input output characteristics]
Parameter External RGB input threshold value VTEXTW Symbol VTEXTB Conditions Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL variable) to (C), increase the amplitude (VL) from 0V. Assume that the voltage at which TP40, TP43, and TP45 outputs become the black level is VTEXTB. Further increase the amplitude and assume the voltage at which they become the white level. Propagation delay time between external RGB outputs TD1EXT TD2EXT Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL = 3V) to (C) and measure the rise delay TD1EXT and fall delay TD2EXT of TP40, TP43, and TP45 outputs. (See Fig. 2) External RGB output blanking level External RGB output white level External RGB input minimum pulse width TEXMIN EXTWT EXTBK Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL = 1.0V) to (C) and measure the difference of TP40, TP43, and TP45 from the black level. Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL = 2.7V) to (C). Measure the difference of TP40, Tp43, and TP45 from the black level. Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL = 2.7V) to (C) and measure the minimum pulse width at which TP40, TP43, and TP45 outputs reach the white side limiter. 3.0 0 V 50 70 90 100 130 150 ns ns Ratings min 0.55 typ 0.7 max 0.85 Unit V
1.62
1.8
1.95
V
V
150
ns
Package Dimensions
unit : mm (typ) 3281
9.0 7.0 48 49 33 32
7.0
9.0
64 1 0.4 (0.5) 16 0.18
17 0.125
1.55max
0.1
(1.35)
SANYO : LQFP64(7X7)
0.5
No.8928-7/26
LV4147W
Conditions of setting to measure the electric characteristics Following settings must be made before measurement of electric characteristics. Setting 1. System reset Turn ON SW58 and start V58 from GND in order to perform system reset for MOS block. (See fig. 1-1.) The default value is set for the serial bus. Setting 2. Horizontal AFC adjustment Enter SIG5 (VL = 0mV) to (A) and adjust VCOADJ so that the width of WL and WH becomes equal in the TP6 output waveform. (See fig. 1-2.) (Note) In order to measure the 2MHz or more band for measurement items, such as the Y-system frequency characteristics or sharpness characteristics, it is necessary to pass through the sample hold circuit via serial bus.
VDD1, VDD2
V58(RESET)
Tr
Tr > 10s
Fig.1-1 System reset
SIG5
V-sync
TP6
TP6
Approx.1/2VDD
Fig.1-2 Horizontal AFC adjustment
No.8928-8/26
LV4147W
Electric characteristics measurement method
3V
SIG6
0V
100% 50% P40, 43, 45 Non-inverted output
TD1EXT
TD2EXT
Fig.2 Delay between external RGB input/output
tTLH tTHL 90%
10%
Fig.3 Output transition time measurement contitions
T
50%
T
Fig.4 Cross point time difference measurement conditions
White VG3 Non-inverted output
VG2 3.5V
VG1 1.5V Input
Black
Fig.5 characteristics measurement conditions
No.8928-9/26
LV4147W
Block Diagram
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name EXTR EXTG EXTB TRAP VDD1 RPD VSS1 TEST2 TEST3 LOAD DATA SCLK TEST1 VDD2 I O I I I I O I/O I I I O Pin Description External digital R input (used also for the test) External digital G input (used also for the test) External digital B input (used also for the test) External trap connection pin Oscillator cell input (3V) Phase comparison output Oscillator cell GND Test pin 2 Test pin 3 Load input for serial bus Data input for serial bus Clock input for serial bus Test pin 1 Digital 1 system power supply (3V) Common For MONI only For EVF only

Continued on next page.
No.8928-10/26
LV4147W
Continued from preceding page. Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name XSTH2 STH2 XSTH1 STH1 CKH4 CKH3 CKH2 CKH1 XDSG DSG BLHD HD XSTV/STV2 STV CKV2/CKV4 CKV1/CKV2 VD VSS2 XENB ENB SCAN FBCOM GNDCOM COMOUT VCCCOM BOUT FBB GND2 GOUT FBG ROUT FBR VCC2 SIGCENT VCC1 NC NC NC BYIN RYIN NC VREG NC RESET YIN START-UP SYNCIN VSEPTC F0ADJ GND1 O I I I I System reset Brightness signal input Power-ON blanking time constant pin Sync input Time constant and external VD input for vertical sync separation Filter F0 adjustment 3V ground I I O Reference voltage B-Y input R-Y input I O I O I O I O O O O I I/O O O O O O O O O O O O O O O O O O Pin Description EVF H-start reverse phase output EVF H-start output Monitor H-start reverse phase output Monitor H-start output EVF H-clock 2 output EVF H-clock 1 output Monitor H-clock 2 output Monitor H-clock 1 output Drain hold timing pulse reverse-phase output Drain hold timing pulse output Backlight HD output H drive output V-start reverse phase output/EVF V start output V start output V clock 2 output/EVF CKV2 V clock 1 output/Monitor CKV2 V drive output Digital 1 system GND Enable reverse-phase output Enable output For scan selection (for monitor) Time constant pin for antipole output DC return Antipole output gland Antipole output Antipole output power supply (7V) B output Time constant pin for B-output DC return Output system ground G output Time constant pin for G-output DC return R output Time constant pin for R-output DC return Output system power supply Output DC level setting pin Analog 3V power supply Common For MONI only For EVF only

() () () ()

No.8928-11/26
LV4147W
Analog pin function description
Pin No. 1 2 3 Pin Name EXTR EXTG EXTB Pin Voltage Pin Description The external digital signal is entered. All of RGB outputs become the black level when the threshold value is about 0.7V for Vth1 and about 1.8V for Vth2 and any one of RGB exceeds Vth1 and become the white level only for the output in which the input exceeds Vth2. Connect to the ground when not using. Equivqlent Circuit
VCC1 1 2 3 GND1
25A 300 0.7V
4
TRAP
1.0V
External trap pin. Trap can be inserted into Y-signal by connecting L and C in series to GND when TRAP ON is set.
VCC1 1k 4 300 200A GND1 75A
13
TEST1
-
Test pin. Connect this pin normally to GND for use.
VDD2
100k 20k 20k 100k
13
GND1
35 SCAN Scan select control output pin. Output from the open collector
VCC2
GND2
36 FBCOM 1.5V Feedback circuit smoothing capacitor pin for precharge output DC level control. Because of high impedance, a capacitor with small leakage is used.
VCC1 1k 36 1k 100k 1k 1k
GND1
37 38 GNDCOM COMOUT 0V VCC2/2 Gland of antipole output Antipole output
VCCCOM 150 38 20 GNDCOM
39 VCCCOM 7V Power supply for antipole output Continued on next page.
50k 35
No.8928-12/26
LV4147W
Continued from preceding page. Pin No. 40 43 45 Pin Name BOUT GOUT ROUT Pin Voltage VCCC2/2 Pin Description RGB primary color signal output. Equivqlent Circuit
VCC2 40 43 45 20 20 40A 1k 41 44 46 100k GND1 1k 1k 1k
GND2
41 44 46 FBB FBG FBR 1.5V Feedback circuit smoothing capacitor pin for RGB output DC level control.Because of high impedance, a capacitor with small leakage is used.
VCC1
1k
42 47 48
GND2 VCC2 SIGCENT
0V 7V VCC2/2
VCC2 ground. Power supply of output system Apply external voltage when the signal output DC voltage is to be used for those other than 1/2 VCC2.
48
300
150k GND2
49 53 54 VCC1 BYIN RYIN 3.0V 1.7V Analog 3V power supply. Enter the color difference of R-Y/B-Y. The clamp level in this case is about 1.7V.
VCC1
4k
150k 10k 5k
VCC2
53 54
1k
GND1
56 VREG 2.0V Regulator output pin. Connect an external capacitor of 1F or more.
4k
40A
30A
VCC1
56 18.5k 30k
GND1
Continued on next page.
No.8928-13/26
LV4147W
Continued from preceding page. Pin No. 58 Pin Name RESET Pin Voltage Pin Description C-MOS circuit reset pin. Normally, connect a capacitor between this pin and GND during use. (Threshold value = 2.0V) Equivqlent Circuit
VDD2 2A 300 58 1k
GND1
59 YIN 1.6V Y signal input pin. The standard input signal level is 0.5Vp-p (from sync chip to 100% white).
VCC1 1k
59
20A GND1
60 START-UP Time constant connection pin to set the RGB output to the black level at power ON. Connect the pin to VDD2 when not using. (Threshold value = 2.0V)
VDD2
1A 300
60
1k
GND1
61 SYNCIN 1.6V Input pin for sync separation.
VDD2
1k 1k 500
61
GND1
62 VSEPTC 1.7V Time constant connection pin for vertical sync separation. (The pin is used also for external VD input.)
0.6A
12A
VDD2
500 1k 1k 20A
62
GND1
63 f0ADJ 1.5V Reference current generation pin for filter. 15k is connected between this pin and GND to generate the reference current. (Keep the pin open for trap OFF mode.)
20A
VCC1
200 5pF 500
63 GND1
64 GND1 0V 3V ground.
500 5pF
No.8928-14/26
LV4147W
Digital pin function description
Pin No. 5 6 Pin Name VDD1 RPD Pin Voltage Equivalent Circuit Power supply dedicated for VCO. Phase comparator output. Pin Description
6 VDDVCO 1k 100k 1.5V 600 2k 1k 5k 10k
100k GND1
7 8 9 VSS1 TEST2 TEST3 0 Digital ground for VCO. Test pin.Normally, connect the input side (TEST2) to GND during use.
VDD1 8 9 VSS1
10 11 12
LOAD DATA SCLK
-
Serial bus input pin.
VDD2
VSS2
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 32 VDD2 XSTH2 STH2 XSTH1 STH1 CKH4 CKH3 CKH2 CKH1 XDSG DSG BLHD HD XSTV/STV2 STV CKV2/CKV4 CKV1/CKV2 VD XENB ENB VSS2 O Digital ground. Digital output pin. Digital output pin.
VDD2
VSS2
No.8928-15/26
No. 1 2 A A NT NT NT NT NT NT NT NT NT NT NT NT ON ON ON ALL 128 128 128 128 ALL ALL ALL 110,000 NT NT ON ON B B ON NT NT 110,000 180,000 B B 180,000 ON ON ON ON ALL ALL ALL ALL 128 128 128 128 128 128 128 ALL ALL ALL 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 128 0 255 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 128 128 128 128 180,000 OFF 180,000 ON ON 180,000 180,000 OFF 180,000 OFF 110,000 OFF 110,000 OFF NT PAL 128 1 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 128 128 128 128 128 128 0 0 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1 128 128 128 128 128 128 0 0 ADJ 1 128 128 128 128 128 128 0 0 ADJ 128 128 128 128 128 128 128 128 128 128 180 128 128 255 0 255 0 255 0 255 0 1 128 128 128 128 128 128 0 0 ADJ 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180,000 ON 1 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 110,000 ON 1 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ON 1 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 A A A A A A A A A A A A A A A A A A A A A A A A A A OFF A OFF A OFF B B A OFF B B ON A OFF A A ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON ON 1 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 A OFF B B ON NT ON 1 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 3 48 53 54 58 System Panel TRAP S/H COL BRT CNT R-B B-B PLL PIC A A A A A A A A A A A A A A A A A A A A A A A A A A A TINT 1 2
Parameter
Symbol
Input signal,
SW set BLM1 UBRT RCNT BCNT COM WLIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mode set
DAC set
condition, etc.
0
(Setting 2, horizontal AFC adjustment)
(A) = SIG4 (VL = 0mV)
1
Current dissipation VCC1
ICC1
(A) = SIG3
2
Current dissipation VCC2
ICC2
(A) = SIG3
3
IDD1
(A) = SIG3
Current dissipation VDD(110,000 and 130,000) Current dissipation VDD(180,000)
IDD2
(A) = SIG3
4
L-level input voltage
VIL
(A) = SIG3
5
H-level input voltage
VIH
(A) = SIG3
6
H-level output voltage
VOH1
(A) = SIG3
7
L-level output voltage
VOL1
(A) = SIG3
8
Output transition time
tTLH
(A) = SIG3
tTHL
(A) = SIG3
9
Cross point time difference
T
(A) = SIG3
10
CKH duty
DTYHC
(A) = SIG3
LV4147W
11
Contrast characteristics, TYP
GCNTTP
(A) = SIG3
12
Contrast characteristics, MIN
GCNTMN
(A) = SIG3
13
Video max. gain
GV
(A) = SIG3
14
Y signal frequency
FTRPNO
(A) = SIG1
FTRPNT
(A) = SIG1
FTRPPL
(A) = SIG1
15
Picture quality variable amount 1
GSHP1X
(A) = SIG6
(TRAP OFF) 180,000 mode
GSHP1N
(A) = SIG6
16
GSHP2X
(A) = SIG6
Picture quality adjustment variable amount 2 (TRAP OFF) 110,000 and 130,000 modes
GSHP2N
(A) = SIG6
17
GSHP3X
(A) = SIG6
Picture quality adjustment variable amount 3 (TRAP ON) 110,000 and 130,000 modes
GSHP3N
(A) = SIG6
18
Picture quality adjustment
GSHP4X
(A) = SIG6
No.8928-16/26
(A) = SIG6 GSHP4N (TRAP ON) 180,000 mode Note: PLL must be reset when the panel mode is changed.
variable amount 4
No. 1 2 A A A A A A A NT PAL B ON ALL ALL ALL ALL ALL ALL ALL ALL ALL 128 128 128 128 128 128 128 128 128 ALL 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 255 0 128 128 160 160 128 128 128 128 128 ALL 128 128 128 ALL 128 128 128 255 255 255 255 128 128 128 128 128 70 70 128 128 ALL 128 ADJ 128 128 128 128 128 128 128 128 128 SET 128 128 128 128 128 128 ALL 128 128 ADJ 128 128 128 128 128 128 128 128 128 128 128 SET 128 128 128 128 128 ALL 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL 128 128 128 128 128 128 0 0 ALL 0 128 128 128 128 128 0 0 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ALL 255 128 128 128 128 128 0 0 ADJ 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 A A A A A A A A A A A A A A A A A A A A A OFF B A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B A ON A OFF A B ON A OFF A B ON A OFF A B ON A OFF A B ON A OFF B A ON ALL 128 128 128 128 128 0 0 ADJ 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A OFF B A ON ALL 255 128 128 128 128 128 0 0 ADJ 128 0 A OFF A A ON ALL 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 255 0 128 128 128 128 128 128 128 128 128 128 128 A OFF A B ON ALL 128 0 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 SET 128 128 128 A OFF A B ON ALL 128 255 128 128 128 128 0 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 SET 128 128 A OFF B B ON ON ALL 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 A OFF B B ON NT OFF ALL 128 128 128 128 128 128 0 0 ADJ 128 0 128 128 128 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 255 0 64 64 64 64 64 64 64 3 48 53 54 58 System Panel TRAP S/H COL BRT CNT R-B B-B PLL PIC A A A A A A A A A A A A A A A A A A A A A A A A A A A TINT 1 2
Parameter
Symbol
Input signal, BLM1 UBRT RCNT BCNT COM WLIM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SW set
Mode set
DAC set
condition, etc.
19
Y signal input/output delay rate
TDYTRN
(A) = SIG8
TDYTRP
(A) = SIG8
20
Color difference input color
GEXCMX
(A) = SIG4, (D) = SIG1
adjustment
GEXCMN
(A) = SIG4, (D) = SIG1
21
Color difference balance
VEXCBL (A) = SIG4, (D) = (E) = SIG1
22
Color difference input balance
GEXRMX (A) = SIG4, (D) = (E) = SIG1
adjustment R
GEXRMN (A) = SIG4, (D) = (E) = SIG1
23
Color difference input balance
GEXBMX (A) = SIG4, (D) = (E) = SIG1
adjustment B
GEXBMN (A) = SIG4, (D) = (E) = SIG1
24
G-Y matrix characteristics
VEXGBN
(A) = SIG4, (D) = SIG1
VEXGBP
(A) = SIG4, (D) = SIG1
VEXGR
(A) = SIG4, (D) = SIG1
25
RGB output DC voltage
VOUT
(A) = SIG4
26
RGB output DC voltage difference
VOUT
(Calculation)
LV4147W
27
User brightness change rate
UBRTMX
(A) = SIG2
UBRTMN
(A) = SIG2
28
User brightness change rate
BRTMX
(A) = SIG2
BRTMN
(A) = SIG2
29
Antipole output change rate
COMMX
(A) = SIG2
COMMN
(A) = SIG2
30
Sub-brightness R change rate
SBBRTR
(A) = SIG4
31
Sub-brightness B change rate
SBBRTB
(A) = SIG4
32
Gain difference between RGB signals
GRGB
(A) = SIG3
33
Sub-contrast R change rate
SBCNTR
(A) = SIG3
34
Sub-contrast B change rate
SBCNTB
(A) = SIG3
No.8928-17/26
35
RGB inverted/non-inverted gain GINV (A) = SIG3 difference 36 Black level potential difference VBL (A) = SIG3 between RG signals Note: PLL must be reset when the panel mode is changed.
No. 1 2 A NT PAL 128 128 128 128 128 128 128 128 128 ALL ALL ALL ALL ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 NT PAL ALL ALL ALL ALL ALL ALL ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 128 ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ON ALL 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ON 128 ALL 128 128 128 128 128 ALL 128 128 0 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL 128 128 255 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL 128 128 0 128 128 128 0 0 ALL 128 128 0 128 128 128 0 0 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 128 ALL 128 255 128 128 128 0 0 ADJ 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 255 128 128 128 0 0 ADJ 128 ALL 128 128 128 128 128 128 0 0 ADJ 128 0 64 64 0 255 64 ADJ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL 128 128 ADJ 60 128 128 0 255 ADJ 128 0 128 128 0 0 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 ADJ 60 128 128 0 0 ADJ 128 0 128 ALL 128 128 ADJ 60 128 128 255 0 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 ADJ 60 128 128 0 0 ADJ 128 0 128 128 ALL 128 128 ADJ ADJ 128 128 120 210 ADJ 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL 128 128 ADJ ADJ 128 128 120 210 ADJ 128 0 128 128 128 64 64 64 64 64 64 ADJ 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 A A A A A A A A A A A A A A A A A A A A A A B B B B B B B B OFF B B ON B OFF B B ON B OFF B B ON B OFF B B ON B OFF B B ON B OFF B B ON B OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON A OFF B B ON ALL 128 128 ADJ ADJ 128 128 120 210 ADJ 128 0 128 128 128 64 0 0 0 0 0 0 0 0 0 15 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 48 53 54 58 System Panel TRAP S/H COL BRT CNT R-B B-B PLL PIC A A A A A A A A A A A A A A A A A A A A A A A B B B B B B B TINT 1 2 BLM1 UBRT RCNT BCNT COM WLIM
Parameter
Symbol
Input signal,
SW set
Mode set
DAC set
condition, etc.
37
Gamma gain
GL
(A) = SIG7
GM
(A) = SIG7
GH
(A) = SIG7
38
1 adjustment variable range
V1MN
(A) = SIG7
V1MX
(A) = SIG7
39
2 adjustment variable range
V2MN
(A) = SIG7
V2MX
(A) = SIG7
40
Antipole output transition time
tCOM
(A) = SIG3
41
RGB output white limiter
VWLIMN
(A) = SIG2
Operating voltage
VWLIMX
(A) = SIG2
42
RGB output black limiter
VBLIMN
(A) = SIG2
variable range
VBLIMX
(A) = SIG2
43
White limiter DC voltage
VWLIM
(A) = SIG4
44
Black limiter DC voltage
VBLIM
(A) = SIG4
45
TRAP attenuation amount
ATRAPN
(A) = SIG1
ATRAPP
(A) = SIG1
LV4147W
46
R-Y, B-Y LPF characteristics
DEMLPF
(A) = SIG4, (D) = (E) = SIG1
47
Input sync signal amplitude sensitivity
WSSEP
(A) = SIG4
48
Sync separation input sensitivity
VSSEP
(A) = SIG4
49
Sync separation output delay
TDSYL
(A) = SIG4
rate
TDSYH
(A) = SIG4
50
Horizontal pull-in range
HPLLN
(A) = SIG4
HPLLP
(A) = SIG4
51
External RGB input threshold
VTEXTB
(A) = SIG4, (C) = SIG5
voltage
VTEXTW
(A) = SIG4, (C) = SIG5
52
Propagation delay time between TD1EXT
(A) = SIG4, (C) = SIG5
external RGB outputs
TD2EXT
(A) = SIG4, (C) = SIG5
53
External RGB output blanking level
EXTBK
(A) = SIG4, (C) = SIG5
54
External RGB output white level
EXTWT
(A) = SIG4, (C) = SIG5
55
External RGB input minimum pulse width
TEXMIN
(A) = SIG4, (C) = SIG5
No.8928-18/26
Note: PLL must be reset when the panel mode is changed.
LV4147W
Input sine wave (1)
SG No. SIG1 Sine wave With/without sine wave video signal (Amplitude, Frequency variable)
150mV
Value shown in the left 0dB
143mV
SIG2
357mV
143mV
SIG3
150mV
5-step staircase wave
143mV
SIG4 VL amplitude variable VS variable : 143mV, unless otherwise specified. WS variable : 4.7s, unless otherwise specified.
VL VS WS fH
fH variable : NTSC 15.734kHz PAL 15.625kHz, unless otherwise specified.
Input sine wave (2)
SG No. SIG5 Sine wave
30s GND
5s VL
VL amplitude variable
SYNC timing
SIG6
75mV 175mV 143mV
Frequency variable
SIG7
357mV 143mV
SIG8
10-step staircase wave
357mV
sin2 2T pulse
143mV
No.8928-19/26
LV4147W
Serial bus communication specifications (1) Conditions for serial transfer
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
ts1
th1
SCLK
50%
tw1L
tw1H
LOAD
50%
ts0
th0
tw2
Parameter Serial transfer Data setup time
Symbol
Conditions
min
typ
max
unit
ts0 ts1
LOAD setup time to start SCLK. DATA setup time to start SCLK. LOAD hold time to start SCLK Data hold time to start SCLK. SCLK pulse width. SCLK pulse width. LOAD pulse width.
150 150 150 150 160 160 1.0
ns ns ns ns ns ns s
Data holdup time
th0 th1
Pulse width
tw1L tw1H tw2
No.8928-20/26
LV4147W
(2) 3-wave serial format
DATA
SCLK
LOAD
Data length : 16bit Clock frequency : 3MHz or less Only when SCLK is input in 16-bit clock while LOAD is in the L period, DATA is accepted at rise of LOAD. Note : When SCLK is in 15-bit or 17-bit clock while LOAD is in the L period, DATA is not accepted.
(3) Data output timing 1. Various mode settings DATA accepted at rise of LOAD is set at fall of the vertical sync signal. When the data is transmitted several times for the same item, the data immediately before the vertical sync signal becomes valid. 2. Setting of the electric volume Concurrently with acceptance of DATA at rise of LOAD, the D/A output data is changed.
No.8928-21/26
LV4147W
(4) Data specifications 1
D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 D3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 D2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 D0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Not used Not used TRAP ON TRAP OFF Not used Not used System changeover NTSC System changeover PAL External VSYNC input OFF External VSYNC input ON Y/color difference clamp position, pedestal Y/color difference clamp position, SYNC Sample hold phase SHS1 Sample hold phase SHS2 Sample hold phase SHS3 Sample hold phase ALL through HD output polarity, positive HD output polarity, negative VD output polarity, positive VD output polarity, negative Panel selection 521 x 218 : 110,000 mode Panel selection 557 x 234 : 130,000 mode Panel selection 800 x 225: 180,000 mode For test. Do not set this bit to "1". Field overlap method, odd number on even number Field overlap method, even number on odd number Normal mode 521x218 (EVF) + 557x234 (monitor) driving BLHD output ON BLHD output Stop Sync generator function, OFF Sync generator functionON (output other than HD, VD, BLHD, and SPCLK is turned OFF). Normal mode For test. Do not set this bit to "1". For test. Do not set this bit to "1". For test. Do not set this bit to "1". Skipping OFF mode for PAL (Indication of no skipping) For test. Do not set this bit to "1". Not used Not used Not used Normal mode For test. Do not set this bit to "1". For test. Do not set this bit to "1". For test. Do not set this bit to "1". For test. Do not set this bit to "1". Not used For test. Do not set this bit to "1". For test. Do not set this bit to "1". For test. Do not set this bit to "1". (Note 6) (Note 6-3) (Note 1) (Note 1) (Note 1) (Note 1) Description Default

x x x x
x x x x x x x
No.8928-22/26
LV4147W
(4) Data specifications 2
D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D7 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 D6 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 D5 x x x x 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 D4 D3 D2 D1 D0 Description H-position setting, 2/fh x 31 steps V-position setting, 1H x 4 steps HD phase setting, 4/fh x 31 steps BLHD pulse setting, 2/fh x 31 steps (Note 2) (Note 3) (Note 4) (Note 5) Default 10000 010 00000 10000 HC5 HC4 HC3 HC2 HC1 x x VP2 VP1 VP0
HD6 HD5 HD4 HD3 HD2 HW5 HW4 HW3 HW2 HW1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Monitor horizontal inversion, normal scan mode Monitor horizontal inversion, reverse scan mode Monitor vertical inversion, normal scan mode Monitor vertical inversion, reverse scan mode EVF horizontal inversion, normal scan mode EVF horizontal inversion, reverse scan mode EVF vertical inversion, normal scan mode EVF vertical inversion, reverse scan mode Scan changeover pin, normalSCAN pin : OPEN Scan changeover pin, reverse scanSCAN pin : OPEN Not used Not used VCO sensitivity changeover 1 VCO sensitivity changeover 2 VCO sensitivity changeover 3 VCO sensitivity changeover 4 Monitor scan stop mode Monitor display mode EVF scan stop mode EVF display mode blanking period CHK/STH stop OFF (NORMAL) blanking period CKH/STH stop ON (power save mode) H blanking period CKH stop OFF (NORMAL) H blanking period CKH stop ON (power save mode) Panel connection form MODE 1 Panel connection form MODE 2 Normal mode For test. Do not set this bit to "1". (Note 6-1) (Note 6-2) (Note 6-4) (Note 6-4)

x
(4) Data specifications 3 (DAC set)
D15 D14 D13 D12 D11 D10 D9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 TINT adjustment COLOR adjustment BRIGHT adjustment CONTRAST adjustment R-BRIGHT adjustment B-BRIGHT adjustment -1 adjustment -2 adjustment Antipole output amplitude adjustment R-CONT adjustment B-CONT adjustment BLKLIMT adjustment Not used PICTURE adjustment USER-BRIGHT adjustment VCO adjustment WHTLIMT adjustment Test mode. Do not set this address. Description Default 10000000 10000000 10010101 10001100 10000000 10000000 01100100 00000000 01010000 10000000 10000000 10101100 00000000 10000000 10000000 10000000 0000 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 x x x x DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
No.8928-23/26
LV4147W
(Note 1) Sample hold phase S/H pulse timing
CKH1 R S/H1 S/H4
A G B B C S/H3 S/H4 S/H2 S/H4
SH1
SH2
SH3
SH4
Horizontal inversion
SHS1 SH1 SH2 SH3 SH4 B through A C
Normal scan
SHS2 A through C B SHS3 C through B A
Horizontal inversion
SHS1 SH1 SH2 SH3 SH4 B A through C
Reverse scan
SHS2 A C through B SHS3 C B Through A
SH1 : SH pulse for R signal SH3 : SH pulse for B signal
SH2 : SH pulse for G signal SH4 : Common SH pulse for RGB signal
(Note 2) H-Position set (step 1 = 2x1/fvco)
: 1/fvco 90ns <521x218, 557x234 mode> : 1/fvco 60ns <881x228 mode>
CLK (fh)
10001(+1) STH 10000 (Default) 01111 (-1)
Step 1 Step 15
Step 1 Step 16
Center
No.8928-24/26
LV4147W
(Note 3) V-Position set
-2H -1H 2H STV (DEFAULT) +1H +2H
000 001 010 011 100
(Note 4) HD phase set (step 1 = 4x1/fvco)
HSYNC
HD
00000 (Default)
HD Step 31
11111
(Note 5) BLHD phase set (step 1 = 2x1/fvco)
00000 Step 16 Approx.6s BLHD Step 15 10000 (Default) 11111
ON/OFF (output L fixed) possible with the serial bus
No.8928-25/26
LV4147W
(Note 6) Output signal by mode
MODE1 (Note 6-1) Pin No. Pin symbol Normal Common For EVF 18 17 22 21 28 27 30 29 34 33 24 23 16 15 20 19 STH1 XSTH1 CKH1 CKH2 STV XSTV/STV2 CKV1/CKV2 CKV2/CKV4 ENB XENB PCG XPCG STH2 XSTH2 CKH3 CKH4 For monitor Normal Common For EVF For monitor MODE2 (Note 6-2) (521x218)+ (557x234) (Note 6-3) Common For EVF For monitor Scan OFF (Note 6-4) Motor OFF "L" "H" "L" "H" EVF OFF "L" "H" "L" "H"

*

*

*
(STV2)
(CKV2) *
*
(CKV2) *
(CKV4)
(CKV4)

* : Generated with an external inverte
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of May, 2007. Specifications and information herein are subject to change without notice. PS No.8928-26/26

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