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STP2223BGA
July 1997
U2P
DATA SHEET DESCRIPTION
The U2P * chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus (including UltraSPARC Processors and Memory) and a PCI based I/O Subsystem. Its major functions are UPA port interface, PCI bus interface, processor I/O data transfers, DMA data transfers and interrupt dispatch.
UPA to PCI Interface
Features
* Full master and slave port connection to the high-speed UltraSPARC UPA Interconnect Architecture. The UPA is a split address/data packet-switched bus which has a potential data throughput rate of over one gigabyte/sec. UPA data is ECC protected. * Two physically separate PCI bus segments, with full master and slave support. PCI Bus A has the following features: - 5 volt or 3.3 volt signalling. - 64-bit data bus. - Compatible with the PCI Rev 2.1 Specification. - Compatible with the PCI 66MHz extensions. - Support for up to four master devices (at 33MHz only). PCI Bus B has the following features: - 5 volt signalling. - 64-bit data bus. - Compatible with the PCI Rev 2.1 Specification. - Support for up to six master devices. * Two separate 16-entry streaming caches, one for each bus segment, for accelerating some kinds of PCI DVMA activity. Single IOMMU with 16-entry TLB for mapping DVMA addresses for both busses. * A "Mondo-Vector" Dispatch Unit, or MDU, for delivering Interrupt requests to UltraSparc CPU modules, including support for PCI interrupts from up to six total slots, as well as interrupts from on board IO devices.
* U2P was code named Psycho+
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PRODUCT SUMMARY
The U2P uses the standard cell library from Lucent Technologies. It is implemented in 0.35 micron, 3 level metal and 3.3 volt optimized CMOS technology. The U2P die has 352 signal pads (including specialty power/grounds) and 104 VSS/VDD pads for a total pad count of 456. The U2P package is a 456 pin PBGA, with 352 signal pins and 104 VSS/VDD pins. Its die consists of 170k gates and 29k bits of RAM. The U2P design includes the following non-standard cells: * 5V tolerant PCI pads. * 66MHz capable PCI pads. * UPA pads (without holding amps). * PLL and PECL receiver for UPA clock. * PLL for main clock. The UPA operation is up to 100 MHz (10ns). Its main internal clock is up to 66.7 MHz (15 ns). The PCI bus A clocks at 1x or 0.5x internal clock (synchronous). The PCI bus B clocks at 0.5x internal clock (synchronous). The maximum power consumption is 3 watts.
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Typical System Partition
Figure 1. shows one possible configuration of U2P in a PCI UltraSPARC system. U2P connects to the System Controller chip and other UPA ports via UPA address, control and data busses. The system has both PCI and EPCI slots, as well as an on board PCI device (PCIO). Interrupt information is provided by the RIC chip, and a JTAG port is provided for board testing as well as in-circuit testing and debugging of U2P.
Memory Data (256+32ECC) BMX Memory SIMMs
UPA_D0(127:0+ECC)
UPA_D1(63:0+ECC)
Memory Address Memory Control
UPA_A0(35:0) UPA/S 64b
Graphics
UPA_A1(35:0)
System Controller
UPA_Ctrl TA(15:0) Tag TD(24+3+P)
Ultra SPARC
Clk PCI Interface A
PCI Bus
DA(18+16BE) D(128+16P) 512KB E$
UDB
UPA Interface
PCI Bus
PCI Interface B
Bus Adapter
PCIO
Figure 1. Typical System Block Diagram
July 1997
Ethernet
RIC
U2P
EBus 2
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External Interfaces
Figure 2. summarizes the external interfaces and pins of U2P.
UPA_DataBus UPA_ECC UPA_Addressbus
64 8 36 6 5 5 3 64 2 8 7 4 4 4 2 2 A_AD A_PAR A_C/BE# A_CTRL A_REQ# A_GNT# A_IDSEL A_ERR A_CLK PCI_RST
UPA 130 pins
UPA_Arbitration UPA_P_Reply UPA_P_Reply UPA_Misc UPA_Reset_L UPA_Sys_Clk
PCI A 96 pins
U2P
JTAG 5 64 2 8 7
TEST 10 pins
Shared PCI RST 1 pin
MISC
5
B_AD B_PAR B_C/BE# B_CTRL B_REQ# B_GNT# B_ERR B_CLK
PCI B 96 pins
Intr. 6 pins
6 INT_NUM 6 6 2 TMR_CLK
Clocks 5 pins
PSYCLK BYPASS
2 2 VSSA 2 VDDA VDD5
Power/Ground
104
5
Special pwr/gnd 8 pins
Figure 2. U2P External Interfaces
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Block Diagram
Figure 3. shows a conceptual block diagram of U2P. The actual implementation is somewhat different - for example, there are no internal bidirectional busses. Block diagrams with the actual implementation details can be found in the U2P Users Manual.
JTAG JTAG PIO Ctl. DMA Ctl. BUS Ctl. PCI Bus Module A PCI Bus A
IOMMU
Streaming Cache A
Streaming Cache B
UPA UPA
ECC Gen/ Check
Merge Buffer
PCI Bus B PCI Bus Module B
Timer/ Counters
Mondo Dispatch Unit
Interrupts
Figure 3. U2P Internal Block Diagram
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Functional Block Overviews
This section gives a brief description of each top level functional block. A more detailed description of each block can be found in the U2P Users Manual. Each block is described in its own individual chapter in the U2P Users Manual. The top level blocks in U2P fall into one of five categories: * UPA. * PCI. * Interrupt. * Internal Control. * Miscellaneous. UPA Interface blocks The UPA is UltraSPARC's packet switched main system bus. In an UltraSPARC system, the UPA can operate up to 100 MHz. Data and address have independent flow controls. Each type of UPA cycle (PIO read, PIO write, DMA read, etc.) uses its own FIFO-based queueing. There is a synchronization boundary between the UPA interface blocks and other U2P blocks, which run at 66.7 MHz. * UPA Master/Slave: This block deals exclusively with UPA address control. It listens to UPA_A when U2P is a slave. It also arbitrates for and drives UPA_A when U2P is a master. * UPA_Reply: This block deals exclusively with UPA data. It generates P_REPLY to the System Controller (SC) ASIC during PIO and copyback cycles. It also listens to S_REPLY from the SC and manages the UPA data FIFO's accordingly. * ECC Generate: Generates ECC on the outgoing 64-bit UPA data path. * ECC Check: Checks ECC on the incoming 64-bit UPA data path. PCI Interface blocks * PBM (PCI Bus Module): This is the main portion of the PCI interface. U2P contains two nearly identical copies of this block. One is designed to support a 64-bit PCI bus at 66 MHz or 33 MHz with up to four master devices. The other supports a 64-bit PCI bus at 33MHz with up to six master devices. The PBM adheres to all PCI protocol guidelines as contained in the PCI Revision 2.1 specification. Each PBM controls arbitration, flow control and error handling for its bus segment. Each PBM also handles the big- to little-endian byte twisting required for correct operation of both PIO and DVMA datapaths. * IOMMU: For the portion of the PCI memory address space which is reserved for DMA to the UPA bus, the IOMMU maps the PCI address into the appropriate UPA physical address. The IOMMU keeps the 16 most recently used translations in a TLB, and automatically performs hardware tablewalks on TLB misses. There is a single IOMMU supporting both PCI busses. Only a single translation can be in progress at a time, and during tablewalks, translations from the other bus segment will be delayed. * Streaming Cache: The Streaming Cache (STC) is used to accelerate PCI DMA activity. For DMA reads, the STC will speculatively prefetch 64-byte cache lines. For DMA writes, the STC buffers up 64-byte lines before sending to the UPA interface. There are two separate STC blocks in U2P, one associated with each PBM block. Each STC contains storage for 16 virtual address tagged entries and their data, which is stored in 64-byte lines, allocated on a least recently used basis.
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Interrupt block Mondo Dispatch Unit (MDU): In the Sun-4U architecture, interrupts to a processor are sent as packets on the UPA bus. The MDU in U2P is a system resource for generating such packets. The MDU accepts interrupt requests from the UPA slave ports, PCI busses and internal U2P sources and dispatches interrupt packets to the UPA. Internal Control * Merge Buffer: In order to allow sub-line writes into a 64-byte memory line, it is necessary to perform a read-modify-write operation on the UPA. The Merge Buffer is responsible for generating the correct UPA read, merging the partial line, and writing the whole block to the UPA. * PIO Control: Decodes slave requests from the UPA_A request FIFO, arbitrates for the appropriate resource and dispatches the request. * Bus Control: This is an internal arbiter shared by the PIO Control and DMA Control blocks. It schedules the use of the main internal data paths. * DMA Control: Arbitrates and decodes requests from internal DMA sources (PBM, STC, IOMMU, MDU), and arbitrates for the appropriate UPA FIFO. Miscellaneous * Timer/Counter: Contains two identical 32-bit timer-counters as specified by the Sun-4U architecture. Used for system scheduling and profiling. * JTAG Control: Provides the necessary control for the standard IEEE 1149.1 JTAG port, as well as additional scan based features that are useful for debugging purposes.
PCI Address Map Overview
Complete information on address maps and other software visible features of U2P can be found in the Programmer's Model chapter of the U2P Users Manual. A simplified diagram showing PIO and normal DVMA address spaces is in Figure 4.
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1.f000.0000
PROM via PCIO DVMA PCI B Mem Space
xxx0.0000
Unused
8000.0000 1.8000.0000
PCI A Mem Space U2P IOMMU
PCI B Space
0000.0000 1.0000.0000
PCI bus B memory space
DVMA
Unused
xxx0.0000 0.0202.0000 0.0201.0000 0.0200.0000 0.0100.0000
Unused PCI B I/O Space PCI A I/O Space PCI A&B Config Space U2P internal regs UPA Address PCI A Space
0000.0000 8000.0000
0.0000.0000
U2P UPA address space
PCI bus A memory space
Figure 4. PIO and DVMA address spaces
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SIGNAL DESCRIPTION
Pin naming conventions
* Active low signals are denoted by an underscore or underscore L, following the signal name, examples: B_CBE_[0] and UPA_CLK_L. * Direction is input (I), output (O), and bidirectional (IO). TABLE 1: Signal Name Prefixes
Functional Block PCI66 Bus (66MHz) PCI Bus (33MHz) UPA bus JTAG Port A_ B_ UPA_ PSY_T Prefix
Pin Summary
TABLE 2: Pin Count
Section UPA Interface PCIA Interface PCIB Interface Clock inputs Miscellaneous Test Signal Total Power/Ground Total Pins 130 97 96 5 11 5 344 112 456 Including 8 special Power/Ground Pins What It Includes UPA Master/Slave/Interrupter 64 bit interface 66MHz, 64 bit PCI interface, shared PCI Reset 33MHz, 64 bit PCI interface UPA, U2P core, Timer clocks and bypass Interrupts, reset, ext/int_event JTAG port and diagnostics
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Pinout by Pin Number
TABLE 3: PBGA Pinout
Signal Name VDD VSS ECC_VLD UPA_SRLY[2] VDD VSS UPA_CR UPA_AP UPA_A[3] VDD VSS UPA_A[14] UPA_A[19] UPA_A[24] UPA_A[29] VSS VDD INT_NUM[4] BOOT_BUS PCI_RST_ VSS VDD VDD5 A_AD[2] VSS VDD VSS UPA_ECC[5] UPA_SRLY[0] UPA_SRLY[4] UPA_PRLY[1] UPA_PRLY[3] UPA_RIN[0] UPA_A[0] UPA_A[4] Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 IO I I O O I IO IO BN02Z24S BIN02S BIN02S BOZ24S BOZ24S BIN02S BN02Z24S BN02Z24S UPA ECC bus UPA system reply UPA system reply UPA port reply UPA port reply UPA request in UPA address UPA address IO NVDD5P PCIMXI21 PCIA input diode clamp reference voltage (note 1) PCIA address/data bus I I O B5IN03S BIN06S PCI21MUS Interrupt number 1= boot device on PCIB, 0= boot device on PCIA PCI reset IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S UPA address UPA address UPA address UPA address I IO IO BIN02S BN02Z24S BN02Z24S UPA SC request UPA address parity UPA address I I BIN02S BIN02S UPA ECC is valid UPA system reply Direction Cell Type Description
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TABLE 3: PBGA Pinout (Continued)
Signal Name UPA_A[8] UPA_A[11] UPA_A[15] UPA_A[20] UPA_A[23] UPA_A[28] UPA_A[32] UPA_RST_L INT_NUM[3] EXT_EVENT INT_EVENT UPA_CLK UPA_BYPASS PSYCLOPS_CLK A_AD[1] A_AD[3] VSS UPA_ECC[4] UPA_ECC[3] UPA_ECC[7] UPA_SRLY[1] UPA_DTST UPA_PRLY[2] UPA_ARBRST_L UPA_RIN[2] UPA_A[2] UPA_A[6] UPA_A[10] UPA_A[13] UPA_A[18] UPA_A[25] UPA_A[30] UPA_A[33] INT_NUM[1] INT_NUM[5] PSY_TMS VDDA-VA1 Ball B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 IO IO IO I I O I I IO IO IO IO IO IO IO IO I I I BN02Z24S BN02Z24S BN02Z24S BIN02S BIN02S BOZ24S BIN02S BIN02S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S B5IN03S B5IN03S PINA02S NVDDAN UPA ECC bus UPA ECC bus UPA ECC bus UPA system reply UPA data stall UPA port reply UPA arbitration reset UPA request in UPA address UPA address UPA address UPA address UPA address UPA address UPA address UPA address Interrupt number Interrupt number JTAG Test mode select PLL 3.3V supply, filtered Direction IO IO IO IO IO IO IO I I IO O I I I IO IO Cell Type BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PINX02S B5IN03S PNAXZ24S BOZ24S BIED03S BIN06NA BIN02NA PCIMXI21 PCIMXI21 UPA address UPA address UPA address UPA address UPA address UPA address UPA address UPA reset. Main U2P reset. Interrupt number External event interrupt Internal event interrupt UPA 100MHz input clock (pos, PECL) UPA PLL bypass 66MHz main clock PCIA address/data bus PCIA address/data bus Description
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TABLE 3: PBGA Pinout (Continued)
Signal Name VSSA-VS1 VDDA-VA2 A_AD[0] A_AD[6] A_AD[8] A_AD[7] UPA_ECC[1] UPA_DB[63] UPA_ECC[2] VSS UPA_PRLY[0] UPA_PRLY[4] UPA_RIN[1] UPA_A[1] UPA_A[5] UPA_A[9] UPA_A[12] UPA_A[16] UPA_A[21] UPA_A[22] UPA_A[27] UPA_A[31] UPA_A[34] INT_NUM[2] VDD5 PSY_TRST_L UPA_CLK_L PSY_BYPASS VSS A_AD[9] A_AD[12] A_AD[10] VDD UPA_DB[60] UPA_DB[62] UPA_DB[61] VDD Ball C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 IO IO IO BN02Z24S BN02Z24S BN02Z24S UPA data bus UPA data bus UPA data bus IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIA address/data bus PCIA address/data bus PCIA address/data bus I I I O O I IO IO IO IO IO IO IO IO IO IO I BOZ24S BOZ24S BIN02S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S B5IN03S NVDD5P PINA02S BIED03S BIN06NA UPA port reply UPA port reply UPA request in UPA address UPA address UPA address UPA address UPA address UPA address UPA address UPA address UPA address UPA address Interrupt number 5V input diode clamp reference voltage (note 2) JTAG Test reset UPA 100MHz input clock (neg, PECL) PSYCLK PLL bypass IO IO IO IO IO IO IO Direction Cell Type NVSSAN NVDDAN PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S PLL ground PLL 3.3V supply, filtered PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA ECC bus UPA data bus UPA ECC bus Description
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TABLE 3: PBGA Pinout (Continued)
Signal Name B_CPU_GNT_ VSS UPA_SRLY[3] UPA_ROUT UPA_AV VDD UPA_A[7] UPA_A[17] UPA_A[26] INT_NUM[0] VDD PSY_TCLK PSY_TDO PSYCLOPS_CLKR VSS A_AD[4] VDD A_AD[14] A_AD[13] A_AD[15] VDD VSS UPA_DB[58] UPA_DB[59] UPA_DB[57] UPA_ECC[6] A_AD[5] A_AD[18] A_AD[16] A_AD[17] VSS UPA_DB[54] UPA_DB[53] UPA_DB[56] UPA_DB[52] VSS VSS Ball E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S UPA data bus UPA data bus UPA data bus UPA data bus IO IO IO IO IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 UPA data bus UPA data bus UPA data bus UPA ECC bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIA address/data bus PCIA address/data bus PCIA address/data bus IO PCIMXI21 PCIA address/data bus I O I BIN02S B5OZ10S REFPAD JTAG Test clock JTAG Test data output 66MHz clock reference pad to connect ext cap IO IO IO I BN02Z24S BN02Z24S BN02Z24S B5IN03S UPA address UPA address UPA address Interrupt number I O IO BIN02S BOZ24S BN02Z24S UPA system reply UPA request out UPA address valid Direction O Cell Type BOZ24S Description PCIB internal grant (debug only)
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TABLE 3: PBGA Pinout (Continued)
Signal Name A_AD[23] A_AD[19] A_AD[22] A_AD[21] UPA_DB[49] UPA_DB[48] UPA_DB[51] UPA_DB[47] UPA_ECC[0] A_AD[11] A_AD[28] A_AD[24] A_AD[27] A_AD[26] UPA_DB[45] UPA_DB[44] UPA_DB[46] UPA_DB[43] UPA_DB[55] A_AD[20] A_AD[32] A_AD[29] A_AD[31] A_AD[30] VDD UPA_DB[40] UPA_DB[42] UPA_DB[39] UPA_DB[50] A_AD[25] A_AD[36] A_AD[33] A_AD[35] VDD VSS UPA_DB[37] UPA_DB[38] Ball G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 IO IO BN02Z24S BN02Z24S UPA data bus UPA data bus IO IO IO IO IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 UPA data bus UPA data bus UPA data bus UPA data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus Direction IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Cell Type PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 Description PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA data bus UPA data bus UPA data bus UPA data bus UPA ECC bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA data bus UPA data bus UPA data bus UPA data bus UPA data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus
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TABLE 3: PBGA Pinout (Continued)
Signal Name UPA_DB[36] VDD VSS VSS VSS VSS VSS VSS VDD A_AD[39] A_AD[37] A_AD[38] VSS UPA_DB[34] UPA_DB[33] UPA_DB[35] UPA_DB[32] UPA_DB[41] VSS VSS VSS VSS VSS VSS A_AD[34] A_AD[43] A_AD[40] A_AD[42] A_AD[41] UPA_DB[29] UPA_DB[28] UPA_DB[30] UPA_DB[27] UPA_DB[31] VSS VSS VSS Ball L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 IO IO IO IO IO IO IO IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA data bus UPA data bus UPA data bus UPA data bus UPA data bus IO IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S UPA data bus UPA data bus UPA data bus UPA data bus UPA data bus IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIA address/data bus PCIA address/data bus PCIA address/data bus Direction IO Cell Type BN02Z24S UPA data bus Description
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TABLE 3: PBGA Pinout (Continued)
Signal Name VSS VSS VSS A_AD[44] A_AD[48] A_AD[45] A_AD[47] A_AD[46] UPA_DB[24] UPA_DB[25] UPA_DB[23] UPA_DB[26] UPA_DB[22] VSS VSS VSS VSS VSS VSS A_AD[53] A_AD[49] A_AD[52] A_AD[50] A_AD[51] UPA_DB[19] UPA_DB[20] UPA_DB[18] UPA_DB[21] UPA_DB[12] VSS VSS VSS VSS VSS VSS A_AD[63] A_AD[54] Ball N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 IO IO PCIMXI21 PCIMXI21 PCIA address/data bus PCIA address/data bus IO IO IO IO IO IO IO IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA data bus UPA data bus UPA data bus UPA data bus UPA data bus IO IO IO IO IO IO IO IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus PCIA address/data bus UPA data bus UPA data bus UPA data bus UPA data bus UPA data bus Direction Cell Type Description
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TABLE 3: PBGA Pinout (Continued)
Signal Name A_AD[57] A_AD[55] A_AD[56] VSS UPA_DB[16] UPA_DB[15] UPA_DB[17] VDD VSS VSS VSS VSS VSS VSS VDD A_AD[58] A_AD[60] A_AD[59] VSS VDD UPA_DB[13] UPA_DB[11] UPA_DB[14] UPA_DB[3] VDD5 A_AD[61] A_CBE_[0] A_AD[62] VDD UPA_DB[8] UPA_DB[9] UPA_DB[7] UPA_DB[10] VDD5 A_ACK64_ A_CBE_[1] A_CBE_[4] Ball R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 IO IO IO IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S NVDD5P PCIMXI21 PCIMXI21 PCIMXI21 UPA data bus UPA data bus UPA data bus UPA data bus 5V input diode clamp reference voltage (note 2) PCIA 64bit ACK PCIA command/byte enable bus PCIA command/byte enable bus IO IO IO IO IO IO IO BN02Z24S BN02Z24S BN02Z24S BN02Z24S NVDD5P PCIMXI21 PCIMXI21 PCIMXI21 UPA data bus UPA data bus UPA data bus UPA data bus PCIA input diode clamp reference voltage (note 1) PCIA address/data bus PCIA command/byte enable bus PCIA address/data bus IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIA address/data bus PCIA address/data bus PCIA address/data bus IO IO IO BN02Z24S BN02Z24S BN02Z24S UPA data bus UPA data bus UPA data bus Direction IO IO IO Cell Type PCIMXI21 PCIMXI21 PCIMXI21 Description PCIA address/data bus PCIA address/data bus PCIA address/data bus
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TABLE 3: PBGA Pinout (Continued)
Signal Name A_CBE_[2] A_CBE_[3] UPA_DB[4] UPA_DB[5] UPA_DB[2] UPA_DB[6] B_AD[56] A_IDSEL[3] A_CBE_[5] A_PAR A_CBE_[6] A_CBE_[7] TMR_CLK UPA_DB[0] B_CPU_REQ_ UPA_DB[1] VSS VSS A_PAR64 A_TRDY_ A_FRAME_ A_REQ64_ VSS B_AD[62] B_AD[61] B_AD[63] B_AD[50] A_REQ_[0] A_IRDY_ A_STOP_ PSY_TDI VSS VDD B_AD[60] B_AD[58] B_AD[59] VDD Ball V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 IO IO IO PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus IO IO IO IO I IO IO I PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21MIN PCIMXI21 PCIMXI21 PINA02N PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIA bus request PCIA initiator ready PCIA stop JTAG Test data in IO IO IO IO PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 PCIA AD[63:32]/CBE[7:4] even parity PCIA target ready PCIA frame PCIA 64 bit request Direction IO IO IO IO IO IO IO O IO IO IO IO I IO O IO Cell Type PCIMXI21 PCIMXI21 BN02Z24S BN02Z24S BN02Z24S BN02Z24S PCI21LUS PCI21MUN PCIMXI21 PCIMXI21 PCIMXI21 PCIMXI21 B5IN03N BN02Z24S PCI21LUS BN02Z24S Description PCIA command/byte enable bus PCIA command/byte enable bus UPA data bus UPA data bus UPA data bus UPA data bus PCIB address/data bus PCIA Config cycle chip selects PCIA command/byte enable bus PCIA AD[31:0]/CBE[3:0] even parity PCIA command/byte enable bus PCIA command/byte enable bus 10MHz Timer input clock UPA data bus PCIB internal request (debug only) UPA data bus
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TABLE 3: PBGA Pinout (Continued)
Signal Name B_AD[49] VSS B_AD[43] B_AD[34] B_AD[29] VDD B_AD[20] B_AD[10] B_AD[1] B_CBE_[0] VDD B_PAR64 B_GNT_[2] B_SERR_ VSS A_REQ_[1] VDD A_IDSEL[0] A_IDSEL[1] A_DEVSEL_ VDD B_AD[55] B_AD[57] B_AD[54] VSS B_AD[40] B_AD[36] B_AD[31] B_AD[26] B_AD[22] B_AD[18] B_AD[15] B_AD[11] B_AD[6] B_AD[5] B_AD[0] B_CBE_[5] Ball AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 IO IO IO IO IO IO IO IO IO IO IO IO PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB command/byte enable bus IO IO IO PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus O O IO PCI21MUN PCI21MUN PCIMXI21 PCIA Config cycle chip selects PCIA Config cycle chip selects PCIA device select I PCI21MIN PCIA bus request IO O I PCI21LUS PCI21LUS PCI21LIS PCIB AD[63:32]/CBE[7:4] even parity PCIB bus grant PCIB system error IO IO IO IO PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB command/byte enable bus IO IO IO PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus Direction IO Cell Type PCI21LUS Description PCIB address/data bus
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TABLE 3: PBGA Pinout (Continued)
Signal Name B_CBE_[2] B_REQ64_ B_STOP_ B_GNT_[5] B_GNT_[0] B_REQ_[2] VSS A_GNT_[0] A_IDSEL[2] A_PERR_ B_AD[52] B_AD[53] B_AD[51] B_AD[45] B_AD[41] B_AD[38] B_AD[35] B_AD[30] B_AD[25] B_AD[21] B_AD[17] B_AD[14] B_AD[9] B_AD[2] B_CBE_[6] B_CBE_[3] B_ACK64_ B_IRDY_ B_PAR B_GNT_[1] B_REQ_[4] B_REQ_[1] A_CLK A_REQ_[2] A_GNT_[1] A_GNT_[2] VSS Ball AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O I I I I O O PCI21MUN PCI21MUN PCIMXI21 PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LIS PCI21LIS PCI21MIN PCI21MIN PCI21MUN PCI21MUN PCIA bus grant PCIA Config cycle chip selects PCIA bus parity error PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB command/byte enable bus PCIB command/byte enable bus PCIB 64bit ACK PCIB initiator ready PCIB AD[31:0]/CBE[3:0] even parity PCIB bus grant PCIB bus request PCIB bus request PCIA bus clock phase detect (note 3) PCIA bus request PCIA bus grant PCIA bus grant Direction IO IO IO O O I Cell Type PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LIS Description PCIB command/byte enable bus PCIB 64 bit request PCIB stop PCIB bus grant PCIB bus grant PCIB bus request
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TABLE 3: PBGA Pinout (Continued)
Signal Name B_AD[48] B_AD[46] B_AD[42] B_AD[39] B_AD[37] B_AD[32] B_AD[27] B_AD[23] B_AD[19] B_AD[16] B_AD[12] B_AD[7] B_AD[4] VDD5 B_CBE_[4] B_CBE_[1] B_FRAME_ B_DEVSEL_ B_GNT_[4] B_REQ_[5] B_REQ_[3] B_REQ_[0] A_SERR_ A_GNT_[3] VSS VDD VSS B_AD[47] B_AD[44] VDD VSS B_AD[33] B_AD[28] B_AD[24] VDD VSS B_AD[13] Ball AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 IO PCI21LUS PCIB address/data bus IO IO IO PCI21LUS PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus PCIB address/data bus IO IO PCI21LUS PCI21LUS PCIB address/data bus PCIB address/data bus IO IO IO IO O I I I I O Direction IO IO IO IO IO IO IO IO IO IO IO IO IO Cell Type PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS NVDD5P PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LUS PCI21LIS PCI21LIS PCI21LIS PCI21MIN PCI21MUN Description PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus PCIB address/data bus 5V input diode clamp reference voltage (note2) PCIB command/byte enable bus PCIB command/byte enable bus PCIB frame PCIB device select PCIB bus grant PCIB bus request PCIB bus request PCIB bus request PCIA system error PCIA bus grant
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TABLE 3: PBGA Pinout (Continued)
Signal Name B_AD[8] B_AD[3] B_CBE_[7] VSS VDD B_TRDY_ B_PERR_ B_GNT_[3] VSS VDD B_CLK A_REQ_[3] VSS VDD Ball AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 I I PCI21LIS PCI21MIN PCIB bus clock phase detect (note 3) PCIA bus request IO IO O PCI21LUS PCI21LUS PCI21LUS PCIB target ready PCIB bus parity error PCIB bus grant Direction IO IO IO Cell Type PCI21LUS PCI21LUS PCI21LUS Description PCIB address/data bus PCIB address/data bus PCIB command/byte enable bus
(1) PCIA VDD5 - For proper noise immunity, tie to 3.3V for PCI cards which use 3V signalling, tie to 5V for PCI cards which use 5V signalling. (2) MISC VDD5 - Tie to 5V. Internal to U2P these three pins are part of a single voltage rail. (3) A_CLK, B_CLK - used by U2P to determine the clock phase of a given PCIA, PCIB cycle, respectively. Required since either bus can be running at half the frequency of the internal clock.
Input Buffers
U2P implements four types of input buffers: 1. TTL UPA and JTAG inputs 2. 5V tolerant TTL INT_NUM and TMR_CLK inputs 3. PCI PCI inputs (5V tolerant) 4. PECL UPA_CLK and UPA_CLK_L inputs Note: Refer to the Lucent Technologies HL350C 3 Volt 0.35 micron. CMOS Standard-Cell Library data book for full specification on the buffer types. Generally an input buffer is 5 Volt tolerant if it is a PCI buffer (and VDD5 is tied to 5 Volts) or if it is of type B5xxxx.
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ELECTRICAL SPECIFICATIONS
Absolute Maximum ratings
Stresses beyond those listed in the following table may cause physical damage to the device and should be avoided. TABLE 4: Absolute Maximum Ratings
Symbol VDD VDD5 Vin, Vout I Tstg TCM Pd Parameter DC Power Supply Voltage DC Power Supply Voltage DC Input, Output Voltage DC Current Drain per VDD and VSS pair Storage Temperature Maximum Case Temperature Power dissipation Limit -0.5 to 5.0 (note 1) -0.5 to 7.0 (note 1) VSS - 0.3 to VDD + 0.3 (note 2) 100 -40 to 125 85 3.0 Unit V V V mA C C Watts
(1) The 5V supply should be powered up before the 3V supply. In any case the 5V supply should never be more than 0.4V below the 3V supply. (2) Except 5V tolerant PCI buffers where VIN max = VDD5 + 0.3V
Recommended Operating Conditions
TABLE 5: Recommended Operating Conditions
Symbol VDD VDD5 Vin, Vout TCO Parameter DC Power Supply Voltage PCI input reference voltage DC Input, Output Voltage Operating CaseTemperature Limit 3.135 to 3.465 4.75 to 5.25 when VDD5 = 5V 3.135 to 3.465 when VDD5 = 3.3V 0 to VDD 0 to 70 V C Unit V V
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DC Characteristics
TABLE 6: DC Characteristics
Symbol Vil Parameter Input Low Voltage TTL PCI PECL Vih Input High Voltage TTL PCI PECL Vol Output Low Voltage TTL PCIA (DC) PCIB (DC) Voh Output High Voltage TTL PCIA (DC) PCIB (DC) Iin Ioz Cin Cout Input Leakage Tri-state outputs Input Capacitance Output Capacitance Voh = VSS or VDD Any input/bidir buffer Any output buffer 2.5 2.5 Ioh = -4, -8, -16 mA Ioh = - 0.5 mA Ioh = - 2.0 mA 2.4 0.9 VDD 2.4 1 9 6 6 V V V A A pF pF Iol = -4, -8, -16 mA Iol = 1.5 mA Iol = 6.0 mA 0.4 0.1 VDD 0.55 V V V UPA_CLK, UPA_CLK_L 2.0 0.5VDD VDD -1.165 VDD +0.5 V V UPA_CLK, UPA_CLK_L -0.3 0.8 0.3 VDD VDD -1.475 V V Conditions Min Max Unit
Environmental ELectrical Protection
TABLE 7: Environmental Electrical Protection
ESD Minimum 2KV Latch UP Minimum 150 mA
AC Characteristics
All UPA inputs and outputs are referenced to the PECL clock input UPA_SYS_CLK + and UPA_SYS_CLK -. This clock input also controls an on-chip Phase Lock Loop (PLL). All UPA inputs and outputs are clocked by the rising edge of CLK + at the crossover between CLK +and CLK -, where both signals are at the same voltage. All UPA inputs are applied with a rise and fall time of 1.0 ns (nanosecond). PCI inputs and outputs are referenced to PCIA_CLK and PCIB_CLK respectively. Other U2P internal blocks run at the PSYCLOPS_CLK, which is fixed at 66.7 MHz (15ns). There is a synchronization boundary between the UPA interface block and other internal blocks.
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The JTAG signals are referenced to JTAG Test Clock PSY_TCLK. They are asynchronous signals with respect to UPA and PCI signals. The design of the U2P ASIC was done under the conditions specified in TABLE 8:. TABLE 8: Internal Timing Characteristics
Symbol upaclk psyclk clkskew Parameter Operating Frequency, UPA_CLK Operating Frequency, PSYCLOPS_CLK Internal Skew and Jitter Conditions 3.15V, Tj = 85C 3.15V, Tj = 85C - 0.5 Min Max 100 66 0.5 Unit MHz MHz ns
Note: Worst Case Slow Motive claims operation of the two clock domains at the following max frequencies; upaclk = 105.9 MHz, psyclk = 67.5 MHz. PLL Clock Distribution and Characteristics Figure 5. shows the PLL scheme inside the U2P.
BIED03T CLK+ CLK- PLL_BYPASS JTAG_TCK FBIN P N FBOUT Z
PLL1XSF FBCLK1X REFCLK CLK1X BYPASS
Clock MUX
Clock Buffers
Internal Clock
Clock select from TAP controller
Figure 5. PLL Clock Distribution Circuitry . TABLE 9: PLL Characteristics
Symbol upaclk psyclk clkskew Parameter Operating Frequency, UPA_CLK Operating Frequency, PSYCLOPS_CLK Internal Skew and Jitter 125MHz 100MHz 66MHz 35MHz Conditions Min 40 40 Max 125 85 400 450 500 600 Unit MHz MHz ps ps ps ps
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Note: If the clock is stopped after the PLL is locked and the feedback loop is not broken, the PLL will go to the low frequency state, i.e., 4-10MHz. If the clock recovers and resumes normal operation the PLL will catch up with the input clock within 250 sec. Note: If the feedback loop is broken and the input frequency is higher than the feedback frequency, there will be run-away i.e., PLL will go to high frequency state. The only way to recover is to bring BYPASS up for 200 sec.
UPA Timing
A timing diagram is shown in Figure 6. as a reference for the data in the timing tables. UPA input and output signals are referenced to the rising edge of UPA_CLKTiming Diagrams
tcycle tHC tRC tLC 10% tFC 90%
Clock
Clock
tSU
1.5V
1.5V
tH 1.5V 1.5V tVO tCO
Input Signal
Output Signal
Parameter Definitions
tSU : Required setup time of a chip input referenced to a given (clock) edge. tH : Required hold time of a chip input referenced to a given (clock) edge. tCO : Guaranteed propagation time of an output referenced to a given (clock) edge. tVO : Guaranteed output hold time of an output referenced to a given (clock) edge. tHC : Required clock high time. tLC : Required clock low time. tRC : Required clock rise time. tFC: Required clock fall time.
Figure 6. Timing Waveforms
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TABLE 10: UPA_CLK Characteristics
Signal Name tcycle tHC tLC tRC tFC Description Clock cycle time Clock high time Clock low time Clock rise time Clock fall time DC Levels VIL VDD - 1.165 Min 40 4.4 4.4 600 600 Max 100 Unit MHz ns ns ps ps
The maximum skews between the rising edge and the falling edge of UPA_CLK + and UPA_CLK - are 50 ps. That is, the rising edge of UPA_CLK + can be shared at most 50 ps after/before the falling edge of UPA_CLK -. The falling edge of UPA_CLK + can be skewed at most 50 ps after/before the rising edge of UPA_CLK -.
TABLE 11: UPA Input and Output Timing
Signal Name tSU tH tCO tVO tRI tFI Description Input Setup Time Input Hold Time Output Propagation Time Output Hold Time Input Rise Time Input Fall Time 55pf 55pf Condition Min 2.1 0.5 0 0.5 1.0 1.0 4.1 Max Unit ns ns ns ns ns ns
Note: Worst Case Slow Motive shows tco_max = 4.1 ns @ 70 pf.
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PCI Timing
T_cyc clock Input Output T_val T_on Tri_Output T_off T_high T_hold T_low T_su
Figure 7. AC Timing Parameters
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TABLE 12: PCIA AC Timing Characteristics
Symbol T_cyc T_high T_low PCI Inputs T_su T_su(ptp) T_hold PCI Outputs @ 66 MHz T_val T_val(ptp) T_on T_off PCI Outputs @ 33 MHz T_val T_val(ptp) T_on T_off pci_clk to Signal Valid Delay - bused pci_clk to Signal Valid Delay - pci_req_l Float to Active Delay Active to Float Delay (See Note) (See Note) (See Note) 2 2 2 28 11 12 ns ns ns ns pci_clk to Signal Valid Delay - bused pci_clk to Signal Valid Delay - pci_req_l Float to Active Delay Active to Float Delay (See Note) (See Note) (See Note) 1 1 1 14 6 6 ns ns ns ns Input Setup Time to pci_clk - bused Input Setup Time to pci_clk - pci_req_ Input Hold Time from pci_clk 5 5 0 ns ns ns Parameter pci_clk Cycle Time pci_clk High Time pci_clk Low Time Conditions Min 15 6 6 Max 30 Unit ns ns ns
Note: Measurement conditions for Tval (max) rise = 25 Ohm/10pf parallel to ground, and for Tval (max) fall = 10pf to ground, 25 Ohm to VDD. Refer to PCI 2.1 Specification, Chapter 7, for full AC specifications on output buffers.
TABLE 13: PCIB AC Timing Characteristics
Symbol T_cyc T_high T_low PCI Inputs T_su T_su(ptp) T_hold PCI Outputs T_val pci_clk to Signal Valid Delay - bused (See Note) 2 11 ns Input Setup Time to pci_clk - bused Input Setup Time to pci_clk - pci_req_ Input Hold Time from pci_clk 7 12 0 ns ns ns Parameter pci_clk Cycle Time pci_clk High Time pci_clk Low Time Conditions Min 30 11 11 Max DC Unit ns ns ns
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TABLE 13: PCIB AC Timing Characteristics (Continued)
Symbol T_val(ptp) T_on T_off Parameter pci_clk to Signal Valid Delay - pci_req_l Float to Active Delay Active to Float Delay Conditions (See Note) (See Note) Min 2 2 28 Max 12 Unit ns ns ns
Note: Measurement conditions for Tval (max) rise = 25 Ohm/10pf parallel to ground, and for Tval (max) fall = 10pf to ground, 25 Ohm to VDD. Refer to PCI 2.1 Specification, Chapter 7, for full AC specifications on output buffers.
A_CLK, B_CLK Timing
T_cyc PSYCLOPS_CLK T_duty A_CLK T_skew B_CLK
Figure 8. A_CLK, B_CLK AC timing parameters
TABLE 14: A_CLK, B_CLK timing parameters
Symbol T_cyc T_skew T_duty Parameter PSYCLOPS_CLK cycle time clock skew to PSYCLOPS_CLK A_CLK, B_CLK duty cycle requirement Conditions Min 15 -750 Tcyc/2 -750 Max 25 +750 Tcyc/2 +750 Unit ns ps ps
JTAG Timing TABLE 15: JTAG Timing Characteristics
Symbol JTAG clock T_cyc JTAG Inputs JTAG clk Cycle Time 100 ns Parameter Conditions Min Max Unit
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TABLE 15: JTAG Timing Characteristics (Continued)
Symbol T_su(rx) T_hld(rx) T_val Parameter JTAG Inputs Setup Time to jtag_clk JTAG Inputs Hold Time to jtag_clk JTAG Output Valid Time from jtag_clk negative edge 30pF Load Conditions Min 30 20 49 Max Unit ns ns ns
MECHANICAL INFORMATION
Package Marking (Production Version)
STP2223BGA 100-4611-05 Lucent Technologies M-1298B5 YYWWL XXXXKN# (Sun logo) SUN
Sun Part Number
YYWW L XXXX KN #
Year and Work Week Assembly site Wafer Lot Clean Room number Chip version
Thermal Data and Characteristics
TABLE 16: Thermal Characteristics
Package type 456 PBGA/4 layers Theta_JA 12.8 (1) 11.8 (2) Theta_JC 3.7 Unit C/W
(1) 0 LFM, no heatsink, 4W thermal die, 20C ambient, sea level (2) 100 LFM, no heatsink, 4W thermal die, 20C ambient, sea level
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Package Drawing
1.63 TYP 25 SPACES @ 1.27 = 31.75 1.63 TYP
26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** ************************** BOTTOM VIEW ************************** ************************** ************************** ************************** ************************** ************************** ************************** **************************
SOLDER BALL GRID ARRAY COORDINATES ARE FOR REFERENCE ONLY A1 INDICATOR (GOLD PLATED)
2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 3 4 5 6 7 8 10 12 14 16 18 20 22 24 26 9 11 13 15 17 19 21 23 25
SOLDER BALL GRID ARRAY COORDINATES ARE FOR REFERENCE ONLY A1 INDICATOR (UNDER COVER COAT) NOTES: 1. Seating Plane is "best Fit" plane as determined by coplanarity measurement equipment. 2. The flatness of the overmold surface in the center 12 x 12 mm area shall be within 0.13 mm.
25 SPACES @ 1.27 = 31.75
All Measurements in Millimeters
0.75 0.15 DIA TYP AFTER REFLOW
// 0.15 C 1.73 0.09 0.56 0.04 --C-- 0.60 0.10 TYP
22.00 REF. APPROX TYP 4 PLACES
35.00 0.20 SQUARE
SEE NOTE 2 TOP VIEW
30 APPROX ALL SIDES
30.00 +0.70 -0.00 SQUARE
17.50 0.20
2.33 0.19 0.19 C SEATING PLANE SEE NOTE 1
D
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ORDERING INFORMATION
Part Number STP2223BGA Speed Description UPA to PCI Interface
Document Part Number: 802-7834-02
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