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Quad Lane Extender
QLx411GRx
The QLx411GRx is a settable quad receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 11.3Gb/s such as InfiniBand (SDR, DDR and QDR) and 40G Ethernet (40GBase-CR4). The QLx411GRx compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to at least 10m on 28AWG cable. The small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. The four equalizing filters within the QLx411GRx can each be set to provide optimal signal fidelity for a given media and length. The compensation level for each filter is set by two external control pins. Operating on a single 1.2V power supply, the QLx411GRx enables per channel throughputs of 10Gb/s to 11.3Gb/s while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, and 2.5Gb/s. The QLx411GRx uses current mode logic (CML) inputs/outputs and is packaged in a 4mmx7mm 46 lead QFN. Individual lane LOS support is included for module applications.
QLx411GRx
Features
* Supports data rates up to 11.3Gb/s * Low power (135mW per channel) * Low latency (<500ps) * Four equalizers in a 4mmx7mm QFN package for straight route-through architecture and simplified routing * Each equalizer boost is independently pin selectable * Supports 64b/66b encoded data - long run lengths * Line silence preservation * 1.2V supply voltage * Individual lane LOS support
Applications
* QSFP active copper cable modules * InfiniBand SDR, DDR and QDR * 40G Ethernet (40GBase-CR4) * XAUI and RXAUI * High-speed active cable assemblies * High-speed printed circuit board (PCB) traces
Benefits
* Thinner gauge cable * Extends cable reach greater than 3x * Improved BER
Typical Application Circuit
Active Copper Cable Assembly
10nF 1.2V Tx1[P,N] Tx2[P,N] Tx3[P,N] Tx4[P,N] 10nF 4 12 100pF
0.1F 0.1F
1.2V
Host Channel Adapter
12 4 100pF VDD EP CP LOS
0.1F
LOS CP EP VDD
0.1F 0.1F
8-Pair Differential 100 Twin-Axial Cable
IN1[P,N] IN2[P,N]
OUT1[P,N] OUT2[P,N]
0.1F 0.1F
Rx1[P,N] Rx2[P,N]
0.1F
SERDES or Switch
Rx1[P,N] Rx2[P,N]
OUT1[P,N] OUT2[P,N]
IN1[P,N] IN2[P,N]
SERDES or Switch
QLx411GRx
0.1F
QLx411GRx
Rx3[P,N] Rx4[P,N]
0.1F 0.1F
IN3[P,N] IN4[P,N] DT 100pF
OUT3[P,N] OUT4[P,N]
0.1F 0.1F
Rx3[P,N] Rx4[P,N] Tx1[P,N] Tx2[P,N] Tx3[P,N] Tx4[P,N]
0.1F 0.1F
OUT3[P,N] OUT4[P,N]
IN3[P,N] IN4[P,N] DT 100pF
1.2V
0.1F
1.2V 10nF
Fabric Switch
Connector Paddle Card
10nF
10m 28AWG
Connector Paddle Card
November 19, 2009 FN6989.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
QLx411GRx
Ordering Information
PART NUMBER (Note) QLX411RIQT7 QLX411RIQSR PART MARKING QLX411RIQ QLX411RIQ TEMP. RANGE (C) 0 to +70 0 to +70 PACKAGE (Pb-Free) 46 Ld QFN 7" Prod. Tape & Reel; Qty 1,000 46 Ld QFN 7" Sample Reel; Qty 100 PKG. DWG. # L46.4x7 L46.4x7
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Configuration
QLx411GRx (46 LD 4x7 QFN) TOP VIEW
CP1[A] CP1[B] CP2[A] CP4[A] CP2[B] 38 NC 37 OUT1[P] 36 OUT1[N] 35 VDD 34 OUT2[P] 33 OUT2[N] 32 VDD EXPOSED PAD (GND) 31 OUT3[P] 30 OUT3[N] 29 VDD 28 OUT4[P] 27 OUT4[N] 26 LOS3 25 LOS4 24 GND 16 17 18 19 20 21 22 23 CP3[A] CP3[B] CP4[B] NC NC NC NC
NC
NC
NC
46 45 44 43 42 41 40 39 DT IN1[P] IN1[N] VDD IN2[P] 1 2 3 4 5
IN2[N] 6 VDD 7 IN3[P] 8 IN3[N] 9 VDD 10 IN4[P] 11 IN4[N] 12 LOS1 13 LOS2 14 NC 15
2
NC
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Pin Descriptions
PIN NAME DT PIN NUMBER 1 DESCRIPTION Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output OUT[k] is muted when the power of the equalized version of IN[k] falls below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier. Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended.
IN1[P,N] VDD IN2[P,N] IN3[P,N] IN4[P,N] LOS1 LOS2 NC
2, 3
4, 7, 10, 29, 32, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to 35 ground is recommended for each of these pins for broad high-frequency noise suppression. 5, 6 8, 9 11, 12 13 14 15, 16, 18, 21, 38, 41, 44, 45, 46 19, 20 Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOS indicator 1. High output when equalized IN1 signal is below DT threshold. LOS indicator 2. High output when equalized IN2 signal is below DT threshold. Not connected: Do not make any connections to these pins.
CP3[A,B,]
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k resistor. This pin should be grounded. LOS indicator 4. High output when equalized IN1 signal is below DT threshold. LOS indicator 3. High output when equalized IN2 signal is below DT threshold. Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25k resistor. Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane.
CP4[A,B,]
22, 23
GND LOS4 LOS3 OUT4[N,P] OUT3[N,P] OUT2[N,P] OUT1[N,P] CP2[B,A]
24 25 26 27, 28 30, 31 33, 34 36, 37 39, 40
CP1[B,A]
42, 43
EXPOSED PAD
-
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QLx411GRx
Absolute Maximum Ratings
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Operating Ambient Temperature Range . . . . . . 0C to +70C Storage Ambient Temperature Range . . . . -55C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Operating Conditions
PARAMETER Supply Voltage Operating Ambient Temperature Bit Rate SYMBOL VDD TA NRZ data applied to any channel CONDITION MIN 1.1 0 2.5 TYP 1.2 25 MAX 1.3 70 11.3 UNITS V C Gb/s
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. PARAMETER Output LOW Logic Level Output HIGH Logic Level Input Current SYMBOL VOL VOH LOS[k] LOS[k] Current draw on digital pin, i.e., CP[k][A,B] CONDITION MIN 0 1000 30 TYP 0 MAX 250 VDD 100 UNITS mV mV A
Electrical Specifications
PARAMETER Supply Current Cable Input Amplitude Range DC Differential Input Resistance DC Single-Ended Input Resistance Input Return Loss (Differential) Input Return Loss (Common Mode) Input Return Loss (Com. to Diff. Conversion) Output Amplitude Range Differential Output Impedance Output Return Loss (Differential) Output Return Loss (Common Mode) Output Return Loss (Com. to Diff. Conversion)
Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. CONDITION MIN TYP 360 Measured differentially at data source before encountering channel loss Measured on input channel IN[k] Measured on input channel IN[k]P or IN[k]N 600 80 40 8 8 20 1200 100 50 1600 120 60 MAX UNITS mA mVP-P dB dB dB 2 2 2 1 NOTES
SYMBOL IDD VIN
SDD11 SCC11 SDC11
100MHz to 7.5GHz 100MHz to 7.5GHz 100MHz to 7.5GHz
VOUT
Measured differentially at OUT[k]P and OUT[k]N with 50 load on both output pins Measured on OUT[k]
450 80 8 8 20
600 105
650 120
mVP-P dB dB dB 2 2 2
SDD22 SCC22 SDC22
100MHz to 7.5GHz 100MHz to 7.5GHz 100MHz to 7.5GHz
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Electrical Specifications
PARAMETER Output Residual Jitter Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. (Continued) CONDITION 10Gb/s; Up to 10m 28AWG standard twin-axial cable (approx. -27dB @ 5GHz); 1200mVP-P VIN 1600mVP-P tr, tf 20% to 80% MIN TYP 0.25 MAX UNITS UI NOTES 1, 3, 4
SYMBOL
Output Transition Time Lane-to-Lane Skew Propagation Delay LOS Assert Time
35 50
ps ps ps s
5
From IN[k] to OUT[k] Time to assert Loss-of-Signal (LOS) indicator when transitioning from active data mode to line silence mode Time to de-assert Loss-of-Signal (LOS) indicator when transitioning from line silence mode to active data mode Time to transition from active data to line silence (muted output) on 20m 28AWG standard twin-axial cable at 5Gb/s Time to transition from line silence mode (muted output) to active data on 20m 28AWG standard twin-axial cable at 5Gb/s
500 50
6
LOS De-Assert Time
50
s
6
Data-to-Line Silence Response Time Line Silence-to-Data Response Time NOTES:
50
s
6
50
s
6
1. After channel loss, differential amplitudes at QLx411GRx inputs must meet the input voltage range specified in "Absolute Maximum Ratings" on page 4. 2. Temperature = +25C, VDD = 1.2V. 3. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS.
4. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 5. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
6. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude is 20mVP-P (differential) or less.
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Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched into the twin-ax cable using an SMA/CX4 adapter card. The chip evaluation board is connected to the output of the cable through another adapter card. The QLx411GRx output signal is then visualized on a scope to determine signal integrity parameters such as jitter (Note 7).
Pattern Generator
SMA Adapter Card
100 Twin-Axial Cable
SMA Adapter Card
QLx411GRx Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION SET UP
FIGURE 2. JITTER vs CABLE LENGTH AT 10Gb/s (BOOST LEVELS 0-3) NOTE:
FIGURE 3. QLx411GRx 10Gb/s OUTPUT FOR A 10M 28AWG CABLE
7. Prior to the tapeout, the data in Figures 2 and 3 represents simulations approximating the conditions of setup in Figure 1, not measured data.
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QLx411GRx
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx411GRx
Operation
The QLx411GRx is an advanced quad lane-extender for high-speed interconnects. A functional diagram of one of the four channels in the QLx411GRx is shown in Figure 4. In addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the QLx411GRx contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. The signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the Detection Threshold (DT) pin voltage. This function is intended to preserve periods of line silence ("quiescent state" in InfiniBand contexts). Furthermore, the output of the signal detect/DT comparator is used as a loss of signal (LOS) indicator to indicate the absence of a received signal. As illustrated in Figure 4, the core of each high-speed signal path in the QLx411GRx is a sophisticated equalizer followed by a limiting amplifier. The equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. Each equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver.
FIGURE 5. GAIN PROFILE FOR VARIOUS BOOST SETTINGS IN QLx411GRx
Control Pin Boost Setting
The connectivity of the CP pins is used to determine the boost level of each channel. Table 1 defines the mapping from the 2-bit CP word to the 5 possible boost levels.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CPPIN CONNECTIVITY CP[A] 25k 25k 25k Open Open CP[B] 25k Open 0 25k Open BOOST LEVEL 0 1 2 3 4
Individually Adjustable Equalization Boost
Each channel in the QLx411GRx features an independently settable equalizer for custom signal restoration. The flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5Gb/s to 11.3Gb/s. Because the boost level is externally set rather than internally adapted, the QLx411GRx provides reliable communication from the very first bit transmitted. There is no time needed for adaptation and control loop convergence. Furthermore, there are no pathological data patterns that will cause the QLx411GRx to move to an incorrect boost level.
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QLx411GRx
CML Input and Output Buffers
The input and output buffers for the high-speed data channels in the QLx411GRx are implemented using CML. Equivalent input and output circuits are shown in Figures 6 and 7.
Line Silence/Quiescent Mode
Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The QLx411GRx contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelityenhancing benefits of limiting amplification during active data transmission. Line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the voltage at the DT pin. When the amplitude falls below the threshold, the output driver stages are muted and held at their nominal common mode voltage1.
VDD IN[k] P 50
Buffer
LOS Indicator
Pins LOS[k] are used to output the state of the muting circuitry to serve as a loss of signal indicator for channel k. This signal is directly derived from the muting signal off the DT-threshold signal detector output. The LOS signal goes HIGH when the power signal is below the DT threshold and LOW when the power goes above the DT threshold. This feature is meant to be used in optical systems (e.g. QSFP) where there are no quiescent or electrical-idle states. In these cases, the DT threshold is used to determine the sensitivity of the LOS indicator.
50 IN[k] N
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR THE QLx411GRx
VDD
50
50 OUT[k] P OUT[k] N
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR THE QLx411GRx
1. The output common mode voltage remains constant during both active data transmission and output muting modes
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Typical Application Reference Design
Figure 8 shows reference design schematics for a QLx411GRx evaluation board with an SMA connector interface.
1.2V NC NC NC CP1[A] Detection threshold reference voltage 100pF 10nF EQ Boost Control for Channels 1 and 2 CP2[B]
39
CP1[B]
DT IN1[P] IN1[N] 1.2V IN2[P] IN2[N] 1.2V IN3[P] IN3[N] 1.2V IN4[P] IN4[N] LOS1 LOS2 Loss of signal indicator (Channels 1 and 2)
46
45
44
43
42
41
40
CP2[A]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CP3[A] CP4[B] CP3[B] CP4[A] 23
38 37 36 35 OUT1[P] OUT1[N] 1.2V OUT2[P] OUT2[N] 1.2V OUT3[P] OUT3[N] 1.2V OUT4[P] OUT4[N] LOS3 LOS4 GND
A
QLx411GRx
34 33 32 31 30 29 28 27 26 25 24
Loss of signal indicator (Channels 3 and 4)
NC
NC
NC
1.2V 100pF*
10nF
EQ Boost Control for Channels 3 and 4
QLx411GRx LANE EXTENDER
Reference Control Pin Mode
Quellan, Inc.
= SMA Connector Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35 (*100pF capacitor should be positioned closest to the pin) A) DC Blocking Capacitors = X7R or COG 0.1F (>6GHz bandwidth)
FIGURE 8. APPLICATION CIRCUIT FOR THE QLx411GRx EVALUATION BOARD SHOWING THE USE OF THE CONTROL PINS FOR SETTING THE EQUALIZER COMPENSATION LEVEL
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About Q:ACTIVE(R)
Intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. To address this, Intersil has developed its groundbreaking Q:ACTIVE(R) product line. By integrating its analog ICs inside cabling interconnects, Intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow's datacenters. This new technology transforms passive cabling into intelligent "roadways" that yield lower operating expenses and capital expenditures for the expanding datacenter. Intersil Lane Extenders allow greater reach over existing cabling while reducing the need for thicker cables. This significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6989.1 November 19, 2009
QLx411GRx
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09
2.80 4.00 A B 6 PIN 1 INDEX AREA 38 39 42X 0.40 46 6 PIN 1 INDEX AREA 1
7.00
5.60
5.50 0.1 Exp. DAP
24 (4X) 0.05 TOP VIEW SIDE VIEW 46X 0.20 4 0.10 M C A B 46X 0.40 23 2.50 0.1 Exp. DAP BOTTOM VIEW SEE DETAIL "X" 16
15
0.70 0.05
0.10 C SEATING PLANE 0.05 C SIDE VIEW
C
C
0.152 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X" ( 3.80 ) ( 2.50)
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. (46X 0.20) 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. ( 46 X 0.60) TYPICAL RECOMMENDED LAND PATTERN
2. ( 6.80 ) ( 5.50 ) ( 42X 0.40) 3. 4.
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FN6989.1 November 19, 2009

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