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HT82M75REW/HT82K75REW 2.4GHz Transceiver 8-Bit OTP MCU
Features
* Operating voltage: * Up to 40 bidirectional I/O lines with pull-high options * All I/O pins have falling and rising edge wake-up
fSYS= 6MHz: 1.8V~3.3V
* Internal 6MHz RC oscillator for fSYS * Power down and wake-up functions to reduce
function
* Single 16-bit internal timer with overflow interrupt
power consumption
* Two bit to define microcontroller system clock
and timer input
* Low voltage reset function (LVR) for DC_DC output
(fSYS/1, fSYS/2, fSYS/4)
* All instructions executed in one or two machine
controlled by configuration option
* Built-in DC/DC to provide stable 2.8V, 3.0V, 3.3V
cycles
* Table read instructions * 63 powerful instructions * 6-level subroutine nesting * Bit manipulation instruction * Program Memory: 4K15 * Data Memory: 1288~1608 * Watchdog Timer function
with error 5% selected by configuration options
* Low voltage detector (LVD) with levels
1.8V/2.0V/2.2V/2.5V/2.8V 5% for battery input (BAT_IN) selected by application program
* Wide range of available package types * EEPROM Memory with 1288 capacity * RF Transceiver with 2.4GHz RF frequency
General Description
The device is an 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O, mouse/keyboard appliances and SPI control product applications. The advantages of low power consumption, I/O flexibility, Timer functions, Watchdog timer, Power Down, wake-up functions together with the optional peripherals such as EEPROM Memory and RF transceiver provide the devices with versatility for industrial control, consumer products, subsystem controllers, RF module control, etc.
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Selection Table
Part No. HT82M75REW HT82K75REW Program Memory 4K15 4K15 Data Memory 1288 1608 Data EEPROM 1288 1288 I/O 15 31 Timer 16-bit1 16-bit1 DC/DC SPI Converter Interface O O O O RF Transceiver O O Built-in OSC O O Stack 6 6 Package 40QFN (660.85mm) 64LQFP
Note:
1. There are additional peripherals named RF Transceiver with RF frequency of 2.4GHz and Data EEPROM with capacity of 128 bytes in HT82M75REW and HT82K75REW devices. All information related to the RF Transceiver and EEPROM Data Memory will be described in the corresponding section respectively. 2. As devices exist in more than one package format, the table reflects the situation for the package with the most pins.
Block Diagram
W a tc h d o g T im e r O s c illa to r W a tc h d o g T im e r V o lta g e D e te c to r D C /D C
S ta c k
OTP P ro g ra m M e m o ry
RAM D a ta M e m o ry
R eset C ir c u it 8 - b it R IS C C o re
EEPROM D a ta M e m o ry
I/O P o rts
1 6 - b it T im e r
SPI In te rfa c e
RF T r a n s m itte r
RC
In te rn a l O s c illa to r
In te rru p t C o n tr o lle r
Pin Assignment
PB4 PB5 PB6 PB7 LX VSSLX B A T _ IN VDD VSS RES PA0 PA1 PA2 PA3 PA4 PA5 V D D _ 3 V /V D D _ G R /V D V XT XT VDD VD VDD LO VDD D_B DD_ AL_ AL_ _PL D_C _VC OP_ _RF RF_ G O C N P P P
403938 37 363534 33 32 31 1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 1718 19 20
RF_N VD D_RF2 NC VDD VSS VDD B A T _ IN VSSLX LX RES
30 29 28 27
H T82M 75R EW 4 0 Q F N -A
26 25 24 23 22 21
VDD VDD G P IO G P IO G P IO PB1 PB2 PB3 PB4 PB5
_2V2 _D 0 1 2
GN G G VD VDD
G
PA6 PA7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 P IO 2 D_D P IO 1 P IO 0 D_D _2V2 1 2 3 4 5 6 7 8 9
64636261605958575655545352515049
H T82K 75R EW 6 4 L Q F P -A 10 11 12 13 14 15 16 1718192021 2223242526272829303132
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PB3 PB2 PB1 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VSS VDD VD D_RF2 NC RF_N
A
1 PB6 PB7 PA0 PA1 P A 2 /T M R PA3 RA4 PA5 PA6 PA7
L
RF_ NC VDD DB5 LO O DB5 VDD VDD VDD GDN XTA XTA DB4 VDD VDD VDD P _VCO _CP _PLL _PLL L_P L_N P_C _RFI _A _ G R /V D D _ B G _3V
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Pin Description
The following table only includes the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the corresponding section of the datasheet along with the relevant peripheral function functional description. Pin Name PA0~PA1 PA2/TMR PA3~PA7 I/O Options Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. PA2 is shared with the external timer input pin TMR. Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Also a configuration option determines if the PB0 is a CMOS output type or NMOS output type. PB0 is shared with SCS of the SPI interface.
I/O
Pull-high Wake-up
PB0/SCS PB1~PB7
I/O
Pull-high or Wake-up CMOS/NMO S
PC0~PC1 PC2/INT PC3~PC4 PC5/SDI PC6/SDO PC7/SCK
I/O
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input (both falling and rising edge) by a configuration option. SoftPull-high or ware instructions determine if the pin is a CMOS output or Schmitt Trigger Wake-up input. Configuration options determine if the pins have pull-high resistors. CMOS/NMO Also a configuration option determines if the PC pins are CMOS output type S or NMOS output type. The INT is shared with PC2, PC5~PC7 are shared with the SPI interface. Bidirectional 8-bit input/output port. Each nibble can be configured as Pull-high or wake-up inputs (both falling and rising edge) by a configuration option. SoftWake-up ware instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Bidirectional 8-bit input/output port. Each nibble can be configured as Pull-high or wake-up inputs (both falling and rising edge) by a configuration option. SoftWake-up ware instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. 3/4 3/4 3/4 3/4 3/4 3/4 Negative power supply, ground Schmitt Trigger reset input. Active low Positive power supply Battery input DC/DC LX switch DC/DC ground
PD0~PD7 (HT82K75R only)
I/O
PE0~PE7 (HT82K75R only) VSS RES VDD BAT_IN LX VSSLX
I/O
3/4 I 3/4 I I I
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Pin Description for EEPROM Memory
Pin Name VDDP VSSP SDA SCL NC Note: Type 3/4 3/4 I/O I 3/4 Description External Positive power supply for EEPROM Memory External Negative power supply for EEPROM Memory, ground Internal Serial data input/output signal Internal connected with MCU I/O line. Serial clock input signal Internal connected with MCU I/O line. Implies that the pin is Not Connected and can therefore not be used.
The pin descriptions for all external pins with the exception of the EEPROM VDDP and VSSP pins are described in the preceding MCU section. VDDP and VSSP should be externally connected to the MCU power supply named VDD and VSS respectively. The SDA and SCL lines here are internal connected to the MCU I/O pins PC0 and PC1 respectively for these devices.
Pin Description for RF Transceiver
Pin Name RF_P RF_N VDD_RF1 VDD_RF2 GPIO0 GPIO1 GPIO2 VDD_D GND_D VDD_2V2 VDD_3V GND_GR VDD_A XTAL_P XTAL_N VDD_PLL VDD_CP VDD_VCO LOOP_C VDD_GR VDD_BG DB4 DB5 Type I/O I/O I I I/O I/O I I O I 3/4 I I I I I I I/O I O I I Description External Differential RF input/output (+) External Differential RF input/output (-) External RF transceiver power supply (1) External RF transceiver power supply (1) External General Purpose digital I/O It is also used as an external TX/RX switch control External General Purpose digital I/O It is also used as an external Power Amplifier (P.A.) enable control. External RF transceiver digital circuit power supply (+) External RF transceiver digital circuit power supply (-) External RF transceiver DC-DC output voltage It cannot be used. External RF transceiver 3V input for a DC-DC regulator External RF transceiver Guard-Ring ground External RF transceiver power supply for analog circuits (1) External RF transceiver 32MHz Crystal input (+) External RF transceiver 32MHz Crystal input (-) External RF transceiver PLL power supply (1) External RF transceiver Charge pump power supply (1) External RF transceiver Voltage-controlled oscillator power supply (1) External RF transceiver PLL loop filter external capacitor It is connected to the external 47pF capacitor. External RF transceiver Guard-Ring power supply (1) External RF transceiver Bandgap power supply (1) External Test pin It is connected to ground. External Test pin It is connected to ground.
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Pin Name SI SO SCLK SEN INT RST NC Type I O I I I I 3/4 Description Internal RF Transceiver Slave SPI Serial Data Input Signal Internally connected to the MCU Master SPI SDO output signal Internal RF Transceiver Slave SPI Serial Data Output Signal Internally connected to the MCU Master SPI SDI input signal Internal RF Transceiver Slave SPI Serial Clock Input Signal Internally connected to the MCU Master SPI SCK output signal Internal RF Transceiver Slave SPI Serial interface Enable Input Signal Internally connected to the MCU Master SPI SCS output signal Internal RF Transceiver Interrupt Output Signal Internally connected to the MCU INT input signal Internal RF Transceiver global hardware reset input signal, active low. Internally connected to the MCU I/O pin configured as output type. Implies that the pin is Not Connected and can therefore not be used.
Notes: (1) Connecting bypass capacitor(s) as close to the pin as possible. (2) The pin descriptions for all external pins except the RF Transceiver pins listed in the above table are described in the preceding MCU section. (3) The INT and RST lines are internally connected to the MCU I/O pins PC2 and PC3 respectively for the HT82M75REW and HT82K75REW devices.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VBAT IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 RPH1 Parameter BAT_IN Operating Voltage Operating Current (Crystal OSC) Standby Current Input Low Voltage for I/O (Schmitt Trigger) Input High Voltage for I/O (Schmitt Trigger) Input Low Voltage (RES) Input High Voltage (RES) Other I/O Pins Sink Current Other I/O Pins Source Current Other Pins Internal Pull-high Resistance Test Conditions VDD 3/4 3V 3/4 3/4 3/4 3/4 3/4 3V 3V 3V VOL=0.1VDD VOH=0.9VDD 3/4 Conditions 3/4 No load, fSYS= 6MHz No load, system HALT WDT disable, LVR disable 3/4 3/4 3/4 3/4 Min. 1.8 3/4 3/4 0 0.7VDD 0 0.9VDD 4 -2.5 10 Typ. 2.2 3 3/4 3/4 3/4 3/4 3/4 3/4 -4.5 30 Max. 3.3 6 20 0.3VDD VDD 0.3VDD VDD 3/4 3/4 50
Ta=25C Unit V mA mA V V V V mA mA kW
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D.C. Characteristics for EEPROM Memory
Symbol ICC1* ICC2* ISTB* Note: Parameter Operating Current Operating Current Standby Current Test Conditions VCC 3V 3V 3V Conditions Read at 100kHz Write at 100kHz VIN=0 or VCC Min. 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 Ta=-40C~85C Max. 1 3 3 Unit mA mA mA
* The operating current ICC1 and ICC2 listed here are the additional currents consumed when the EEPROM Memory operates in Read Operation and Write Operation respectively. If the EEPROM is operating, the ICC1 or ICC2 should be added to calculate the relevant operating current of the device for different conditions. To calculate the standby current for the whole device, the standby current shown above should also be taken into account. Ta=-40C~85C Remark 3/4 3/4 3/4 Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 Standard Mode* Min. 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 4700 3/4 3/4 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 3/4 100 5 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ms
A.C. Characteristics
Symbol fSK tHIGH tLOW tr tf tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tAA tBUF tSP tWR Note: Parameter SCL Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time
These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 3.6V For relative timing, refer to timing diagrams
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A.C. Characteristics for EEPROM Memory
Test Conditions Symbol fSYS tRCSYS tWDT1 tRES tSST tLVR tWake-up tconfigure Parameter VDD System Clock Watchdog OSC Period Watchdog Time-out Period with 6-stage Prescaler External Reset Low Pulse Width System Start-up Timer Low Voltage Width to Reset MCU Wake-up Timer Watchdog Time-out Period 3V 3V 3V 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 WDTS=1 3/4 3/4 3/4 3/4 3/4 5.7 3/4 3/4 1 3/4 0.25 3/4 3/4 6 71 4.57 3/4 512 1 3/4 1024 6.3 3/4 3/4 3/4 3/4 2 1 3/4 MHz ms ms ms 1/fSYS ms ms tRCSYS Min. Typ. Max. Unit Ta=25C
Power-On Reset Characteristics
Test Conditions Symbol Parameter VDD Conditions 3/4 Without 0.1mF between VDD and VSS Without 0.1mF between VDD and VSS ,Ta=25C Without 0.1mF between VDD and VSS With 0.1mF between VDD and VSS 3/4 0.05 0.9 2 10 1.0 3/4 3/4 3/4 3/4 3/4 3/4 1.5 3/4 3/4 1.8V~ 3.3V 3/4 3/4 Min. Typ. Max.
Ta=25C Unit mA V/ms V ms ms
IPOR
RRVDD VPOR
Operating current VDD Rise Rate to Ensure Power-on Reset Maximum VDD Start Voltage to Ensure Power-on Reset
tPOR
Power-on Reset Low Pulse Width
3/4
V
DD
tP
OR
RR
VDD
V
POR
T im e
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RF Transceiver D.C. Characteristics
Symbol ITX Test Conditions RF Transceiver TX Active. At 0 dBm output power RF Transceiver RX Active in Normal Mode (250 Kbps) IRX RF Transceiver RX Active in Turbo Mode (1M bps) ISTB DC-DC Off* DC-DC Off* DC-DC Off* Min. 3/4 3/4 3/4 3/4 3/4 Typ. 21 19 21 60 VDD=3V, Ta=25C Max. 30 28 30 80 Unit mA mA mA mA mA
RF Transceiver in STANDBY mode. Partial 32MHz clock and Sleep clock remains active. RF/MAC/BB, system clock shutdown. RF Transceiver in DEEP_SLEEP mode. Power to digital circuit remains active to retain Registers and FIFOs. All the other power is shutdown. RF Transceiver in POWER_DOWN mode. Minimum wake-up circuit remains active. All power is shutdown. Register and FIFO data are not retained.
IDS
3.2
10.0
IPD
3/4
0.6
2.0
mA
Note:
* The operating current ITX or IRX listed here is the additional current consumed when the RF Transceiver operates in Active TX mode or Active RX mode. If the RF Transceiver is active, either ITX or IRX should be added to calculate the relevant operating current of the device for different operating mode. To calculate the standby current for the whole device, the standby current shown above including ISTB, IDS and IPD should be taken into account for different Power Saving Mode. VDD=3V, Ta=25C, LO frequency=2.445GHz, DC-DC Off
RF Transceiver A.C. Characteristics
Receiver Parameters RF Input Frequency RF Sensitivity Maximum RF Input Adjacent Channel Rejection Alternative Channel Rejection 3/4
Test Conditions
Min. 2.400 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Typ. 3/4 -90 -80 5 20 -62 40 -42 -60
Max. 2.495 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Unit GHz dBm dBm dBm dBc dBm dBc dBm dBm
At antenna input with O-QPSK 250Kbps signal, PER 0.1% 1 Mbps 3/4 @ 5MHz, 250Kbps (-82dBm + 20 dB = -62dBm) @ 10 MHz, 250Kbps (-82dBm + 40 dB = -42dBm) Measured at the balun matching the network with the input frequency at 2.4~2.5GHz 3/4
LO Leakage Noise figure (Including matching)
8
dB
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Transmitter Parameters RF carrier frequency Maximum RF output power RF output power Accuracy RF output power control range TX gain control resolution Carrier suppression TX spectrum mask for O-QPSK signal TX EVM Synthesizer Parameters PLL Stable Time PLL Programming resolution 3/4 3/4 3/4 At 0 dBm output power setting 3/4 3/4 3/4 3/4 Offset frequency > 3.5 MHz At 0 dBm output power 3/4 VDD=3V, Ta=25C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off Test Conditions Min. 2.400 -3 3/4 3/4 0.1 3/4 3/4 3/4 3/4 Typ. 3/4 0 3/4 36 3/4 -30 3/4 3/4 30 Max. 2.495 3/4 4 3/4 0.5 3/4 -30 -20 3/4 Unit GHz dBm dBm dB dB dBc dBm dBc %
VDD=3V, Ta=25C, LO frequency=2.445GHz, 250 Kbps, DC-DC Off Test Conditions Min. 3/4 3/4 Typ. 130 1 Max. 3/4 3/4 Unit ms MHz
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System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and
S y s te m C lo c k
execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.
P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
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When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 6
Program Counter Bits Mode b11 Initial Reset SPI Interrupt Timer/Event Counter Overflow External interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine PC11 PC10 PC9 #11 S11 #10 S10 #9 S9 PC8 #8 S8 0 0 0 0 b10 0 0 0 0 b9 0 0 0 0 b8 0 0 0 0 b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 1 b2 0 1 0 1 b1 0 0 0 0 b0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits @7~@0: PCL bits S11~S0: Stack register bits
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Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. Structure The Program Memory has a capacity of 4K15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices
000H 004H 008H 00CH In itia lis a tio n V e c to r SPI In te rru p t V e c to r T im e r /E v e n t C o u n te r In te rru p t V e c to r E x te rn a l In te rru p t V e c to r
This vector is used by serial interface. When 8-bits of data have been received or transmitted success-fully from serial interface. The program will jump to this location and begin execution if the interrupt is enable and the stack is not full.
* Location 008H
This vector is used by the timer/event counter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 00CH
This vector is used by the external interrupt. If the INT external input pin on the device receives a high to low transition, the program will jump to this location and begin execution, if the interrupt is enabled and the stack is not full.
* Table location
FFFH
1 5 b its
Program Memory Structure
Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Table Location Bits
Instruction b11 TABRDC[m] TABRDL[m] PC11 1 b10 PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
Table Location Note: PC11~PC8: Current program counter bits when TBHP is disabled TBHP register bit3~bit0 when TBHP is enabled @7~@0: Table Pointer TBLP bits Rev. 1.00 12 June 11, 2010
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The three methods are shown as follows: The instructions TABRDC [m] (the current page, one page=256words), where the table location is defined by TBLP (07H) in the current page. And the configuration option TBHP is disabled (default). The instructions TABRDC [m], where the table location is defined by registers TBLP (07H) and TBHP (01FH). And the configuration option TBHP is enabled. The instructions TABRDL [m], where the table location is defined by register TBLP (07H) in the last page (F00H~FFFH).
will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Otherwise, the configuration option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is F00H which refers to the start address of the last page within the 4K Program Memory of device. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H, 1FH), which indicates the table location. Before accessing the table, the location must be placed in the TBLP and TBHP (If the configuration option TBHP is disabled, the value in TBHP has no effect). The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It
P ro g ra m C o u n te r H ig h B y te TBLP
P ro g ra m M e m o ry
TBHP TBLP
P ro g ra m M e m o ry
TBLH T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Table Read - TBLP only
Table Read - TBLP/TBHP
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tempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? ; temporary register #1 ; temporary register #2
mov mov
; initialise table pointer - note that this address ; is referenced ; to the last page or present page
tabrdl
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address F06H transferred to tempreg1 and TBLH
dec tabrdl
tblp tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org dc F00h ; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
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Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8-bit wide. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H.
H T82K 75R EW 00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry DFH BFH 3FH 40H 00H
H T82M 75R EW
S p e c ia l P u r p o s e D a ta M e m o ry
G e n e ra l P u rp o s e D a ta M e m o ry
Data Memory Structure
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H T82M 75R EW 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 40H BFH S P IR SBCR SBDR G e n e ra l P u rp o s e D a ta M e m o ry (1 2 8 B y te s ) TBHP CTLR PA PAC PB PBC PC PCC S p e c ia l P u r p o s e D a ta M e m o ry ACC PCL TBLP TBLH W DTS STATUS IN T C TM RH TM RL TM RC PTR IA R 0 MP0 IA R 1 MP1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 40H DFH S P IR SBCR SBDR G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) :U nused, re a d a s "0 0 " TBHP PA PAC PB PBC PC PCC PD PDC PE PEC CTLR S p e c ia l P u r p o s e D a ta M e m o ry ACC PCL TBLP TBLH W DTS STATUS IN T C TM RH TM RL TM RC PTR H T82K 75R EW IA R 0 MP0 IA R 1 MP1
Special Purpose Data Memory Structure
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Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from all of the data banks if the Data Memory is divided into 2 or more banks. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access all data banks if the Data Memory is divided into 2 or more banks.
data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. IAR0 mp0 block loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared a,04h ; setup size of block block,a a,offset adres1; Accumulator loaded with first RAM address mp,a ; setup memory pointer with first RAM address
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Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH, TBHP These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value.
b7 TO PDF OV Z AC
Otherwise, the configuration option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out.
b0 C
S T A T U S R e g is te r
Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
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In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Interrupt Control Registers - INTC The microcontroller provides an internal timer/event counter overflow interrupt. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Timer/Event Counter Registers TMRH, TMRL, TMRC All devices possess a single internal 16-bit count-up timer. An associated register pair known as TMRL/TMRH is the location where the timer 16-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMRC, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Watchdog Timer Register - WDTS The Watchdog function in the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows.To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have correspondingly designated registers known as PA, PB, etc. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register known as PAC, PBC, etc., also mapped to specific addresses with the Data Memory.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and Wake-up option for all I/O pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The microcontroller provides 24 or 40 bit bidirectional input/output lines labeled with port names known as PA, PB, etc. These I/O ports are mapped to the Data Memory with addresses as shown in the Special Purpose Data Memory table. All of these I/O lines can be used for input and output operations and one line as an input only. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. The individual pull-high resistor is selected to be connected to each pin on Port A by a configuration option. A configuration option can determine if the pull-high resistors are connected to the lower significant four pins or higher significant four pins on each I/O port except Port A. Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the port pin changes from high to low. This function is especially suitable for applications that can be woken up via external switches. All of the I/O pins can be configured to have the capability to wake-up the device by high to low and low to high edges using different configuring ways. It means once the I/O pin is configured to have the
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V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
I/O D a ta B it Q D CK S Q
P o rt
W r ite D a ta R e g is te r P A O u tp u t C o n fig u r a tio n
M U
P u ll- L o w X W a k e - u p o p tio n fo r a n y I/O p o rt
R e a d D a ta R e g is te r W a k e -u p fo r a n y I/O p o rt P A 2 /T M R
Input/Output Ports
wake-up capability, the device can be woken up by any I/O transition. For more details, refer to the Configuration Option Section later. I/O Port Control Registers Each I/O port has its own control register known as PAC, PBC, etc., to control the input/output configuration. With this control register, each CMOS/NMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associated port control register. PC and PB can be set CMOS or NMOS output for option. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS/NMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application proRev. 1.00 20
gram control.
* External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O pin PA2. To configure this pin to operate as timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, this pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.
* External Interrupt Input
The external interrupt pin INT is pin-shared with the I/O pin PC2. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled. I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the control registers, known as PAC, PBC, etc., are programmed to setup some pins as outputs, these output pins will have June 11, 2010
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an initial high output value unless the associated data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All I/O have the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low and low to high transition of any of the selected wake-up pins. of the TE bit, each high to low, or low to high transition on the PA2/TMR pin will increment the counter by one. Timer Registers - TMRH, TMRL The TMRH and TMRL registers are two 8-bit special function register locations within the special purpose Data Memory where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA2/TMR pin. The timer will count from the initial value loaded by the preload register to the full count value of FFFFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 0000H to FFFFH the preload registers must first be cleared to 0000H. It should be noted that after power-on the preload registers will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload registers during this period will remain in the preload registers and will only be written into the actual counter the next time an overflow occurs. Accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMRL, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMRH, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer from its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register directly will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Register - TMRC The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMRC. Together with the TMRL and TMRH registers, these three
Timer/Event Counters
The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The device contains an internal 16-bit count-up timer which has three operating modes. The timer can be configured to operate as a general timer, external event counter or as a pulse width measurement device.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing There are three registers related to the Timer/Event Counter, TMRL, TMRH and TMRC. The TMRL/TMRH register pair are the registers that contains the actual timing value. Writing to this register pair places an initial starting value in the Timer/Event Counter preload register while reading retrieves the contents of the Timer/Event Counter. The TMRC register is a Timer/Event Counter control register, which defines the timer options, and determines how the timer is to be used. The timer clock source can be configured to come from the internal system clock divided by 4 or from an external clock on shared pin PA2/TMR. Configuring the Timer/Event Counter Input Clock Source The timer clock source can originate from either the system clock divided by 4 or from an external clock source. The system clock divided by 4 is used when the timer is in the timer mode or in the pulse width measurement mode. An external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin PA2/TMR. Depending upon the condition
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registers control the full operation of the Timer/Event Counter. Before the timer can be used, it is essential that the TMRC register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the required logic levels. The timer-on bit TON or bit 4 of the TMRC register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register. Configuring the Timer Mode In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The timer-on bit, TON, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero.
D a ta B u s L o w B y te B u ffe r 1 6 - B it P r e lo a d R e g is te r R e lo a d
TM 1 TM R TE fS
YS
TM 0
/4
T im e r /E v e n t C o u n te r M o d e C o n tro l TON
H ig h B y te
L o w B y te
O v e r flo w to In te r r u p t
1 6 - B it T im e r /E v e n t C o u n te r
16-bit Timer/Event Counter Structure
b7 TM 1
b0 TM 0 TON TE T im e r /E v e n t C o u n te r C o n tr o l R e g is te r N o t im p le m e n te d , r e a d a s " 0 " T o d e fin e th e a c tiv e e d g e o f T M R 1 : a c tiv e o n h ig h to lo w 0 : a c tiv e o n lo w to h ig h T o e n a b le o r d is a b le tim e r c o u n tin g 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g m o d e TM 0 TM 1 no 0 0 ev 1 0 tim 0 1 1 1 pu s e le c t m od entc erm ls e w e ava o u n te ode ( id th m ila b rm in te ea le o d e ( e x te r n a l c lo c k ) r n a l c lo c k ) s u re m e n t m o d e p in in p u t s ig n a l
Timer/Event Counter Control Register
fS
YS
/4
In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
Timer Mode Timing Chart
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HT82M75REW/HT82K75REW
Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on external pin PA2/TMR, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA2/TMR pin receives a low to high transition. If the TE bit is high, the counter will increment each time PA2/TMR receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To ensure that the external pin PA2/TMR is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. In the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA2/TMR can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA2/TMR pin, the timer will start counting until the PA2/TMR pin returns to its original high level. At this point the TON bit will be automatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA2/TMR pin and stop counting when the PA2/TMR pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA2/TMR. As the TON bit has now been reset any further transitions on the PA2/TMR pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA2/TMR pin and not by the logic level. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. If the timer interrupt is enabled, an interrupt signal will also be generated. To ensure that the external pin PA2/TMR is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input.
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
E x te r n a l T im e r P in In p u t TON ( w ith T E = 0 ) fS
YS
In c re m e n t T im e r C o u n te r fS
T im e r
YS
+1
+2
+3
+4
is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart Rev. 1.00 23 June 11, 2010
HT82M75REW/HT82K75REW
I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA2 pin for correct operation. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register PAC bit 2 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not sync h ro n is ed w i t h t h e i n t e r nal t i m e r c l o ck, t h e microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. But the timer for internal clock overflow cant wake up the MCU if MCU is in a Power down condition.
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Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer low register mov tmrl,a; ; load low register first mov a, 0aah ; setup timer high register mov tmrh,a mov a,080h ; setup Timer control register mov tmrc,a ; timer mode is used ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
Interrupts are an important part of any microcontroller system. When an internal function such as a Timer/Event Counter overflow, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several interrupts generated by internal interrupts events and external interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by a single interrupt control register, which is located in the Data Memory. By controlling the appropriate enable bits in this register the interrupt can be enabled or disabled. Also when an interrupt occurs, the request flag will be set by the microcontroller. The global enable bit if cleared to zero will disable all interrupts. Interrupt Operation A Timer/Event Counter overflow, will generate an interrupt request by setting its corresponding request flag, if its interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a Rev. 1.00 25 new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Once an interrupt subroutine is serviced, other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. June 11, 2010
HT82M75REW/HT82K75REW
Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and its corresponding timer interrupt enable bit, ETI, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H, will take place. When the interrupt is serviced, the timer interrupt request flag, TF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bit, the requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
b7 E IF TF S IF EEI ETI E S II
b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le C o n tr o l S e r ia l in te r fa c e in te r r u p t 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le C o n tro l T h e e x te rn a l In te rru p t 1 : e n a b le 0 : d is a b le S e r ia l In te r fa c e In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e E x te r n a l In te r r u p t R e q u it F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e S e r ia l In te r fa c e In te r r u p t R e q u e s t F la g S IF T im e r /E v e n t C o u n te r O v e r flo w In te r r u p t R e q u e s t F la g T F E x te rn a l In te rru p t R e q u e s t F la g E IF E S II
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity H ig h In te rru p t P o llin g
ET0I
EEI
Low
Interrupt Structure
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
10kW
inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES VDD
0 .1 m F VSS
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
RES Reset Timing Chart 27 June 11, 2010
Rev. 1.00
HT82M75REW/HT82K75REW
* Low Voltage Reset - LVR
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 u 1 0 1 u u 1 RESET Conditions RES reset during power-on RES wake-up HALT RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
1
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT
tR
STD
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t S S T T im e - o u t In te rn a l R e s e t
Timer/Event Counter
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
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HT82M75REW/HT82K75REW
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register PCL ACC TBLP TBLH STATUS INTC TMRL TMRH TMRC PA PAC PB PBC PC PCC PD ** PDC ** PE ** PEC ** WDTS MP0 MP1 CTLR PTR TBHP SPIR SBCR SBDR Note: Reset (Power-on) 000H xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 xxxx xxxx xxxx xxxx 0100 0x00 0000 0000 ----- 0000 0000 0000 0110 0000 xxxx xxxx ** For the HT82K75REW only - not implemented u means unchanged x means unknown WDT time-out RES Reset (Normal Operation) (Normal Operation) 000H uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 uuuu uuuu uuuu uuuu 0100 0x00 0000 0000 ----- 0000 0000 0000 0110 0000 xxxx xxxx 000H uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 uuuu uuuu uuuu uuuu 0100 0x00 0000 0000 ----- 0000 0000 0000 0110 0000 xxxx xxxx RES Reset (HALT) 000H uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 uuuu uuuu uuuu uuuu 0100 0x00 0000 0000 ----- 0000 0000 0000 0110 0000 xxxx xxxx WDT Time-out (HALT)* 000H uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uxuu uuuu uuuu 0000 uuuu 0000 uuuu uuuu uuuu uuuu uuuu
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Oscillator
The clock source for these devices is provided by an integrated oscillator requiring no external components. This oscillator has one fixed frequencies of 6MHz. Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 71ms at 3V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. signer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. If the configuration option has enabled the Watchdog Timer internal oscillator, then the Watchdog Timer will continue to run when in the Power Down Mode and will thus consume some power. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling or rising edge on any of the I/O pins * A system interrupt * A WDT overflow (if the contents of the PTR are zeros) * A PTR overflow occurs (if the contents of the PTR are
Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
not equal to zeros) If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Note that the WDT time-out will not occur if the contents of the Period Timer Register (PTR) are not equal to zeros. Each pin on Port A or any nibble on other ports can be setup via configuration options to permit a negative or positive transition on the pin to wake-up the system. When a port pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt will not be immediately serviced, but will rather be serviced later when the related interrupt is 30 June 11, 2010
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT function is enabled.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, will be set
and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de-
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finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 512 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 512 system clock period delay has ended. ternal WDT oscillator and its clock period may vary with VDD, temperature and process variation. The WDT clock is further divided by an internal 6-stage counter followed by a 7-stage prescaler to obtain longer WDT time-out period selected by the WDT prescaler rate selection bits, WS2~WS0, in the associated WDT register known as WDTS. There is only one instruction to clear the Watchdog Timer known as CLR WDT. As the instruction CLR WDT is executed, all contents of the 6-stage counter and 7-stage prescaler will be clear. It makes the WDT time-out period more accurate relatively. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. Although the WDT overflow is a source to wake up the MCU from the Power Down Mode, there are some limitations on the conditions at which the WDT overflow occurs. If the WDT function is enabled and the PTR contents are equal to zeros, the WDT overflow will occur to wake up the MCU from the Power Down Mode. If the PTR contents are not equal to zeros, the WDT overflow will not occur in Power Down Mode even if the WDT function has been enabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by its own internal dedicated internal WDT oscillator. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The WDT function is selected by a configuration option. There is also an internal register associated with the WDT named WDTS to disable the Watchdog Timer function and select various WDT time-out periods in the device. The clock source of the WDT comes from the in-
C L R W D T F la g CLR W D T O s c illa to r 6 - b it C o u n te r CLR 7 - b it P r e s c a le r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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HT82M75REW/HT82K75REW
Bit No. 0 Func. Name R/W CNT_WK R Description 0: MCU wakeup not by period counter 1: MCU wakeup by period counter overflow (Read only)
1
DC_Ctrl
This bit is used to decide whether the DC block is in operation R/W 0: enable DC_DC output (default) 1: disable DC_DC output R Flag for 2.2V battery low signal coming from DC/DC block (error 5%) 0: battery voltage > 2.2 or 2.0V 1: battery voltage 2.2 or 2.0 V
2
2.2 Low Battery
3 4
Clock_div
00: CLK/1=6MHz (default) 01: CLK/2=3MHz R/W 10: CLK/4=1.5MHz 11: CLK/4=1.5MHz LVD detect voltage select 000: 1.8V 001: 2.0V R/W 010: 2.2V (default) 011: 2.5V 100: 2.8V Control Register CTLR
5 6 7
LVD_Set
Period Timer Register - PTR This register is used to define the period of the timer which always counts in the Power Down mode. Once the timer is reached, the MCU will be woken-up by Period Timer Register overflow. Once the MCU is woken-up by the period timer, the CNT_WK bit of the wake-up Register is set to 1. Bit No. Function Name R/W Description The Period Timer is the time interval generator with one second as a unit. If the bits [7:0] are equal to 00H, the MCU will be woken up by one of the wake-up source mentioned in Wake-up Section except the PTR overflow event. If the bits [7:0] are not equal to 00H, the MCU will be woken up from the Power Down mode by the following events except WDT overflow event: * I/O Port wake-up * INT wake-up * Reset * The Period Timer is reached to the values specified by the PTR. Period Timer Register - PTR
0~7
Period Timer
R/W
b7 W S2 W S1
b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c W S0 W S1 W S2 W 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 N otused t :1 :4 :8 :1 6 :3 2 :6 4 :1 2 8 W D T R a te D T is d is a b le d
Watchdog Timer Register
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HT82M75REW/HT82K75REW
DC-to-DC Converter (DC/DC) Section This circuit is used to generate a stable 2.8V or 3.0V or 3.3V (error5%) power voltage for whole IC and output to the IRPT. The clock of DC/DC is 140kHz. Also it can detect the battery voltage. If the battery voltage drops to 2.2V or 2.0V determined by a configuration option (er ror5%), the DC/DC circuit will output a Low Voltage Detect signal LVD (2.2V/2.0V Low battery flag stored in associated flag bit of the Control Register CTLR.2) to MCU. Also there is a low voltage reset (LVR) circuit to check the DC/DC output voltage. When the DC/DC output voltage drops to 2.4V, the MCU will be reset. The LVR function is controlled by a configuration together with a software control bit named DC_ctrl in the Control Register CTLR. To enable the LVR function, the configuration option of LVR function has to be enabled and the control bit DC_ctrl must be set to 0 to enable the DC/DC circuit. If the configuration option is selected to disable the LVR function or the DC_ctrl bit is set to 1 to disable the DC/DC circuit, then the LVR function will be disabled. If the LVR function is enabled by appropriate setting of the configuration option and software control bit as mentioned above, then the LVR still works even if the MCU enters into the Power Down Mode. It is recommended that the LVR function is enabled when the MCU is in the Power Down Mode. When the DC/DC output voltage drops to 2.2V, the DC/DC can still work properly and is capable of outputting driving current with 100mA typically.
B A T _ IN DC_O ut T e s t_ D C LX D C /D C w ith V o lta g e D e te c to r 2 .4 L V R 1 .8 V /2 .0 V /2 .2 V /2 .5 V /2 .8 V L V D
As the voltage of the Battery-in pin drops to 1.8V, the DC/DC still has the capability of outputting current with 40mA at least. The DC/DC output signal 1.8V/2.0V/2.2V/2.5V/2.8V LVD is connected to the associated flag in Control Register (i.e. bit 2 in CTLR). Test_DC is the internal test pin of the DC_DC.
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HT82M75REW/HT82K75REW
SPI Serial Interface
The device includes one SPI Serial Interfaces. The SPI interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each other. The devices communicate using a master/slave technique where only the single master device can initiate a data transfer. A simple four line signal bus is used for all communication. SPI Interface Communication Four lines are used for each function. These are, SDI Serial Data Input, SDO - Serial Data Output, SCK - Serial Clock and SCS - Slave Select. Note that the condition of the Slave Select line is conditioned by the CSEN bit in the SBCR control register. If the CSEN bit is high then the SCS line is active while if the bit is low then the SCS line will be I/O mode. The accompanying timing diagram depicts the basic timing protocol of the SPI bus. SPI Registers There are three registers for control of the SPI Interface. These are the SBCR register which is the control register and the SBDR which is the data register and SPIR register which is the SPI mode control register. The SBCR register is used to setup the required setup parameters for the SPI bus and also used to store associated operating flags, while the SBDR register is used for data storage. The SPIR register is used to select SPI mode, clock polarity edge selection and SPI enable or disable selection. After Power on, the contents of the SBDR register will be in an unknown condition while the SBCR register will default to the condition below:
CKS 0 M1 1 M0 1 SBEN 0 MLS 0 CSEN WCOL 0 0 TRF 0
Note that data written to the SBDR register will only be written to the TXRX buffer, whereas data read from the SBDR register will actual be read from the register. SPI Bus Enable/Disable To enable the bus, the SBEN bit should be set high, then wait for data to be written to the SBDR (TXRX buffer) register. For the Master Mode, after data has been written to the SBDR (TXRX buffer) register then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in. To Disable the SPI bus SCK, SDI, SDO, SCS should be I/O mode.
Bit No. 0
Label SPI_CPOL
R/W R/W
Function 0: clock polarity falling (default falling) 1: clock polarity rising 0: SPI output the data in the rising edge(polarity=1) or falling edge (polarity=0); SPI read data in the in the falling edge(polarity=1) or rising edge (polarity=0); (default) 1: SPI first output the data immediately after the SPI is enable. And SPI output the data in the falling edge(polarity=1) or rising edge (polarity=0); SPI read data in the in the rising edge(polarity=1) or falling edge (polarity=0) 0: SPI_CSEN disable, SCS define as GPIO (default disable) 1: SPI_CSEN Enable , this bit is used to enable/disable software CSEN function This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode 0: I/O mode (default) 1: SPI mode Always 0 SPIR Register
1
SPI_MODE
R/W
2
SPI_CSEN
R/W
3 7~4
SPI_EN Reserved bit
R/W R/W
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HT82M75REW/HT82K75REW
D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r SBEN
SDO
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k SCK EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt
SDI
TRF AND W C O L F la g
M a s te r o r S la v e SBEN In te r n a l B u s y F la g SBEN
W r ite S B D R E n a b le /D is a b le
a n d , s ta rt EN
W r ite S B D R W r ite S B D R
SCS
M a s te r o r S la v e SBEN CSEN
SPI Block Diagram Note: WCOL: set by SPI cleared by users CSEN: enable/disable chip selection function pin master mode: 1/0 = with/without SCS output function Slave mode: 1/0 = with/without SCS input control function SBEN: enable/disable serial bus (0: initialise all status flags) when SBEN=0, all status flags should be initialised when SBEN=1, all SPI related function pins should stay at floating state TRF: 1 = data transmitted or received, 0= data is transmitting or still not received CPOL: I/O = clock polarity rising/falling edge: For SPIR Register. If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0) SCK is the serial clock timing.
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HT82M75REW/HT82K75REW
SPI Operation All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram shows the basic operation of the bus. The CSEN bit in the SBCR register controls the SCS line of the SPI interface. Setting this bit high, will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI inteface. If the CSEN bit is low, the SCS line will be in a floating condition and can therefore not be used for control of the SPI interface. The SBEN bit in the SBCR register must also be high which will place the SDI line in a floating condition and the SDO line high. If in the Master Mode the SCK line will be either high or low depending upon the clock polarity control bit in SPIR register. If in the Slave Mode the SCK line will be in a floating condition. If SBEN is low then the bus will be disabled and SCS, SDI, SDO and SCK will all be I/O mode. In the Master Mode, the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission or reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode:
* Master Mode
collision error has occurred so return to step5. If equal to zero then go to the following step. Step 7. Check the TRF bit or wait for an SPI serial bus interrupt. Step 8. Read data from the SBDR register. Step 9. Clear TRF. Step10. Goto step 5.
* Slave Mode:
Step 1. Select the clock source using the CKS bit in the SBCR control register Step 2. Setup the M0 and M1 bits in the SBCR control register to select the Master Mode and the required Baud rate. Values of 00, 01 or 10 can be selected. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device. Step 4. Setup the SBEN bit in the SBCR control register to enable the SPI interface. Step 5. For write operations: write the data to the SBDR register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. Goto to step 6.For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Step 6. Check the WCOL bit, if set high then a
Step 1. The CKS bit has a dont care value in the slave mode. Step 2. Setup the M0 and M1 bits to 11 to select the Slave Mode. The CKS bit is dont care. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Master device. Step 4. Setup the SBEN bit in the SBCR control register to enable the SPI interface. Step 5. For write operations: write data to the SBDR register, which will actually place the data into the TXRX register, then wait for the master clock and SCS signal. After this goto Step 6. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Step 6. Check the WCOL bit, if set high then a collision error has occurred so return to step5. If equal to zero then goto the following step. Step 7. Check the TRF bit or wait for an SPI serial bus interrupt. Step 8. Read data from the SBDR register. Step 9. Clear TRF Step10. step 5
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HT82M75REW/HT82K75REW
SPI Configuration Options and Status Control One option is to enable the operation of the WCOL, write collision bit, in the SBCR register. Some control in SPIR register. The SPI_CPOL select the clock polarity of the SCK line . The SPI_MODE select SPI data output mode. SPI include four pins , can share I/O mode status . The status control combine with four bits for SPIR and SBCR register. Include SPI_CSEN , SPI_EN for SPIR register and CSEN ,SBEN for SBCR register. SPIR(22H) SPI_EN 0 1 1 1 1 SPI_CSEN x x 0 1 1 SBCR(23H) SBEN x 0 1 1 1 CSEN x x x 0 1 SPI I/O mode I/O mode SPI mode SPI mode SPI mode I/O Status SCS I/O mode I/O mode I/O mode I/O mode SCS mode SCS not Floating SCS not Floating The SPI enable, SCS, SDI, SDO, SCK the internal Pull-high function is invalid. Note
Note:
X: dont care
Error Detection The WCOL bit in the SBCR register is provided to indicate errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SBDR register takes place during a data transfer operation and will prevent the write operation from continuing. The bit will be set high by the Serial Interface but has to be cleared by the user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration option. Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received.
b7 CKS M1 M0 SBEN M LS
b0 CSENW COL TRF SBCR R e g is te r T r a n s m itt/R e c e iv e fla g 0 : N o t c o m p le te 1 : T r a n s m is s io n /r e c e p tio n c o m p le te W r ite c o llis io n b it 0 : C o llis io n fr e e 1 : C o llis io n d e te c te d S e le c tio n s ig n a l e n a b le /d is a b le b it 0 : S C S flo a tin g fo r I/O m o d e 1 : E n a b le M S B /L S B fir s t b it 0 : L S B s h ift fir s t 1 : M S B s h ift fir s t S e r ia l B u s e n a b le /d is a b le b it 0 : D is a b le 1 : E n a b le M a s te r /S la M1 M0 0 0 0 1 1 0 1 1 v e /B a u d r a te b its M as M as M as S la v te r, te r, te r, em b a u d ra te : fS b a u d ra te : fS b a u d ra te : fS ode
PI P I/ P I/
4
16
C lo c k s o u r c e s e le c t b it 0 : f S P I= f S Y S / 2 1 : f S P I= f S Y S
SPI Interface Control Register
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HT82M75REW/HT82K75REW
S P I_ m o d e = 0 SCS (S P I_ C S E N = 1 ) SCK (S P I_ C P O L = 1 ) SCK (S P I_ C P O L = 0 ) SDI D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
(I/O
m ode)
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S P I_ m o d e = 1 SCS (S P I_ C S E N = 1 ) SCK (S P I_ C P O L = 1 ) SCK (S P I_ C P O L = 0 ) SDI D 7 /D 0 D 6 /D 1
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
(I/O
m ode)
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Bus Timing
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HT82M75REW/HT82K75REW
A
S P I T ra n s fe r C le a r W C O L
W r ite D a ta in to SBDR
M a s te r
M a s te r o r S la v e
S la v e Yes W CO L=1?
[M 1 , M 0 ]= 0 0 , 0 1 ,1 0 S e le c t c lo c k [C K S ]
[M 1 , M 0 ]= 1 1
No
No C o n fig u r e CSEN and M LS
T r a n s m is s io n C o m p le te d ? (T R F = 1 ? ) Yes
SBEN=1
re a d d a ta fro m SBDR
A
c le a r T R F
T ra n s fe r F in is h e d ? Yes END
No
SPI Transfer Control Flowchart
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HT82M75REW/HT82K75REW
Configuration Options
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PA0~7 Pull-high by bit: Pull-high or non-pull-high PA wake-up by bit, :Wake-up or non-wake-up PB Pull-high by nibble : Pull-high or non-pull-high PC Pull-high by nibble : Pull-high or non-pull-high SPI_WCOL enable/disable (default) Output slew enable 100ns or 200ns TBHP function (enable /disable) DC_DC output option:2.8V,3.0V,3.3V LVR enable/disable (default disable) WDT clock source : enable, disable for normal mode PB wake-up by bit, Wake-up or non-wake-up PC wake-up by bit, Wake-up or non-wake-up PC output type CMOS/NMOS PB0 output type CMOS/NMOS PD pull-high by nibble: pull-high or non-pull-high (*) PE pull-high by nibble: pull-high or non-pull-high (*) PD wake-up by nibble: wake-up or non-wake-up (*) PE wake-up by nibble: wake-up or non-wake-up (*) Options
Note: For HT82K75REW, there are additional configuration options as the asterisk marks shown.
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40
June 11, 2010
HT82M75REW/HT82K75REW EEPROM Data Memory
EEPROM Memory Features
* 1K capacity organized into 1288 * Accessible using two I2C lines * Device address: 01010000B followed with a * Device Operations: - Byte Write Operation - Current Address Read Operation - Random Address Read Operation - Sequential Address Read Operation
read/write operation selection bit
EEPROM Memory Overview
An area of EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is contained within the device. This type of memory is non-volatile with data retention even after power is removed and is useful for storing information such as product identification numbers, calibration values, user data, system setup data, etc.
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HT82M75REW/HT82K75REW
EEPROM Data Memory Functional Description
The embedded EEPROM Data Memory is an I2C type device and therefore operates using a two wire serial bus. It has a capacity is 1K organized into a structure of 128 8-bit words and contains the information or data important for user. EEPROM Data Memory Internal Connection In addition to the pins described above there are other MCU to EEPROM Data Memory interconnecting lines that are described in the above EEPROM Pin Description table. Note that the SDA and SCL lines are internal connected to the MCU I/O pins respectively and are not bonded to external pins.
VDD VDD I/O.x VDD VDDP SDA
* Serial clock - SCL
The SCL line is the EEPROM serial clock input line which is controlled by the host MCU I/O pin. The host MCU should configure this I/O pin connected to the SCL line as output pin. The SCL line is an internal line and not connected to an output pin. The SCL input clocks data into the EEPROM on its positive edge and clocks data out of the EEPROM on its negative edge.
* Clock and data transition
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition.
* Start condition
A high-to-low transition of SDA with SCL high will be interpreted as a start condition which must precede any other command - refer to the Start and Stop Definition Timing diagram.
* Stop condition
MCU
I/O.y VSS
EEPROM
SCL VSSP
A low-to-high transition of SDA with SCL high will be interpreted as a stop condition. After a read sequence the stop command will place the EEPROM in a standby power mode - refer to Start and Stop Definition Timing Diagram.
* Acknowledge
Dual VDD/Single VSS Power Supply MCU to EEPROM Internal Connection
VDD VDD I/O.x VDD VDDP SDA
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
D a ta a llo w e d to c h a n g e SDA
MCU
I/O.y VSS
EEPROM
SCL VSSP
SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te
S to p c o n d itio n
Dual VDD / Dual VSS Power Supply MCU to EEPROM Internal Connection Accessing the EEPROM Data Memory The two I2C lines are the Serial Clock line, SCL, and the Serial Data line SDA. The SDA and SCL pins are internal connected to the host MCU I/O pins. Normal I/O control software instructions are used to control the reading and writing operations on the EEPROM Data Memory.
* Serial data - SDA
Start and Stop Definition Timing Diagram Device Addressing All EEPROM devices require an 8-bit device address word following a start condition to enable the EEPROM for read or write operations. The device address word consist of a mandatory one, zero sequence for the first four most significant bits. Refer to the diagram showing the Device Address. This is common to all the EEPROM devices. The next three bits are all zero bits. The 8th bit of device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
The SDA line is the bidirectional EEPROM serial data line which is controlled by the host MCU I/O pin. The host MCU should configure this I/O pin as input or output dynamically opposite to the data direction of the EEPROM. The SDA line is an internal line and not connected to an output pin.
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HT82M75REW/HT82K75REW
If the comparison of the device address is successful then the EEPROM will output a zero as an ACK bit. If not, the EEPROM will return to a standby state.
1 0 1 0 0 0 0 R /W
* Read operations
The data EEPROM supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to 1.
* Current address read
D e v ic e A d d r e s s
Device Operations
* Byte Write
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the non-volatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write cycle is completed.
* Acknowledge polling
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the EEPROM power is maintained. The address will roll over during a read from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a No ACK - High - signal and a following stop condition.
* Random read
To maximize bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received.
S e n d W r ite C o m m a n d
A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a No ACK signal - high - followed by a stop condition.
* Sequential read
S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o tr o ll B y te w ith R /W = 0
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller responds with a No ACK signal - high - followed by a stop condition.
(A C K = 0 )? Yes N e x t O p e r a tio n
No
Acknowledge Polling Flow
D e v ic e a d d r e s s SDA S
W o rd a d d re s s
DATA P
S ta rt
R /W
ACK
ACK
ACK
S to p
Byte Write Timing
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HT82M75REW/HT82K75REW
D e v ic e a d d r e s s SDA S P ACK NoACK S ta rt DATA S to p
Current Read Timing
D e v ic e a d d r e s s SDA S
W o rd a d d re s s S ACK
D e v ic e a d d r e s s
DATA
S to p P NoACK
S ta rt
ACK S ta rt
ACK
Random Read Timing
D e v ic e a d d r e s s SDA S S ta rt ACK
DATA n
DATA n+1
DATA n+x
S to p P NoACK
ACK
Sequential Read Timing
Timing Diagrams
tf SCL tS
U
tr tL
OW D
tH
IG H
:S
TA
tH tS
P
:S
TA
tH
D
:D
AT
tS
U
:D
AT
tS
U
:S
TO
SDA SDA OUT
tA
A
tB V a lid V a lid
UF
SCL SDA 8 th b it W o rd n S to p C o n d itio n
ACK tW
R
S ta rt C o n d itio n
Note:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
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44
June 11, 2010
HT82M75REW/HT82K75REW RF Transceiver
RF Transceiver Features
RF/Analog Circuit Features
* ISM band 2.400GHz~2.495GHz operation * -90dBm/-80dBm sensitivity @ 250k/1M bps
MAC/Baseband Features
* Automatic ACK response and FCS check * 62-byte TX FIFO * Dual 64-byte RX FIFOs * Various power saving modes * Simple four-wire SPI interface
(Packet error rate under 0.1%)
* 3dBm maximum input level * -3dBm~0dBm typical output power * Differential RF input/output and integrated TX/RX
switch
* Integrated low phase noise VCO, frequency
RF Transceiver Applications
* Home/Building/Factory Automation * PC Peripheral * RF Remote Controller * Consumer Electronics * 2-way Medium-Data-Rate Applications
synthesizer and PLL loop filter
* Integrated 32MHz oscillator drive * Digital VCO and filter calibration * 18mA in RX and 15mA in TX mode * 2.4mA deep sleep mode, 0.1mA power down * 1M bps turbo mode supported * PLL lock-on time less than 130ms
RF Transceiver Overview
The device contains a 2.4 GHz RF transceiver with a Baseband/MAC block. The RF transceiver can be controlled by the MCU for low data rate applications such as consumer electronics, PC peripherals, toys, industrial automations, etc. For medium data rate applications like wireless voice and image transmission, the RF transceiver provides 1M bps turbo mode.
RF Transceiver Block Diagram
RF Transceiver SI SO SCLK SEN INT RST Interfacing Memory Power Management Lower MAC RF_P PHY RF_N
VDD GND GPIO0~GPIO2 XTAL_P XTAL_N
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RF Transceiver Power-on and Reset Characteristics The RF Transceiver has built-in power-on reset (POR) circuit which automatically resets all digital registers when the power is turned on. The 32MHz oscillator circuit starts to lock frequency of the right clock after power-on. The whole process takes 3ms for a clock circuit to become stable and completes the power-on reset. It is highly recommended that the user waits at least 3ms before starting to access the RF Transceiver. The RF Transceiver hardware reset signal (warm start) named RST is controlled by MCU I/O pin and internally pulled high with 33kW resistor connected to VCC within the RF Transceiver. The RF Transceiver will hold in reset state around 20ms after RST signal is released from the low state. RF Transceiver Crystal Parameter Specifications The RF Transceiver utilizes external 32MHz crystal to generate the oscillation for RF Transceiver input clock. The associated pins are XTAL_P and XTAL_N. The table below lists the parameters of the crystal oscillator used in the RF Transceiver. To operate the RF Transceiver properly, user has to select the crystal which meets the following requirements. Parameters Crystal Frequency Frequency Offset Load Capacitance Recovery Time -40 3/4 3/4 Min. Typ. 32 3/4 3/4 3/4 Max. 3/4 40 10 180 Unit MHz ppm pF ms consists of TX/RX control and digital signal processing module. Interconnection between the MCU and the RF Transceiver is implemented by internally connecting the MCU Master SPI interface to the RF Transceiver Slave SPI interface. All data transmissions and receptions between MCU and RF Transceiver including RF Transce i ve r co m m a n d s a r e co n d u ct e d a l o n g t h i s interconnected SPI interface. The RF Transceiver function control is executed by the MCU using its SPI Master serial interface. The RF Transceiver contains its own independent interrupt which can be used to indicate when a wake-up event occurs, an available packet reception occurs or when a packet transmission has successfully terminated or retransmission is timed out. RF Transceiver Internal Connection In addition to the RF Transceiver external pins described above there are other MCU to RF Transceiver interconnecting lines that are described in the above RF Transceiver Pin Description table. Note that these lines are internal to the device and are not bonded to external pins. The RF Transceiver is composed of several functional blocks named Interfacing block, Lower MAC block, Memory block, Power Management block and PHY block. The detailed functions of the functional blocks are described in the following sections.
V
DD
V
CC
VDD SCK SDO SC LK SI SO SEN IN T RST
VD D_RF
RF_P RF_N XTAL_P XTAL_N
32 MHz crystal oscillator recovery time highly depends on the shunt capacitance of 32 MHz crystal. The lower shunt capacitance value makes the recovery time shorter. This recovery time 180ms is measured with 32 MHz crystal by NDK NX3225SA.
MCU
SDI SCS IN T I/O
RF T r a n s c e iv e r
G P IO 0 G P IO 1 GND G P IO 2
RF Transceiver Functional Description
The RF transceiver integrates receiver, transmitter, voltage-controlled oscillator (VCO), and phase-locked loop (PLL). It uses advanced radio architecture to minimize the external component count and the power consumption. The Baseband/MAC block provides the hardware architecture for both MAC and PHY layers. It mainly
VSS
MCU to RF Transceiver Internal Connection
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RF Transceiver PHY Block
The key features and the block diagram of the PHY layer in RF Transceiver are listed as below. Operating frequency range is from 2400MHz to 2495MHz. It uses Offset QPSK (OQPSK) modulation to transmit data at 250k/1M bps. Direct Sequence Spreading Spectrum (DSSS) is used in baseband algorithm to increase the SNR. The RF Transceiver uses a fractional-N Phase-Locked Loop (PLL) as frequency synthesizer. Therefore, 1MHz channel spacing is supported and any integer carrier frequency between 2400MHz to 2495MHz can be used. The loop filters of PLL are integrated into the RF Transceiver except one external capacitor which should be connected between the PLL loop filter external pin and the ground. In order to keep the PLL stable, the board layout around the PLL loop filter external capacitor pin should be carefully designed to avoid EMI. The recommended value of this external capacitor is 47pF. Under 1M bps turbo mode, user can use the same program settings of MAC and all MAC functions are remained the same. Compare with 250k bps mode, in 1M bps mode, signal bandwidth is extended to 8MHz. The packet includes a 6 bytes PHY header and a 7~63 bytes PHY payload. The 6 bytes PHY header includes 4 bytes of preamble, 1 byte of start-of-frame delimiter (SFD) and 1 byte of payload length. Preamble and SFD are used for receiver packet detection and synchronization. The Frame Length field specifies the length of the PHY payload field. The valid length can be from 7 to 63 bytes. The frame format is shown as below:
4 b y te s P r e a m b le 1 b y te S ta rt o f F ra m e D e lim ite r PHY Header 1 b y te F ra m e L e n g th 7 ~ 6 3 b y te s P H Y P a y lo a d
PHY Layer Frame Format
M ix e r LNA
P o ly p h a s e F ilte r
L im itin g A m p lifie r ADC
ADC B aseband C ir c u it DAC
To Low M A C B lo c k
R F IO
PLL
To Lower M A C B lo c k
PA DAC
PHY Block architecture
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RF Transceiver Low MAC Block
The RF Transceiver MAC provides plenty of hardware-assisted features to relieve the host MCU power requirement. Besides providing reliable wireless packet transactions between two nodes, it also handles data and command transfer between the network and the physical layers PHY.
LowerM AC M e m o ry PHY RXMAC In te r fa c in g
from the recipient device. If the bit is 1, the recipient device shall send an acknowledgement frame back after determining that the received frame is valid. The bit 1 of FC field is 0 for data frame. The length of payload field is variable from 0 to 56 bytes. The frame check sequence (FCS) is calculated over the address field, FC field and the payload. The polynomial is degree 16:
G
16
(x ) = x
16
+x
12
+x
5
+1
* Acknowledgement Frame
TXM AC
Lower MAC Block Diagram MAC Frame Format
* Data Frame
The length of acknowledgement frame is always 5 bytes. Bit 1 of FC field is 1 for ACK frame. The payload field, containing user information of acknowledgement frame, can be configured by SREG0x03 and SREG0x04. The FCS is calculated over the FCS of the received packet, FC field and the payload field. The polynomial is degree 16:
G
16
(x ) = x
16
+x
12
+x
5
+1
The address field contains the broadcast address (0xFFFF-FFFFH) or destination address. The bit 0 of frame control (FC) field is used for Ack-Request which specifies whether an acknowledgement is required
Data Frame
Acknowledgement Frame
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TXMAC When the TXFIFO is triggered, the TXMAC gets the data from TXFIFO to generate a 16-bit FCS and sends the packet to the PHY layer of the TX immediately. If necessary, TXMAC handles the retransmission, when the acknowledgement packet is not received. The block diagram of a TXMAC is shown below. RXMAC The RX PHY of the RF Transceiver filters signals and tracks the synchronization symbols. If a packet passes the filtering, RXMAC performs frame type parsing, address recognition and FCS checking. If the destination address is broadcast address or matches its own identity, configured by SREG0x05 to SREG0x08, and the FCS check is passed, an interrupt is issued at SREG0x31 [3] to indicate a valid packet is received. Meanwhile, the frame length field of PHY header and PHY payload will be stored in RXFIFO. Unqualified packets are skipped. RXFIFO0 and RXFIFO1 are mapped into the 64-byte memory space from 0x300H to 0x33FH as Ping-Pong FIFOs. If Ping-Pong RX mode is enabled by SREG0x34 [0], RXMAC automatically switches between RXFIFO0 and RXFIFO1 to store incoming frame whenever a new packet comes. When the MCU host reads the long address memory 0x300H, the RXMAC will change the flag of SREG0x34 [1] automatically. For manually controlled RX operation, if the value of the flag SREG0x34 [1] is 0, the RXFIFO0 shall be read. Otherwise, the RXFIFO1 shall be read. In the above diagram, the current status of each frame is represented in SREG0x30. SREG0x30 [7] means RXFIFO full indicating the two RXFIFOs are occupied. If the MCU host cannot read the RXFIFO in time, the value of SREG0x30 [7] will be set to 1. Once the MCU host read the RXFIFO, the value of the SREG0x30 [7] will be set to 0 automatically. The contents of the RXFIFO can be flushed only by the following three ways: (1) the MCU host reads length field of RXFIFO and the last byte of the packet, (2) the host issues an RX flush, and (3) the software reset by SREG0x2A [0]. Note that RXFIFO is ready to receive next packet and all the data in RFIFO will be overwritten after RXFIFO flushed.
TXMAC Block Diagram
RXMAC Block Diagram
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Auto Acknowledgement The RXMAC supports automatically acknowledgement. If and only if the packet is successfully received and an Ack-Request bit, Bit 0, in the FC field of the received packet is set, RXMAC informs TXMAC to send an acknowledgement packet automatically. User should write the FC field correctly into the TX FIFO. If an acknowledgement is requested and the replied ACK frame is not received, the transmitter automatically resends the packet until the maximum retransmission times, specified in SREG0x1B [7:4], are reached. To utilize the function properly, the corresponding registers of both transmitting and receiving sides need to be set correctly.
* Auto-retransmission on TX Side
To automatically retransmit a packet when an ACK is not received, SREG0x1B [2] is required to be set to 1.
* Auto-acknowledgement on RX Side
To automatically reply an ACK packet when Ack-Request bit is set to 1, SREG0x00 [5] should be set to 0.
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RF Transceiver Memory Block
The Memory Block of the RF Transceiver is implemented by the SRAM. As the following Memory Block diagram shown, the RF Transceiver Memory is composed of registers and FIFOs, which can be accessed by the SPI interface. They are categorized into two kinds of address spaces. One is the short address space; the other is the long address space. Registers Registers provide control bits and status flags for the RF Transceiver operations, including transmission, reception, interrupt control, MAC/baseband/RF parameter settings, etc. The registers are divided into two types according to addressing mode as listed below.
* Short address register (6-bit short addressing mode
register, total 64 registers)
* Long address register (10-bit long addressing mode
register, total 128 registers) Short address registers are accessed by short addressing mode with valid addresses ranging from 0x00H to 0x3FH. Long address registers are accessed by long addressing mode with valid addresses ranging from 0x200H to 0x27FH. Short registers are accessed faster than long registers. Please refer to the following SPI Interface section for detailed addressing rules via SPI interface.
Memory Space Diagram
Memory Block Diagram
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Short Address Registers
Addr. 0x00 0x03 0x04 0x05 0x06 0x07 0x08 0x0D 0x12 0x17 0x18 0x1B 0x22 0x24 0x26 0x2A 0x2E 0x30 0x31 0x32 0x34 0x35 0x36 0x38 File Name RXMCR AUINFL AUINFH DADR_0 DADR_1 DADR_2 DADR_3 RXFLUSH ACKTO PACON TXCON TXTRIG WAKECTL TXSR GATECLK SOFTRST TXPEMISP RXSR ISRSTS INTMSK BATRXF SLPACK RFCTL BBREG0 r r r r TXRTYN3 IMMWAKE TXRETRY3 r r TXPET3 RXFFFULL r r r SLPACK r r WAKEPOL MATOP6 r r TXRTYN2 REGWAKE TXRETRY2 r r TXPET2 WRFF1 WAKEIF WAKEMSK r WAKEPAD MATOP5 r TXONTS3 TXRTYN1 r TXRETRY1 SPISYNC r TXPET1 r r r BATIND r MATOP4 PAONTS3 TXONTS2 TXRTYN0 r TXRETRY0 r r TXPET0 Bit 7 r AUINF7 AUINF15 Bit 6 r AUINF6 AUINF14 Bit 5 NOACKRSP AUINF5 AUINF13 Bit 4 r AUINF4 AUINF12 Bit 3 r AUINF3 AUINF11 Bit 2 r AUINF2 AUINF10 Bit 1 r AUINF1 AUINF9
Legend: r=reserved
Bit 0 r AUINF0 AUINF8 Value on POR 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 r MATOP3 PAONTS2 TXONTS1 r r r r r r PTX MATOP2 PAONTS1 TXONTS0 TXACKREQ r r ENTXM r r r r r r r MATOP1 PAONTS0 r r r r r RSTBB r r r r RDFF1 RXFLUSH MATOP0 r r TXTRIG r TXNS r RSTMAC r r TXNIF TXNMSK RXFIFO2 0110 0000 0011 1001 0000 0010 1000 1000 0011 0000 0100 0000 0000 0000 0000 0000 0000 0000 0111 0101 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 1000 0001
DADR[7:0] DADR[15:8] DADR[23:16] DADR[31:24]
RXFFOVFL RXCRCERR r r r RXIF RXMSK r
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 r r r r WAKECNT8 WAKECNT7 r r RFRST r r r r TURBO
Short Address Registers List
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Long Address Registers
Addr. 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x211 0x22F 0x23D 0x23E 0x250 0x251 0x252 0x253 0x254 0x259 0x273 0x274 0x275 0x276 0x277 File Name RFCTRL0 RFCTRL1 RFCTRL2 RFCTRL3 RFCTRL4 RFCTRL5 RFCTRL6 RFCTRL7 RFCTRL8 SLPCAL_0 SLPCAL_1 Bit 7 CHANNEL3 r r TXGB4 r BATTH3 TXFBW1 r r SLPCAL7 SLPCAL15 Bit 6 CHANNEL2 r RXFC0-1 TXGB3 r BATTH2 TXFBW0 r TXD2CO0 SLPCAL6 SLPCAL14 r r r r r r DCOPC4 SLCTRL5 FIFOPS 1MFRCH6 r Bit 5 Bit 4 Bit 3 r r r TXGB0 r r BATEN r r SLPCAL3 SLPCAL11 SLPCAL19 r r Bit 2 r r r r RXFCO r r r r SLPCAL2 SLPCAL10 SLPCAL18 r Bit 1 r VCORX1 r r RXD2CO1 r r r r SLPCAL1 SLPCAL9 SLPCAL17 IRQCTRL
Legend: r=reserved
Bit 0 r VCORX0 r r RXD2CO0 r r r r SLPCAL0 SLPCAL8 SLPCAL16 r Value on POR 0000 0001 0000 0001 1000 0100 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 0000 0000
CHANNEL1 CHANNEL0 r RXFC0-0 TXGB2 r BATTH1 32MXCO1 r r SLPCAL5 SLPCAL13 r r r r r TXGB1 r BATTH0 32MXCO0 RXFC2 r SLPCAL4 SLPCAL12 SLPCALEN r r
SLPCAL_2 SLPCALRDY IRQCTRL TESTMODE GPIODIR GPIO RFCTRL50 RFCTRL51 RFCTRL52 RFCTRL53 RFCTRL54 RFCTRL59 r MPSPI r r r DCOPC5 SLCTRL6 r 1MCSEN r
TESTMODE2 TESTMODE1 TESTMODE0 0010 1000 GPIO2DIR GPIO2 DCOPC2 r SLCTRL1 PACTRL2-2 1MFRCH2 r PLLOPT1 PACTRL1-2 SCLKOPT2 SCLKOPT6 GPIO1DIR GPIO1 DCOPC1 r SLCTRL0 PACTRL2-1 1MFRCH1 r PLLOPT0 PACTRL1-1 SCLKOPT1 SCLKOPT5 SLPVSEL1 GPIO0DIR GPIO0 DCOPC0 r 32MXCTRL PACTRL2-0 1MFRCH0 PLLOPT3 r PACTRL1-0 SCLKOPT0 SCLKOPT4 SLPVSEL0 0011 1111 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0001 0000 0000 1100 1010 0001 0101 0000 0001 0000 1000
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0 r r r SLCTRL4 DIGITALPS 1MFRCH5 r r r DCPOC r SLCTRL3 P32MXE 1MFRCH4 r r r DCOPC3 r SLCTRL2 PACEN2 1MFRCH3 r PLLOPT2 PACEN1 SCLKOPT3 r
RFCTRL73 VCOTXOPT1 VCOTXOPT0 RFCTRL74 RFCTRL75 RFCTRL76 RFCTRL77 PACEN0 r r r
PACTRL0-2 PACTRL0-1 PACTRL0-0 r r r r r SLPSEL1 r r SLPSEL0
SLPVCTRL1 SLPVCTRL0
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FIFOs serve as the temporary data buffers for data transmission and reception. Each FIFO holds only one packet at a time. TXFIFO, the transmission FIFO, is composed of 62-byte FIFO. RX FIFO, the receiving FIFO, is composed of two 64-byte FIFOs.
* TX FIFO - (62 bytes)
The TXMAC gets the to-be transmitted data from the 62-byte TXFIFO. The memory space of TXFIFO is from 0x001 to 0x03E and contains a FL field, address field, FC field and payload field. The FL field indicates the length of the address field, FC field and the payload field. The valid value of frame length is from 5 to 61 bytes.
* RX FIFO - RXFIFO0 (64 bytes) and
The RF Transceiver has four power saving modes that will be further described in Power Saving Modes Section. For ultra low-power operation, Power-down mode is available which consumes around 0.1mA while the RF Transceiver is powered down. All data stored in registers and FIFOs will be lost under Power-down mode. In this mode, The RF Transceiver is able to wake up by a wake-up input signal. Except Power down mode, the data in the registers/FIFOs are retained during the other power saving modes. Power Supply Scheme The table below lists the recommended values of the external bypass capacitors for each power pin of the RF Transceiver. For the power pins VDD_RF1 and VDD_3V, an extra bypass capacitor is needed for the decoupling purpose while the rest of the power pins require only one bypass capacitor. The path length between the bypass capacitors to each pin should be made as short as possible. Pin Name VDD_RF1 VDD_RF2 VDD_D VDD_3V Bypass Capacitor 1 47pF 47pF 10nF 10mF 47pF 47pF 10nF 10nF Bypass Capacitor 2 10nF
RXFIFO1 (64 bytes) A RXFIFO is composed of two 64-byte FIFOs (RXFIFO0 and RXFIFO1) to store the incoming packet. Each of them is designed to store one packet at a time. RXFIFO contains a FL field, address field, FC field, payload field and FCS field. The memory space of RXFIFO is from 0x300 to 0x33F. The FL field, which is extracted from the PHY header, indicates the length of the address field, FC field, the payload field and FCS field. The valid value of frame length is from 7 to 63 bytes. The value of the FL field of PHY header is calculated by adding 2, the length of FCS field of MAC frame, and the above mentioned value up.
RF Transceiver Power Management Block
Almost all wireless sensor network applications require low-power consumption to lengthen battery life. Typical battery-powered device is required to be operated over years without replacing its battery. The RF Transceiver achieves low active current consumption of both the digital and the RF/analog circuits by controlling the supply voltage and using low-power architecture.
VDD_A VDD_PLL VDD_CP
Recommended External Bypass Capacitors
TXFIFO Format
RXFIFO Format
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DC-DC Converter There are two ways to supply power to the RF Transceiver. One is through the on-chip DC-DC converter and the other is without the DC-DC converter. With DC-DC converter, the RF Transceiver consumes lower current. With the DC-DC converter, power pins including VDD_RF1, VDD_RF2, VDD_D, VDD_A, VDD_PLL and VDD_CP should be hardwired to the DC-DC converter output, pin VDD_2V2 of the RF Transceiver. Without DC-DC converter, all the power pins should be directly hardwired to the external supplied voltage. For this device the on-chip DC-DC converter is not used. User can set LREG0x250 [4] to 0 and LREG0x273 to 0x4E to bypass the DC-DC converter. When the DC-DC converter is bypassed, pins VDD_2V2 and VDD_3V are shorted internally. Battery Monitor The RF Transceiver provides a function to monitor the RF Transceiver supplied voltage. A 4-bit voltage threshold can be configured so that when the supplied voltage is lower than the threshold, the system will be notified. For battery monitor function, please refer to the Section named Battery Monitor Operations. Power Saving Modes The RF Transceiver power modes are classified into the following four modes:
* IDLE: RF circuit off. The regulator, oscillator, and digi* POWER_DOWN: All power is shutdown. Registers
and FIFOs data are not retained, a wake-up input signal can wake up the RF Transceiver. IDLE mode is rarely used because the device should at least always turns on its RX circuit to capture the on-air RF signals. The only difference between STANDBY mode and DEEP_SLEEP mode is the power status of the sleep clock. To wake the RF Transceiver up, the MCU host has to control the time of sleep process. The power management control is used for the low power operation of MAC and baseband modules. It manages to turn on and off the 32 MHz clock when the RF Transceiver goes into power saving mode. By turning off the 32 MHz clock, the MAC and baseband circuits become inactive regardless whether their power supplies exist or not. All the digital modules are clock-gated automatically. That means only when a module is functioning, its clock would then be turned on. This approach efficiently decreases certain amount of the current consumption. RF Transceiver Interfacing Block The interfacing block mainly includes three parts named SPI interface, GPIO and Interrupt signal. Each of them is described as followings. SPI Interface The MCU communicates with the RF Transceiver via an internal SPI interface to read/write the control registers and FIFOs. The SPI interface connected to the MCU SPI master in the RF Transceiver has the following features:
* A 4-line slave SPI interface composed of: SEN (SPI
tal circuits are on.
* STANDBY: RF/MAC/BB shutdown with sleep and
32MHz clocks remain active
* DEEP_SLEEP: All power is shutdown except the
power to the digital circuits and registers and FIFOs data are retained.
enable), SCLK (SPI Clock), SI (Serial Data Input) and SO (Serial Data Output).
* Most significant bit (MSB) of all addresses and data
transfers on the SPI interface is done first.
Block Diagram of Voltage Regulators with DC-DC Converter On/Bypass
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SPI Addressing Format MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator.
SPI Addressing Format
SPI Characteristics Parameter Symbol fSCLK tCL tCH tSP tNS tSD tHD tRISE tFALL Min. 3/4 100 100 100 100 25 25 3/4 3/4 Max. 5 3/4 3/4 3/4 3/4 3/4 3/4 25 25 Unit MHz ns ns ns ns ns ns ns ns The minimum time SCLK must be low. The minimum time SCLK must be high. The minimum time SEN must be low before the first positive edge of SCLK. The minimum time SEN must be held low after the last negative edge of SCLK. The minimum time data must be ready at SI, before the positive edge of SCLK The minimum time data must be held at SI, after the positive edge of SCLK. The maximum rise time for SCLK and SEN. The maximum fall time for SCLK and SEN. Conditions
SCLK, clock frequency SCLK low pulse duration SCLK high pulse duration SEN setup time SEN hold time SI setup SI hold time Rise time Fall time
SPI Timing Diagram The following figures show the timing diagrams for the short and long addressing mode respectively. The MCU SPI master will initiate a read or write operation by asserting the interface enable signal SEN to low, toggling SCLK and sent the address field by SI. The interface enable signal SEN should be high when a transaction is completed.
tSP tSD tHD tCH tCL tNS
SCLK SEN read short address data SI SO
0 A6 A5 A4 A3 A2 A1 0 X 0 A6 A5 A4 A3 A2 A1 0 X
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
DR7 DR6 DR5
write short address data SI SO
0 A6 A5 A4 A3 A2 A1 1
Dw7 Dw6 Dw5 Dw4 Dw3 Dw2 Dw1 Dw0
0 A6 A5 A4 A3 A2 A1 1
Dw7 Dw6 Dw5
Timing Diagram of Short Addressing Mode
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The SPI burst mode is provided for the access of long address memory space on a continuous basis. If SEN does not go high after the 8-bit write data and the SCLK continuously toggles, the followed 8-bit write data is written to the next address field. Same for the read access, the data of the next address will be read. The SPI burst mode is only available for the long-address mode.
tSP tSD tHD tCH tCL tNS
SCLK SEN read long address data SI SO write long address data SI SO
1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 1 X X X X
Dw7 Dw6 Dw5 Dw4 Dw3 Dw2 Dw1 Dw0 Dw7 Dw6 Dw5 Dw4
1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 0
X
X
X
X
X
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR7 DR6 DR5 DR4
Timing Diagram of Long Addressing Mode
GPIO The RF Transceiver has 3 digital GPIO pins. Each GPIO pins can be configured as input or output by LREG0x23D respectively. When being configured as an output pad, the driving capability is 4mA for GPIO0 and 1mA for GPIO1 and GPIO2. The status of these pins can be configured or read by LREG0x23E. To benefit wide rang applications, GPIO0, GPIO1 and GPIO2 can be configured to control the external Power Amplifier (P.A.) and RF switch according to the current RF state automatically. Please refer to the following section named External Power Amplifier Configuration for details. Interrupt Signal The RF Transceiver provides an interrupt output pin named INT and the polarity of the interrupt signal is selectable. The RF Transceiver issues interrupts to the MCU host on three possible events. If one of the three events happens, the RF Transceiver sets the corresponding status bit in SREG0x31. If the corresponding
interrupt mask in SREG0x32 is clear (i.e. equals 0), an interrupt will be issued on the interrupt output pin INT. If the corresponding interrupt mask is set to 1 (masked), no interrupt will be issued, but the status is still present. Whenever the SREG0x31 register is read, the interrupt and the status are cleared. The three interrupt events are described as below:
* Wake-up Alert Interrupt (WAKEIF): Each time a
wake-up event happens the RF Transceiver issues the interrupt event.
* Packet Received Interrupt (RXIF): This interrupt is is-
sued when an available packet is received in the RXFIFO. An available packet means that it passes a RXMAC filter, which includes frame type identifying, address filtering and FCS check.
* TX FIFO Release Interrupt (TXNIF): This interrupt can
be issued in two possible conditions. The two conditions are when a packet in TXFIFO is triggered and sent successfully, or when a packet is triggered and the retransmission is timed out.
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RF Transceiver Application Guide
Some typical applications are described in this section to help user gains more understanding of the operation of the RF Transceiver. RF Transceiver Hardware Connection A typical application connection is shown in Application Circuit section. The MCU host serves as a master role, and the RF Transceiver serves as a slave role. For more information, refer to the Application Circuit section. RF Transceiver Initialization After the RF Transceiver is powered up, some registers need to be configured before the data transmission or reception. The procedure is described as below.
* Procedure List
Parameter SREG SREG SREG SREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG LREG SREG SREG SREG SREG
Symbol 0x26 0x17 0x18 0x2E 0x200 0x201 0x202 0x204 0x206 0x207 0x208 0x23D 0x250 0x251 0x252 0x259 0x273 0x274 0x275 0x276 0x32 0x2A 0x36 0x36
Min. GATECLK PACON1 FIFOEN TXPEMISP RFCTL0 RFCTL1 RFCTL2 RFCTL4 RFCTL6 RFCTL7 RFCTL8 GPIODIR RFCTL50 RFCTL51 RFCTL52 RFCTL59 RFCTL73 RFCTL74 RFCTL75 RFCTL76 INTMSK SOFTRST RFCTL RFCTL
Max. Enable SPI sync function Increase PAON time Increase TXON time VCO calibration period RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control For Setting GPIO to Output RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control RF optimized control Enable all interrupt Baseband Reset RF Reset RF Reset
Unit 20 08 94 95 01 02 E0 06 C0 F0 8C 00 07 C0 01 00 40 C6 13 07 00 02 04 00 1M bps 1M bps
Conditions
DC-DC OFF
DC-DC OFF
Reset RF State Machine Release RF State Machine
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* Registers associated with Initialization
Addr. 0x17 0x18 0x26 0x2A 0x2E 0x32 0x36 0x200 0x201 0x202 0x204 0x206 0x207 0x208 0x23D 0x250 0x251 0x252 0x259 0x273 0x274 0x275 0x276 File Name PACON TXCON GATECLK SOFTRST TXPEMISP INTMSK RFCTL RFCTRL0 RFCTRL1 RFCTRL2 RFCTRL4 RFCTRL6 RFCTRL7 RFCTRL8 GPIODIR RFCTRL50 RFCTRL51 RFCTRL52 RFCTRL59 Bit 7 r r r r TXPET3 r r CHANNEL3 r r r TXFBW1 r r r r DCOPC5 SLCTRL6 r Bit 6 r r r r TXPET2 WAKEMSK r CHANNEL2 r RXFC0-1 r TXFBW0 r TXD2CO0 r r DCOPC4 SLCTRL5 r Bit 5 r TXONTS3 SPISYNC r TXPET1 r r Bit 4 PAONTS3 TXONTS2 r r TXPET0 r Bit 3 PAONTS2 TXONTS1 r r r RXMSK Bit 2 PAONTS1 TXONTS0 ENTXM r r r RFRST r r r RXFCO r r r GPIO2DIR DCOPC2 r SLCTRL1 r PLLOPT1 Bit 1 PAONTS0 r r RSTBB r r r r VCORX1 r RXD2CO1 r r r GPIO1DIR DCOPC1 r SLCTRL0 r PLLOPT0 Bit 0 r r r RSTMAC r TXNMSK r r VCORX0 r RXD2CO0 r r r GPIO0DIR DCOPC0 r 32MXCTRL PLLOPT3 r Value on POR 0000 0010 1000 1000 0000 0000 0000 0000 0111 0101 1111 1111 0000 0000 0000 0001 0000 0001 1000 0100 0000 0000 1111 0000 0000 0000 0000 1100 0011 1111 0000 0000 0000 0000 1111 1111 0000 0001 0000 0000 1100 1010 0001 0101 0000 0001
WAKECNT8 WAKECNT7 r r r r BATEN r r
CHANNEL1 CHANNEL0 r RXFC0-0 r 32MXCO1 r r r r r 32MXCO0 RXFC2 r
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0 r r SLCTRL4 r r DCPOC r SLCTRL3 r r DCOPC3 r SLCTRL2 r PLLOPT2 PACEN1 SCLKOPT3 r
RFCTRL73 VCOTXOPT1 VCOTXOPT0 RFCTRL74 RFCTRL75 RFCTRL76 PACEN0 r r PACTRL0-2 r r
PACTRL0-1 PACTRL0-0 r r r r
PACTRL1-2 PACTRL1-1 PACTRL1-0 SCLKOPT2 SCLKOPT6 SCLKOPT1 SCLKOPT5 SCLKOPT0 SCLKOPT4
Change RF Channel Procedure The RF Transceiver operates in 2.4GHz ISM band. The operating frequency is divided into 16 channels. The procedure to change the channels is described as below.
* Set the RF channel. Users can select one of the channels by configuring either LREG0x200 or LREG0x254. * Turn on the TX MAC gated clock by setting SREG0x26 [2] to 1. To avoid an incomplete acknowledgment frame
transmission happen during RF state machine reset period.
* Reset RF Transceiver state machine by setting SREG0x36 [2] to 1 and then set SREG0x36 [2] back to 0. * After RF Transceiver reset, delay for a while to ensure the acknowledgment frame, if any, is successfully transmitted.
250 kbps mode: delay 550ms 1M bps mode: delay 300ms
* To disable the TX MAC gated clock by setting SREG26 [2] to 0.
Registers associated with Change Channel Procedure.
Addr. 0x26 0x36 0x200 0x254 File Name GATECLK RFCTL RFCTRL0 RFCTRL54 Bit 7 r r CHANNEL3 1MCSEN Bit 6 r r CHANNEL2 1MFRCH6 Bit 5 SPISYNC r CHANNEL1 1MFRCH5 Bit 4 r WAKECNT8 CHANNEL0 1MFRCH4 Bit 3 r WAKECNT7 r 1MFRCH3 Bit 2 ENTXM RFRST r Bit 1 r r r Bit 0 r r r Value on POR 0000 0000 0000 0000 0000 0001 0000 0000
1MFRCH2 1MFRCH1 1MFRCH0
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HT82M75REW/HT82K75REW
RF Transceiver Interrupt Configuration The RF Transceiver issues a hardware interrupt at the internally connected interrupt signal line named INT to the MCU host. There are two related registers that need to be set correctly. All the interrupts are masked (disabled) by default. The interrupt mask should be removed by setting SREG0x32 in advance. The interrupt is by default sent to the MCU host as a falling edge signal after mask removed. The polarity can be configured by LREG0x211. The interrupt status can be read from SREG0x31 when it is triggered. Registers associated with Interrupt Configuration
Addr. 0x31 0x32 0x211 File Name ISRSTS INTMSK IRQCTRL Bit 7 r r r Bit 6 WAKEIF WAKEMSK r Bit 5 r r r Bit 4 r r r Bit 3 RXIF RXMSK r Bit 2 r r r Bit 1 r r IRQPOL Bit 0 TXNIF TXNMSK r Value on POR 0000 0000 1111 1111 0000 0000
RF Transceiver External Power Amplifier Configuration To enable the Power Amplifier (P.A.), users can set LREG0x22F [2:0] value to 0x001B. This register setting integrates the P.A. enable and the RF Switch Control (TX branch, RX branch) by utilizing GPIO0, GPIO1 and GPIO2. If the RF Transceiver is in TX mode, the GPIO0 (external P.A. enable) and GPIO1 (TX branch enable) will be pulled HIGH, and GPIO2 (RX branch enable) will be pulled LOW. If the RF Transceiver is in RX mode, the GPIO0 and GPIO1 will be pulled LOW, and GPIO2 will be pulled HIGH. The status of GPIO pins are automatically changed corresponding to TX/RX mode of the RF Transceiver.
* TX mode: [GPIO0, GPIO1, GPIO2] = [HIGH, HIGH, LOW] * RX mode: [GPIO0, GPIO1, GPIO2] = [LOW, HIGH, HIGH]
Registers associated with External Power Amplifier Configuration
Addr. 0x22F File Name TESTMODE Bit 7 MSPI Bit 6 r Bit 5 r Bit 4 r Bit 3 r Bit 2 TESTMODE2 Bit 1 TESTMODE1 Bit 0 TESTMODE0 Value on POR 0010 1000
RF Transceiver Turbo Mode Configuration The RF Transceiver provides 1M bps Turbo mode to transmit and receive data at a higher data rate. Turbo mode provides an added capability for applications which require more bandwidth. The application circuits need not any modification for Turbo mode. To use the RF Transceiver in 250k and 1M bps, the following registers need to be configured as below. Address Mode LREG LREG SREG SREG Addr. 0x206 0x207 0x38 0x2A Register Name RFCTL6 RFCTL7 BBREG0 SOFTRST Value (hex) Descriptions 250k RF optimized control RF optimized control Enable Normal/Turbo mode Baseband Reset 0x00 0xE0 0x80 0x02 1M 0xC0 0xF0 0x81
Registers associated with External Power Amplifier Configuration
Addr. 0x2A 0x38 0x206 0x207 File Name SOFTRST BBREG0 RFCTRL6 RFCTRL7 Bit 7 r r TXFBW1 r Bit 6 r r TXFBW0 r Bit 5 r r 32MXCO1 r Bit 4 r r 32MXCO0 RXFC2 Bit 3 r r BATEN r Bit 2 r r r r Bit 1 RSTBB r r r Bit 0 RSTMAC TURBO r r Value on POR 0000 0000 1000 0001 1111 0000 0000 0000
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HT82M75REW/HT82K75REW
Typical RF Transceiver TX Operation The TXMAC inside the RF Transceiver will automatically generate the preamble, Start-of-Frame Delimiter and the FCS when transmitting. The MCU host must write all other frame fields into TXFIFO for TX operation. To send a packet in TX FIFO, there are several steps to follow: Fill necessary data in TXFIFO. The format of TXFIFO is as follows:
TXFIFO Address 0x001 1 Byte Frame Length 4 Bytes Destination Address 1 Byte Frame Control 0x0+N N Bytes Payload
* Set Ackreq by SREG0x1B [2], if an acknowledgement / retransmission is required. The RF Transceiver automatically
retransmits the packet till the number of the Max trial times specified in SREG1B [7:4] is reached, if there is no acknowledgement received.
* By triggering SREG0x1B [0], the TXMAC will send the packet immediately. This bit will be automatically cleared. * Wait for the interrupt status shown in SREG0x31 [0]. If retransmission is not required, SREG0x31 [0] indicates the
packet is successfully transmitted.
* Check SREG0x24 [0] to see if transmission is successful. If SREG0x24 [0] is equal to 0, it means that the transmis-
sion is successful and the ACK was received. The number of times of the retransmission can be read at SREG0x24 [7:4]. If SREG0x24 [0] is equal to 1, it means that the transmission failed and ACK was not received. Registers associated with Typical TX Operation
Addr. 0x1B 0x24 0x31 File Name TXTRIG TXSR ISRSTS Bit 7 TXRTYN3 TXRETRY3 r Bit 6 TXRTYN2 TXRETRY2 WAKEIF Bit 5 TXRTYN1 TXRETRY1 r Bit 4 TXRTYN0 TXRETRY0 r Bit 3 r r RXIF Bit 2 TXACKREQ r r Bit 1 r r r Bit 0 TXTRIG TXNS TXNIF Value on POR 0011 0000 0000 0000 0000 0000
Typical RF Transceiver RX Operation When a valid packet is received, an interrupt is issued at SREG0x31 [3]. The MCU host can read the whole packet inside the RXFIFO. The RXFIFO is flushed when the frame length field and the last byte of RXFIFO are read, or when the MCU host triggers a RX flush by SREG0x0D [0]. The format of RXFIFO is as follows:
* RXFIFO Address
0x300 1 Byte Frame Length 4 Bytes Destination Address 1 Byte Frame Control N Byte Payload
0x307+N 1 Bytes Frame Control
* Registers associated with Typical RX Operation
Addr. 0x0D 0x31 File Name RXFLUSH ISRSTS Bit 7 r r Bit 6 r WAKEIF Bit 5 r r Bit 4 r r Bit 3 r RXIF Bit 2 PTX r Bit 1 r r Bit 0 RXFLUSH TXNIF Value on POR 0110 0000 0000 0000
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HT82M75REW/HT82K75REW
RF Transceiver Power Saving Operation Standby, Deep-Sleep and Power-Down Modes are designed for the RF Transceiver. It is only allowed to switch between power saving modes and active mode. The following settings are effective in active mode only. Standby Mode Shutdown RF/MAC/BB, while the voltage regulator, partial 32MHz clock and sleep clock remains active.
* Set LREG0x277 [5:4] to 00 to select for STANDBY Mode. * Set LREG0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit. * Set LREG0x253 [4] to 1 to enable partial 32MHz clock.
Deep_Sleep Mode All power is shutdown except the power to the digital circuits and sleep clock. Registers and FIFOs are retained.
* Set LREG0x277 [5:4] to 00 to select for DEEP_SLEEP Mode. * Set LREG0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit.
Power Down Mode All power is shutdown. Registers and FIFOs data are not retained. Initialization is needed after the RF Transceiver back to active mode. Only the internal connected interrupt line named WAKE can wake the RF Transceiver up.
* Set LREG0x277 [5:4] to 11 to select for POWER DOWN Mode. * Set LREG0x277 [3:2] to 10 for enable sleep voltage automatically controlled by internal circuit. * Set LREG0x253 [6:5] to 11 to connect the FIFO power and digital circuit power to ground.
If the internal connected interrupt line named WAKE is going to be used to wake the RF Transceiver up, the configuration for WAKE line should be included. Refer to the following WAKE Line Wake-up Section for details. The on-chip DC-DC converter is not used for this device and then bypasses it by setting the DCPOC bit in LREG0x250 register to 0. After the necessary settings mentioned above are configured, user can execute the following procedures to disable SPISYNC and place the RF Transceiver to the desired power saving mode.
* Set SREG0x26 [5] to 0 to disable SPISYNC. * Set SREG0x35 [7] to 1 to place the RF Transceiver to power saving mode.
Registers associated with Power Saving Operation:
Addr. 0x26 0x35 0x250 0x253 0x277 File Name GATECLK SLPACK RFCTRL50 RFCTRL53 RFCTRL77 Bit 7 r SLPACK r r r Bit 6 r Bit 5 SPISYNC Bit 4 r Bit 3 r Bit 2 ENTXM Bit 1 r Bit 0 r Value on POR 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 r FIFOPS r r DIGITALPS SLPSEL1 DCPOC P32MXE SLPSEL0 DCOPC3 PACEN2 DCOPC2 DCOPC1 DCOPC0
PACTRL2-2 PACTRL2-1 PACTRL2-0 SLPVSEL0
SLPVCTRL1 SLPVCTRL0 SLPVSEL1
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HT82M75REW/HT82K75REW
RF Transceiver Wake-up Operation After entering into Power Saving Mode, the RF Transceiver could be waked up by the internal register trigger. One and only one method should be used for wake-up operation.
* Configure clock recovery time
WAKECNT, used to calculate for recovery time of 32MHz clock of the RF Transceiver, should be set in advance. User shall follow the following two steps to configure WAKECNT.
Calculate the period of sleep clock Set LREG0x20B [4] to 1 and then keep polling LREG0x20B [7] until the value becomes 1. After the value of LREG0x20B [7] becomes 1, LREG0x20B [3:0], LREG0x20A, LREG0x209 form a 20-bit value C. Then the period of the sleep clock (Psleepclock) can be calculated by the following equation: 62.5xC Psleepclock= (ns ) 16 If the sleep clock frequency is higher than the expected value, user can configure LREG0x220 [4:0] to slow down the clock rate. The new clock period Psleepclock_new is obtained by the following equation: Psleepclock_new = Psleepclock_ori 2 LREG0x220[4:0] (ns) Configure WAKECNT to set the recovery time of 32MHz clock to 180ms Set WAKECNT, i.e. SREG0x36 [4:3] and SREG0x35 [6:0], to (1000*180) / Psleepclock. For example, the period of the sleep clock, Psleepclock, is 10000ns. Set SREG0x36 [4:3] and SREG0x35 [6:0]} to 0x12.
Register Trigger Wake-up User can wake the RF Transceiver up from STANDBY and DEEP_SLEEP modes by simply setting SREG0x22 [7:6] to 11. When the RF Transceiver is woken up by Register trigger, the following steps shall be executed to complete the operation:
* Wait the RF Transceiver issues a wake-up interrupt. The related wake-up interrupt flag is stored in SREG0x31 [6]. * Turn on SPISYNC function by setting SREG0x26 [5] to 1. * Setting the LREG0x250 [4] to 1 to turn off the on-chip DC-DC converter.
Registers associated with Power Saving Operation:
Addr.
0x0D 0x22 0x26 0x31 0x35 0x36 0x209 0x20A 0x20B 0x250
File Name
RXFLUSH WAKECTL GATECLK ISRSTS SLPACK RFCTL SLPCAL_0 SLPCAL_1 SLPCAL_2 RFCTRL50
Bit 7
r IMMWAKE r r SLPACK r SLPCAL7 SLPCAL15 SLPCALRD Y r
Bit 6
r REGWAKE r WAKEIF
Bit 5
r r SPISYNC r
Bit 4
r r r r
Bit 3
r r r RXIF
Bit 2
PTX r ENTXM r
Bit 1
r r r r
Bit 0
RXFLUSH r r TXNIF
Value on POR
0110 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0000 0000
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 r SLPCAL6 SLPCAL14 r r r SLPCAL5 SLPCAL13 r r WAKECNT8 WAKECNT7 SLPCAL4 SLPCAL12 SLPCALEN DCPOC SLPCAL3 SLPCAL11 SLPCAL19 DCOPC3 RFRST SLPCAL2 SLPCAL10 SLPCAL18 DCOPC2 r SLPCAL1 SLPCAL9 SLPCAL17 DCOPC1 r SLPCAL0 SLPCAL8 SLPCAL16 DCOPC0
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June 11, 2010
HT82M75REW/HT82K75REW
Primary RF Transceiver TX Operation Users activate the primary TX mode by setting SREG0x0D [2] to 1. After changing the SREG0x0D [2] value, users have to reset the RF and let RF state machine go to primary TX mode correctly. If primary TX mode is enabled, the RF Transceiver will enter power waving mode after ant packet transmits. If primary TX mode is not enabled, the RF Transceiver will switch to RX mode after any packet transmits. If ACK response is needed and primary TX mode is enabled, the RF Transceiver will enter the Power Saving Mode after ACK frame received. If no ACK frame received, the RF Transceiver will not enter the Power Saving Mode until the max time to wait for an acknowledgement frame by setting SREG0x12 [6:0]. Registers associated with Power Saving Operation:
Addr. 0x0D 0x12 File Name RXFLUSH ACKTO Bit 7 r r Bit 6 r MATOP6 Bit 5 r MATOP5 Bit 4 r MATOP4 Bit 3 r MATOP3 Bit 2 PTX MATOP2 Bit 1 r MATOP1 Bit 0 RXFLUSH MATOP0 Value on POR 0110 0000 0011 1001
RF Transceiver Battery Monitor Operation The RF Transceiver has Battery Monitor function and the procedure to enable the Battery Monitor function is described as below.
* Set the battery monitor threshold value at LREG0x205 [7:4]. * Enable the battery monitor by setting the LREG0x206 [3] to the value 1. * Read the battery-low indicator at SREG0x34 [5]. If this bit is set, it means that the supply voltage is lower than the bat-
tery monitor threshold specified by LREG0x205 [7:4]. Registers associated with Power Saving Operation:
Addr. 0x34 0x205 0x206 File Name BATRXF RFCTRL5 RFCTRL6 Bit 7 r BATTH3 TXFBW1 Bit 6 r BATTH2 TXFBW0 Bit 5 BATIND BATTH1 32MXCO1 Bit 4 r BATTH0 32MXCO0 Bit 3 r r BATEN Bit 2 r r r Bit 1 RDFF1 r r Bit 0 RXFIFO2 r r Value on POR 0000 0000 0000 0000 1111 0000
RF Transceiver Register Definitions
The Memory of the RF Transceiver is categorized into two kinds of addressing mode, known as Short Addressing Registers and Long Addressing Registers. Each of the Register definition is described in the following sections. Legends of RF Transceiver Register Types Register Type R/W WT RC R R/W1C Read/Write register Write 1 to trigger register, automatically cleared by hardware Read to clear register Read-only register Read/Write 1 to clear register Description
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HT82M75REW/HT82K75REW
RF Transceiver Short Addressing Registers (SREG0x00~SREG0x3F) 0x00 0x03 0x04 0x05 0x06 0x07 0x08 RXMCR AUINFL AUINFH DADR_0 DADR_1 DADR_2 DADR_3 0x12 0x17 0x18 0x1B ACKTO PACON TXCON TXTRIG 3/4 3/4 3/4 3/4 0x22 WAKECTL 0x24 TXSR 0x26 GATECLK 0x2A SOFTRST 0x2E TXPEMISP 3/4 3/4 3/4 0x30 0x31 0x32 0x34 0x35 0x36 0x38 RXSR ISRSTS INTMSK BATRXF SLPACK RFCTL BBREG0 3/4
0x0D RXFLUSH
* SREG0x00 - RXMCR: Receive MAC Control Register
Bit Name Type POR Bit 7~6 Bit 5
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 NOACKRSP R/W 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
Reserved: maintain as 0b00 NOACKRSP: Automatic Acknowledgement Response 0: (default) enables automatic acknowledgement response 1: disables automatic acknowledgement response Reserved: maintain as 0b00000
Bit 4~0
* SREG0x03 - AUINFL: Acknowledgement User Information Low Byte
Bit Name Type POR Bit 7~0
Bit 7 AUINF7 R/W 0
Bit 6 AUINF6 R/W 0
Bit 5 AUINF5 R/W 0
Bit 4 AUINF4 R/W 0
Bit 3 AUINF3 R/W 0
Bit 2 AUINF2 R/W 0
Bit 1 AUINF1 R/W 0
Bit 0 AUINF0 R/W 0
AUINF [7:0]: 16-bit User Information of Acknowledgement frame Low Byte.
* SREG0x04 - AUINFH: Acknowledgement User Information High Byte
Bit Name Type POR Bit 7~0
Bit 7 AUINF15 R/W 0
Bit 6 AUINF14 R/W 0
Bit 5 AUINF13 R/W 0
Bit 4 AUINF12 R/W 0
Bit 3 AUINF11 R/W 0
Bit 2 AUINF10 R/W 0
Bit 1 AUINF9 R/W 0
Bit 0 AUINF8 R/W 0
AUINF [15:8]: 16-bit User Information of Acknowledgement frame High Byte.
* SREG0x05 - DADR_0: Device Address 0
Bit Name Type POR Bit 7~0
Bit 7 DADR7 R/W 0
Bit 6 DADR6 R/W 0
Bit 5 DADR5 R/W 0
Bit 4 DADR4 R/W 0
Bit 3 DADR3 R/W 0
Bit 2 DADR2 R/W 0
Bit 1 DADR1 R/W 0
Bit 0 DADR0 R/W 0
DADR [7:0]: 32-bit Address of the RF Transceiver.
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HT82M75REW/HT82K75REW
* SREG0x06 - DADR_1: Device Address 1
Bit Name Type POR Bit 7~0
Bit 7 DADR15 R/W 0
Bit 6 DADR14 R/W 0
Bit 5 DADR13 R/W 0
Bit 4 DADR12 R/W 0
Bit 3 DADR11 R/W 0
Bit 2 DADR10 R/W 0
Bit 1 DADR9 R/W 0
Bit 0 DADR8 R/W 0
DADR [15:8]: 32-bit Address of the RF Transceiver
* SREG0x07 - DADR_2: Device Address 2
Bit Name Type POR Bit 7~0
Bit 7 DADR23 R/W 0
Bit 6 DADR22 R/W 0
Bit 5 DADR21 R/W 0
Bit 4 DADR20 R/W 0
Bit 3 DADR19 R/W 0
Bit 2 DADR18 R/W 0
Bit 1 DADR17 R/W 0
Bit 0 DADR16 R/W 0
DADR [23:16]: 32-bit Address of the RF Transceiver.
* SREG0x08 - DADR_3: Device Address 3
Bit Name Type POR Bit 7~0
Bit 7 DADR31 R/W 0
Bit 6 DADR30 R/W 0
Bit 5 DADR29 R/W 0
Bit 4 DADR28 R/W 0
Bit 3 DADR27 R/W 0
Bit 2 DADR26 R/W 0
Bit 1 DADR25 R/W 0
Bit 0 DADR24 R/W 0
DADR [31:24]: 32-bit Address of the RF Transceiver
* SREG0x0D - RXFLUSH: Receive FIFO Flush
Bit Name Type POR Bit 7 Bit 6-5 Bit 4-3 Bit 2
Bit 7 3/4 R 0
Bit 6 3/4 R 1
Bit 5 3/4 R 1
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 PTX R/W 0
Bit 1 3/4 R 0
Bit 0 RXFLUSH WT 0
Reserved: maintain as 0b0 Reserved: maintain as 0b11 Reserved: maintain as 0b00 PTX: Primary TX mode enable (1) 1: primary TX mode 0: primary RX mode (default) Note: RF reset, SREG0x36 [2], is needed after switching between PTX and PRX modes Reserved: maintain as 0b0 RXFLUSH: Flush the RX FIFO 1: Flush RX FIFO. RX FIFO data is not modified. If Ping-pong FIFO is enabled (SREG0x34 [0] =1), both FIFOs are flushed at the same time. Bit is automatically cleared to 0 by hardware.
Bit 1 Bit 0
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66
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HT82M75REW/HT82K75REW
* SREG0x12 - ACKTO: Acknowledgement Timeout Period
Bit Name Type POR Bit 7 Bit 6~0
Bit 7 3/4 R 0
Bit 6 MATOP6 R/W 0
Bit 5 MATOP5 R/W 1
Bit 4 MATOP4 R/W 1
Bit 3 MATOP3 R/W 1
Bit 2 MATOP2 R/W 0
Bit 1 MATOP1 R/W 0
Bit 0 MATOP0 R/W 1
Reserved: maintain as 0b0 MATOP [6:0]: Maximum Acknowledgement Timeout Period 0000000: 0 (default) 0000001: 1 0000010: 2 : 0111001: 57 : 1111111: 127
* SREG0x17 - PACON: Power Amplifier Control Register
Bit Name Type POR Bit 7~5 Bit 4~1
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 3/4 R 0
PAONTS3 PAONTS2 PAONTS1 PAONTS0 R/W 0 R/W 0 R/W 0 R/W 1
Reserved: maintain as 0b000 PAONTS [3:0]: Power Amplifier Settling Time to begin packet transmission. 0001: (default) 0100: (optimized - do not change) Reserved: maintain as 0b0
Bit 0
* SREG0x18 - TXCON: Transmitter Control Register
Bit Name Type POR Bit 7~6 Bit 5~2
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 TXONTS3 R/W 0
Bit 4 TXONTS2 R/W 0
Bit 3 TXONTS1 R/W 1
Bit 2 TXONTS0 R/W 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
Reserved: maintain as 0b00 TXONTS [3:0]: Transmitter Settling Time to begin packet transmission 0010: (default) 0101: (optimized - do not change) Reserved: maintain as 0b00
Bit 1~0
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HT82M75REW/HT82K75REW
* SREG0x1B - TXTRIG: Transmit FIFO Control Register
Bit Name Type POR Bit 7-4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 3/4 R 0
Bit 2 TXACKREQ R/W 0
Bit 1 3/4 R 0
Bit 0 TXTRIG WT 0
TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 R/W 0 R/W 0 R/W 1 R/W 1
TXRTYN [3:0]: Maximum TX Retry Times 0000: 0 : 0011: 3 (default) : 0101: 15 Reserved: maintain as 0b0 TXACKREQ: TX FIFO Acknowledge Request bit 1: acknowledgement packet requested 0: no acknowledgement packet requested (default) Transmit a packet with Acknowledgement request. If Acknowledgement is not received, the RF Transceiver retransmits up to xx times. Reserved: maintain as 0b0 TXTRIG: Transmit Trigger bit 1: Transmit Frame in TX FIFO. Bit is automatically cleared to 0 by hardware.
Bit 3 Bit 2
Bit 1 Bit 0
* SREG0x22 - WAKECTL: Wake-up Control Register
Bit Name Type POR Bit 7
Bit 7
Bit 6
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
IMMWAKE REGWAKE R/W 0 WT 1
IMMWAKE: Immediate Wake-up Mode Enable bit 1: enable immediate Wake-up Mode 0: disable immediate Wake-up Mode (default) REGWAKE: Register Triggered Wake-up bit 1: To wake the RF Transceiver up. Bit is automatically to 0 by hardware. Reserved: maintain as 0b000000
Bit 6 Bit 5~0
* SREG0x24 - TXSR: TX Status Register
Bit Name Type POR Bit 7-4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 TXNX R 0
TXRETRY3 TXRETRY2 TXRETRY1 TXRETRY0 R 0 R 0 R 0 R 0
TXRETRY [3:0]: TXFIFO Retry Times 0000: 0 (default) : 0101: 15 TXRETRY indicates the maximum number of retries of the most recent TXFIFO transmission. Reserved: maintain as 0b000 TXNX: TXFIFO Normal Release Status 1: Fail, retry count exceed 0: Succeeded (default)
Bit 3-1 Bit 0
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HT82M75REW/HT82K75REW
* SREG0x26 - GATECLK: Gated Clock control Register
Bit Name Type POR Bit 7~6 Bit 5
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 SPISYNC R/W 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 ENTRM R/W 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
Reserved: maintain as 0b00 SPISYNC: SPI Interface Synchronization 1: enable (optimized - do not change) 0: disable (default) Reserved: maintain as 0b00 ENTRM: TX MAC Clock Enable Control 1: enable 0: disable (default) Reserved: maintain as 0b00
Bit 4~3 Bit 2
Bit 1~0
* SREG0x2A - SOFTRST: Software Reset control Register
Bit Name Type POR Bit 7-2 Bit 1
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 RSTBB WT 0
Bit 0 RSTMAC WT 0
Reserved: Maintain as 0b000000 RSTBB: Baseband Reset 1: reset baseband circuitry. Initialization is not needed after RSTBB reset. Bit is automatically cleared to 0 by hardware. RSTMAC: MAC and Short/Long Addressing Registers Reset. 1: Reset MAC circuitry and Short/Long Addressing Registers. Initialization is needed after RSTMAC reset. Bit is automatically cleared to 0 by hardware.
Bit 0
* SREG0x2E - TXPEMISP: Transmit Parameters Register
Bit Name Type POR Bit 7~4
Bit 7 TXPET3 R/W 0
Bit 6 TXPET2 R/W 1
Bit 5 TXPET1 R/W 1
Bit 4 TXPET0 R/W 1
Bit 3 3/4 R 0
Bit 2 3/4 R 1
Bit 1 3/4 R 0
Bit 0 3/4 R 1
TXPET [3:0]: TXFIFO Retry Times. 0111: (default) 1001: (optimized - do not change) Reserved: maintain as 0b0101
Bit 3~0
Rev. 1.00
69
June 11, 2010
HT82M75REW/HT82K75REW
* SREG0x30 - RXSR: RX MAC Status Register
Bit Name Type POR Bit 7
Bit 7 RXFFFULL R 0
Bit 6 WRFF1 R 0
Bit 5 3/4 R 0
Bit 4 RXFFOVFL R 0
Bit 3 RXCRCERR R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
RXFFFULL: RX FIFO Full 1: RX FIFO is not available for data receiving 0: RX FIFO is available for data receiving (default) WRFF1: RX FIFO Status 1: Packet is ready in RX FIFO 1 0: Packet is ready in RX FIFO 0 (default) Reserved: maintain as 0b0 RXFFOVFL: RX FIFO Overflow 1: RX FIFO overflows 0: (default) RX FIFO not overflow RXCRCERR: RX CRC Error 1: RX CRC error 0: RX CRC is correct (default) Reserved: maintain as 0b000
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2~0
* SREG0x31 - ISRSTS: Interrupt Status Register
Bit Name Type POR Bit 7 Bit 6
Bit 7 3/4 R 0
Bit 6 WAKEIF RC 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 RXIF RC 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 TXNIF RC 0
Reserved: maintain as 0b0 WAKEIF: Wake-up Alert Interrupt 1: A wake-up interrupt occurred 0: No wake-up alert interrupt occurred (default) This bit is cleared to 0 when the register is read. Reserved: maintain as 0b00 RXIF: RX FIFO Reception Interrupt 1: A RX FIFO reception interrupt occurred 0: No RX FIFO reception interrupt occurred (default) This bit is cleared to 0 when the register is read. Reserved: maintain as 0b00 TXNIF: TX FIFO Normal Transmission Interrupt 1: TX FIFO normal transmission interrupt occurred 0: No TX FIFO normal transmission interrupt occurred (default) This bit is cleared to 0 when the register is read.
Bit 5-4 Bit 3
Bit 2-1 Bit 0
Rev. 1.00
70
June 11, 2010
HT82M75REW/HT82K75REW
* SREG0x32 - INTMSK: Interrupt Mask control Register
Bit Name Type POR Bit 7 Bit 6
Bit 7 3/4 R 1
Bit 6 WAKEMSK R/W 1
Bit 5 3/4 R 1
Bit 4 3/4 R 1
Bit 3 RXMSK R/W 1
Bit 2 3/4 R 1
Bit 1 3/4 R 1
Bit 0 TXNMSK R/W 1
Reserved: maintain as 0b1 WAKEMSK: Wake-up Alert Interrupt Mask 1: disable the wake-up interrupt (default) 0: enable the wake-up alert interrupt Reserved: maintain as 0b11 RXMSK: RX FIFO Reception Interrupt Mask 1: disable the RX FIFO reception interrupt (default) 0: enable the RX FIFO reception interrupt Reserved: maintain as 0b11 TXNMSK: TX FIFO Normal Transmission Interrupt Mask 1: disable the TX FIFO Normal Transmission interrupt (default) 0: enable the TX FIFO Normal Transmission interrupt
Bit 5~4 Bit 3
Bit 2~1 Bit 0
* SREG0x34 - BATRXF: Battery and RX FIFO control Register
Bit Name Type POR Bit 7~6 Bit 5
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 BATIND R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 RDFF1 R 0
Bit 0 RXFIFO2 R/W 0
Reserved: Maintain as 0b00 BATIND: Battery Low Indicator 1: battery voltage is lower than the threshold voltage specified by the LREG0x205 [7:4]. 0: battery voltage is higher than the threshold voltage specified by the LREG0x205 [7:4] (default) Reserved: Maintain as 0b000 RDFF1: RX FIFO Selected to Read 1: read data from RX FIFO 1 0: read data from RX FIFO 0 (default) RXFIFO2: RX Ping-Pong FIFO Enable Control 1: enable the RX Ping-Pong FIFOs 0: disable the RX Ping-Pong FIFOs (default)
Bit 4~2 Bit 1
Bit 0
* SREG0x35 - SLPACK: Sleep Acknowledgement and Wake-up Counter Register
Bit Name Type POR Bit 7 Bit 6~0
Bit 7 SLPACK WT 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
SLPACK: Sleep Acknowledgement Place the RF Transceiver to Power Saving Mode. bit is automatically cleared to 0 by hardware. WAKECNT [6:0]: System Clock Recovery Time 0000000: (default). WAKECNT is a 9-bit value. The WAKECNT [8:7] bits are located in SREG0x36 [4:3].
Rev. 1.00
71
June 11, 2010
HT82M75REW/HT82K75REW
* SREG0x36 - RFCTL: RF Mode Control Register
Bit Name Type POR Bit 7~5 Bit 4~3
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4
Bit 3
Bit 2 RFRST R/W 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
WAKECNT8 WAKECNT7
R/W 0
R/W 0
Reserved: Maintain as 0b000 WAKECNT [8:7]: System Clock Recovery Time 00: (default). WAKECNT is a 9-bit value. The WAKECNT [6:0] bits are located in SREG0x35 [6:0]. RFRST: RF State Machine Reset. 1: Hold RF state machine in Reset state 0: Normal operation of RF state machine (default) Perform RF reset by setting RFRST to 1 and then setting RFRST to 0. Delay at least 192ms after performing to allow RF circuitry to calibrate. Reserved: Maintain as 0b00
Bit 2
Bit 1~0
* SREG0x38 - BBREG0: Baseband Register
Bit Name Type POR Bit 7~1 Bit 0
Bit 7 3/4 R 1
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 TURBO R/W 1
Reserved: Maintain as 0b1000000 TURBO: Turbo Mode Select 1: 1M bps Turbo Mode (default) 0: 250k bps Normal Mode
RF Transceiver Long Addressing Registers (LREG0x200~LREG0x27F) 0x200 0x201 0x202 0x204 0x205 0x206 0x207 0x208 RFCTRL0 RFCTRL1 RFCTRL2 RFCTRL4 RFCTRL5 RFCTRL6 RFCTRL7 RFCTRL8 0x211 0x23C 0x23D 0x23E IRQCTL 3/4 GPIODIR GPIO 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0x250 RFCTRL50 0x251 RFCTRL51 0x252 RFCTRL52 0x253 RFCTRL53 0x254 RFCTRL54 0x259 RFCTRL59 3/4 3/4 3/4 3/4 3/4 3/4 0x273 RFCTRL73 0x274 RFCTRL74 0x275 RFCTRL75 0x276 RFCTRL76 0x277 RFCTRL77 3/4 3/4 3/4 3/4 3/4 3/4 3/4
0x22F TESTMODE
0x203 _RFCTRL3
0x209 SLPCAL_0 0x20A SLPCAL_1 0x20B SLPCAL_2
Rev. 1.00
72
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x200 - RFCTRL0: RF Control Register 0
Bit Name Type POR Bit 7~4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 1
CHANNEL 3 CHANNEL 2 CHANNEL 1 CHANNEL 0
R/W 0
R/W 0
R/W 0
R/W 0
CHANNEL [3:0]: Channel Number. IEEE 802.15.4 2.4GHz band channels (11~26) 0000: channel 11, 2405MHz (default) 1000: channel 19, 2445MHz 0001: channel 12, 2410MHz 1001: channel 20, 2450MHz 0010: channel 13, 2415MHz 1010: channel 21, 2455MHz 0011: channel 14, 2420MHz 1011: channel 22, 2460MHz 0100: channel 15, 2425MHz 1100: channel 23, 2465MHz 0101: channel 16, 2430MHz 1101: channel 24, 2470MHz 0110: channel 17, 2435MHz 1110: channel 25, 2475MHz 0111: channel 18, 2440MHz 1111: channel 26, 2480MHz Reserved: Maintain as 0b0001
Bit 3~0
* LREG0x201 - RFCTRL1: RF Control Register 1
Bit Name Type POR Bit 7~2 Bit 1~0
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 VCORX1 R/W 0
Bit 0 VCORX0 R/W 1
Reserved: Maintain as 0b000000 VCORX [1:0]: RX VC 01: (default) 10: (optimized - do not change)
* LREG0x202 - RFCTRL2: RF Control Register 2
Bit Name Type POR Bit 7 Bit 6~5
Bit 7 3/4 R 1
Bit 6 RXFC0-1 R/W 0
Bit 5 RXFC0-0 R/W 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
Reserved: Maintain as 0b1 RXFC0 [1:0]: RX Filter Control 0. 00: (default) 11: (optimized - do not change) Reserved: Maintain as 0b00000
Bit 4~0
Rev. 1.00
73
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x203 - RFCTRL3: RF Control Register 3
Bit Name Type POR Bit 7-3
Bit 7 TXGB4 R/W 0
Bit 6 TXGB3 R/W 0
Bit 5 TXGB2 R/W 0
Bit 4 TXGB1 R/W 0
Bit 3 TXGB0 R/W 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
TXGB [4:0]: TX Gain Control in dB. Gain step is monotonic and nonlinear with gain resolution of 0.1 ~ 0.5 dB. Gain Resolution is variable between chips. 10000: -3.1 dBm 00000: 0 dBm (default) 10001: -3.3 dBm 00001: -0.1 dBm 10010: -3.6 dBm 00010: -0.3 dBm 10011: -3.8 dBm 00011: -0.6 dBm 10100: -4.2 dBm 00100: -0.9 dBm 10101: -4.4 dBm 00101: -1.1 dBm 10110: -4.7 dBm 00110: -1.2 dBm 10111: -5.0 dBm 00111: -1.3 dBm 11000: -5.3 dBm 01000: -1.4 dBm 11001: -5.7 dBm 01001: -1.5 dBm 11010: -6.2 dBm 01010: -1.7 dBm 11011: -6.5 dBm 01011: -2.0 dBm 11100: -6.9 dBm 01100: -2.2 dBm 11101: -7.4 dBm 01101: -2.4 dBm 11110: -7.9 dBm 01110: -2.6 dBm 11111: -8.3 dBm 01111: -2.8 dBm
TX Output Power Configuration Summary table: TX Output Power Register Control LREG0x253 [3:0] LREG0x274 [7:0] LREG0x203 [7:3] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 00 C6 for DC-DC OFF 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 TX Output Power 0 dBm -0.1 dBm -0.3 dBm -0.6 dBm -0.9 dBm -1.1 dBm -1.2 dBm -1.3 dBm -1.4 dBm -1.5 dBm -1.7 dBm -2.0 dBm -2.2 dBm -2.4 dBm -2.6 dBm -2.8 dBm -3.1 dBm -3.3 dBm -3.6 dBm -3.8 dBm -4.2 dBm -4.4 dBm -4.7 dBm -5.0 dBm
Rev. 1.00
74
June 11, 2010
HT82M75REW/HT82K75REW
TX Output Power Register Control LREG0x253 [3:0] LREG0x274 [7:0] LREG0x203 [7:3] 11000 11001 11010 00 C6 for DC-DC OFF 11011 11100 11101 11110 11111 0C 0C 09 08 Bit 2~0 Reserved: Maintain as 0b000 81 09 01 01 11111 11111 11111 11111 TX Output Power -5.3 dBm -5.7 dBm -6.2 dBm -6.5 dBm -6.9 dBm -7.4 dBm -7.9 dBm -8.3 dBm -16 dBm -24 dBm -32 dBm -40 dBm
* LREG0x204 - RFCTRL4: RF Control Register 4
Bit Name Type POR Bit 7~3 Bit 2
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 RXFCO R/W 0
Bit 1 RXD2O1 R/W 0
Bit 0 RXD2O0 R\/W 0
Reserved: Maintain as 0b00000 RXFCO: RX Filter Calibration output 1: (optimized - do not change) 0: (default) RXD2O [1:0]: RX Divide-by-2 option 00: (default) 10: (optimized - do not change)
Bit 1~0
* LREG0x205 - RFCTRL5: RF Control Register 5
Bit Name Type POR Bit 7~4
Bit 7 BATTH3 R/W 0
Bit 6 BATTH2 R/W 0
Bit 5 BATTH1 R/W 0
Bit 4 BATTH0 R/W 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
BATTH [3:0]: Battery Monitor Threshold. 0000: 1.8V (default) 0001: 1.9V 0010: 2.0V 0011: 2.1V 0100: 2.2V 0101: 2.3V 0110: 2.4V 0111: 2.5V Reserved: Maintain as 0b0000
1000: 2.6V 1001: 2.7V 1010: 2.8V 1011: 2.9V 1100: 3.0V 1101: 3.3V 1110: 3.4V 1111: 3.6V
Bit 3~0
Rev. 1.00
75
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x206 - RFCTRL6: RF Control Register 6
Bit Name Type POR Bit 7~6
Bit 7 TXFBW1 R/W 1
Bit 6 TXFBW0 R/W 1
Bit 5
Bit 4
Bit 3 BATEN R/W 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
32MXCO1 32MXCO0 R/W 1 R/W 1
TXFBW [1:0]: TX Filter 00: Optimized for 250k bps Normal Mode 11: Optimized for 1M bps Turbo Mode 32MXCO [1:0]: 32MHz Crystal Oscillator 00: (Optimized - do not change) 11: (default) BATEN: Battery Monitor Enable 1: Enable 0: Disable (default) Reserved: Maintain as 0b000
Bit 5~4
Bit 3
Bit 2~0
* LREG0x207 - RFCTRL7: RF Control Register 7
Bit Name Type POR Bit 7~5 Bit 4
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 RXFC2 R/W 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
Reserved: Maintain as 0b000 RXFC2: RX Filter Control 2 1: For 1M bps Turbo Mode 0: For 250k bps Normal Mode (default) Reserved: Maintain as 0b0000
Bit 3~0
* LREG0x208 - RFCTRL8: RF Control Register 8
Bit Name Type POR Bit 7~6
Bit 7 TXD2CO1 R/W 0
Bit 6 TXD2CO0 R/W 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 1
Bit 2 3/4 R 1
Bit 1 3/4 R 0
Bit 0 3/4 R 0
TXD2CO [1:0]: TX Divide-by-2 Option 00: (default) 10: (Optimized - do not change) Reserved: Maintain as 0b001100
Bit 5~0
* LREG0x209 - SLPCAL_0: Sleep Clock Calibration 0
Bit Name Type POR Bit 7~0
Bit 7 SLPCAL7 R/W 0
Bit 6 SLPCAL6 R/W 0
Bit 5 SLPCAL5 R/W 0
Bit 4 SLPCAL4 R/W 0
Bit 3 SLPCAL3 R/W 0
Bit 2 SLPCAL2 R/W 0
Bit 1 SLPCAL1 R/W 0
Bit 0 SLPCAL0 R/W 0
SLPCAL [7:0]: Sleep Clock Calibration Counter bit 7~0 A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
Rev. 1.00
76
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x20A - SLPCAL_1: Sleep Clock Calibration 1
Bit Name Type POR Bit 7-0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 SLPCAL8 R/W 0
SLPCAL15 SLPCAL14 SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
SLPCAL [15:8]: Sleep Clock Calibration Counter bit 15~8 A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
* LREG0x20B - SLPCAL_2: Sleep Clock Calibration 2
Bit Name Type POR Bit 7
Bit 7 SLPCALRDY R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16 WT 0 R/W 0 R/W 0 R/W 0 R/W 0
SLPCALRDY: Sleep Clock Calibration Ready 1: Sleep Clock Calibration counter is ready to be read. 0: Not Ready (default) Reserved: Maintain as 0b00 SLPCALEN: Sleep Clock Calibration Enable 1: Starts the Sleep Clock Calibration counter. Bit is automatically cleared to 0 by hardware SLPCAL [19:16]: Sleep Clock Calibration Counter bit 19~16 A 20-bit calibration counter which calibrates the sleep clock. SLPCAL [19:0] indicates the time period of 16 sleep clock cycles. The unit is 62.5ns, counted by the 16MHz.
Bit 6-5 Bit 4 Bit 3-0
* LREG0x211 - IRQCTRL: Interrupt Control Register
Bit Name Type POR Bit 7~2 Bit 1
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 IRQPOL R/W 0
Bit 0 3/4 R 0
Reserved: Maintain as 0b000000 IRQPOL: Interrupt Edge Polarity 1: Rising Edge 0: Falling Edge (default) Reserved: Maintain as 0b0
Bit 0
Rev. 1.00
77
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x22F - TESTMODE: Test Mode Register
Bit Name Type POR Bit 7
Bit 7 MSPI R/W 0
Bit 6 3/4 R 0
Bit 5 3/4 R 1
Bit 4 3/4 R 0
Bit 3 3/4 R 1
Bit 2
Bit 1
Bit 0
TESTMODE2 TESTMODE1 TESTMODE0 R/W 0 R/W 0 R/W 0
MSPI: Multiple SPI Operation 1: Enable multiple SPI Operation, SO will be High-Z state when SPI inactive 0: Single SPI Operation, SO will be low when SPI inactive (default) Reserved: Maintain as 0b0101 TESTMODE [2:0]: Special Operation 000: (default) Normal Operation 001: GPIO0, GPIO1 and GPIO2 are configured to control the external P.A., LNA and RF switch 101: Single-Tone test mode Others: Undefined.
Bit 6-3 Bit 2-0
* LREG0x23D - GPIODIR: GPIO Pin Direction
Bit Name Type POR Bit 7-6 Bit 5-3
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 GPIO1DIR R/W 1
Bit 0 GPIO0DIR R/W 1
GDIRCTRL2 GDIRCTRL1 GDIRCTRL0 GPIO2DIR R/W 1 R/W 1 R/W 1 R/W 1
Reserved: Maintain as 0b00 GDIRCTRL [2:0]: GPIO Direction Control 000: (Optimized - do not change) 111: (default) GPIO2DIR: General Purpose I/O GPIO2 Direction 1: Input (default) 0: Output GPIO1DIR: General Purpose I/O GPIO1 Direction 1: Input (default) 0: Output GPIO0DIR: General Purpose I/O GPIO0 Direction 1: Input (default) 0: Output
Bit 2
Bit 1
Bit 0
* LREG0x23E - GPIO: GPIO
Bit Name Type POR Bit 7~3 Bit 2 Bit 1 Bit 0
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 GPIO2 R/W 0
Bit 1 GPIO1 R/W 0
Bit 0 GPIO0 R/W 0
Reserved: Maintain as 0b00000 GPIO2: Setting for output/Status for input of General Purpose I/O Pin GPIO2 0: (default) GPIO1: Setting for output/Status for input of General Purpose I/O Pin GPIO1 0: (default) GPIO0: Setting for output/Status for input of General Purpose I/O Pin GPIO0 0: (default)
Rev. 1.00
78
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x250 - RFCTRL50: RF Control Register 50
Bit Name Type POR Bit 7~5 Bit 4
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 DCPOC R/W 0
Bit 3 DCOPC3 R/W 0
Bit 2 DCOPC2 R/W 0
Bit 1 DCOPC1 R/W 0
Bit 0 DCOPC0 R/W 0
Reserved: Maintain as 0b000 DCPOC: DC-DC Converter Power Control 1: Enable 0: Bypass (default) DCOPC [3:0]: DC-DC Converter Optimization Control 0000: (default) 0111: (Optimized - do not change)
Bit 3~0
* LREG0x251 - RFCTRL51: RF Control Register 51
Bit Name Type POR Bit 7~6
Bit 7 DCOPC5 R/W 0
Bit 6 DCOPC4 R/W 0
Bit 5 3/4 R/W 0
Bit 4 3/4 R/W 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 3/4 R 0
DCOPC [5:4]: DC-DC Converter Optimization Control 00: (default) 11: (Optimized - do not change) Reserved: Maintain as 0b000000
Bit 5~0
* LREG0x252 - RFCTRL52: RF Control Register 52
Bit Name Type POR Bit 7~1
Bit 7 SLCTRL6 R/W 1
Bit 6 SLCTRL5 R/W 1
Bit 5 SLCTRL4 R/W 1
Bit 4 SLCTRL3 R/W 1
Bit 3 SLCTRL2 R/W 1
Bit 2 SLCTRL1 R/W 1
Bit 1
Bit 0
SLCTRL0 32MXCTRL R/W 1 R/W 1
SLCTRL [6:0]: Sleep Clock Control 0000000: (Optimized - do not change) 1111111: (default) 32MXCTRL: Start-up Circuit in 32MHz Crystal Oscillator Control 1: Enable (default) 0: Disable
Bit 0
Rev. 1.00
79
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x253 - RFCTRL53: RF Control Register 53
Bit Name Type POR Bit 7 Bit 6
Bit 7 3/4 R/W 0
Bit 6 FIFOPS R/W 0
Bit 5 DIGITALPS R/W 0
Bit 4 P32MXE R/W 0
Bit 3
Bit 2
Bit 1
Bit 0
PACEN2 PACTRL2-2 PACTRL2-1 PACTRL2-0 R 0 R 0 R 0 R 0
Reserved: Maintain as 0b0 FIFOPS: FIFO Power while the RF Transceiver is in Power Saving Mode 1: GND 0: VDD (default) DIGITALPS: Digital Power while Sleep 1: GND 0: VDD (default) P32MXE: Partial 32MHz Clock Enable 1: Enable 0: Disable (default) PACEN2: Power Amplifier Control 2 Enable 1: Enable 0: Disable (default) PACTRL2-[2:0]: Power Amplifier Control 2 000: (default) PACTRL2 [2:0] is for 1st stage Power Amplifier current fine tuning. Please follow the TX Output Power Configuration Summary Table in LREG0x203 Register definition.
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
80
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x254 - RFCTRL54: RF Control Register 54
Bit Name Type POR Bit 7
Bit 7 1MCSEN R/W 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1MCSCH6 1MCSCH5 1MCSCH4 1MCSCH3 1MCSCH2 1MCSCH1 1MCSCH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1MCSEN: 1 MHz Channel Spacing Enable 1: Enable. When LREG0x254 [7] = 1, RF channel can only be selected by LREG0x254 [6:0] and the setting of LREG0x200 [7:4] will not change the channel number at all. 0: Disable (default) 1MCSCH [6:0]: 1 MHz Channel Spacing Channel Number LREG0x254 [6:0] only works when LREG0x254 [7] = 1. 0100001: 2433 MHz 0000000: 2400 MHz 0100010: 2434 MHz 0000001: 2401 MHz 0100011: 2435 MHz 0000010: 2402 MHz 0100100: 2436 MHz 0000011: 2403 MHz 0100101: 2437 MHz 0000100: 2404 MHz 0100110: 2438 MHz 0000101: 2405 MHz 0100111: 2439 MHz 0000110: 2406 MHz 0101000: 2440 MHz 0000111: 2407 MHz 0101001: 2441 MHz 0001000: 2408 MHz 0101010: 2442 MHz 0001001: 2409 MHz 0101011: 2443 MHz 0001010: 2410 MHz 0101100: 2444 MHz 0001011: 2411 MHz 0101101: 2445 MHz 0001100: 2412 MHz 0101110: 2446 MHz 0001101: 2413 MHz 0101111: 2447 MHz 0001110: 2414 MHz 0110000: 2448 MHz 0001111: 2415 MHz 0110001: 2449 MHz 0010000: 2416 MHz 0110010: 2450 MHz 0010001: 2417 MHz 0110011: 2451 MHz 0010010: 2418 MHz 0110100: 2452 MHz 0010011: 2419 MHz 0110101: 2453 MHz 0010100: 2420 MHz 0110110: 2454 MHz 0010101: 2421 MHz 0110111: 2455 MHz 0010110: 2422 MHz 0111000: 2456 MHz 0010111: 2423 MHz 0111001: 2457 MHz 0011000: 2424 MHz 0111010: 2458 MHz 0011001: 2425 MHz 0111011: 2459 MHz 0011010: 2426 MHz 0111100: 2460 MHz 0011011: 2427 MHz 0111101: 2461 MHz 0011100: 2428 MHz 0111110: 2462 MHz 0011101: 2429 MHz 0111111: 2463 MHz 0011110: 2430 MHz 1000000: 2464 MHz 0011111: 2431 MHz 1000001: 2465 MHz 0100000: 2432 MHz
Bit 6~0
1000010: 2466 MHz 1000011: 2467 MHz 1000100: 2468 MHz 1000101: 2469 MHz 1000110: 2470 MHz 1000111: 2471 MHz 1001000: 2472 MHz 1001001: 2473 MHz 1001010: 2474 MHz 1001011: 2475 MHz 1001100: 2476 MHz 1001101: 2477 MHz 1001110: 2478 MHz 1001111: 2479 MHz 1010000: 2480 MHz 1010001: 2481 MHz 1010010: 2482 MHz 1010011: 2483 MHz 1010100: 2484 MHz 1010101: 2485 MHz 1010110: 2486 MHz 1010111: 2487 MHz 1011000: 2488 MHz 1011001: 2489 MHz 1011010: 2490 MHz 1011011: 2491 MHz 1011100: 2492 MHz 1011101: 2493 MHz 1011110: 2494 MHz 1011111: 2495 MHz 1100000: Undefined : 1111111: Undefined
Rev. 1.00
81
June 11, 2010
HT82M75REW/HT82K75REW
* LREG0x259 - RFCTRL59: RF Control Register 59
Bit Name Type POR Bit 7~1 Bit 0
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 3/4 R 0
Bit 1 3/4 R 0
Bit 0 PLLOPT3 R 0
Reserved: Maintain as 0b0000000 PLLOPT3: PLL Performance Optimization 1: (default) 0: (Optimized - do not change)
* LREG0x273 - RFCTRL73: RF Control Register 73
Bit Name Type POR Bit 7~6
Bit 7
Bit 6
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 PLLOPT2 R/W 0
Bit 2 PLLOPT1 R/W 0
Bit 1 PLLOPT0 R/W 0
Bit 0 3/4 R 0
VCOTXOPT1 VCOTXOPT0 R/W 0 R/W 0
VCOTXOPT [1:0]: VCO for TX Optimization 00: (default) 01: (Optimized - do not change) Reserved: Maintain as 0b00 PLLOPT [2:0]: PLL Performance Optimization 000: (default) 111: Optimized for DC-DC Converter Bypass Reserved: Maintain as 0b0
Bit 5~4 Bit 3~1
Bit 0
* LREG0x274 - RFCTRL74: RF Control Register 74
Bit Name Type POR Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAC0EN PACTRL0-2 PACTRL0-1 PACTRL0-0 PAC1EN PACTRL1-2 PACTRL1-1 PACTRL1-0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0
PAC0EN: Power Amplifier Control 0 Enable 1: Enable (default) 0: Disable PACTRL0 [2:0]: Power Amplifier Control 0 100: (default) PACTRL0 [2:0] is for 1st stage Power Amplifier current large scale control. PAC1EN: Power Amplifier Control 1 Enable 1: Enable (default) 0: Disable PACTRL1 [2:0]: Power Amplifier Control 1 100: Optimized for DC-DC on 110: Optimized for DC-DC off 010: (default) PACTRL1 [2:0] is for 2nd stage Power Amplifier current control. Please follow the TX Output Power Configuration Summary Table in LREG0x203 Register definition.
Bit 6~4
Bit 3
Bit 2-0
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* LREG0x275 - RFCTRL75: RF Control Register 75
Bit Name Type POR Bit 7~4 Bit 3~0
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 1
Bit 3 SCLKOPT3 R/W 0
Bit 2 SCLKOPT2 R/W 1
Bit 1 SCLKOPT1 R/W 0
Bit 0 SCLKOPT0 R/W 1
Reserved: Maintain as 0b0001 SCLKOPT [3:0]: Sleep Clock Optimization 0011: (Optimized - do not change) 0101: (default)
* LREG0x276 - RFCTRL76: RF Control Register 76
Bit Name Type POR Bit 7~3 Bit 2~0
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 3/4 R 0
Bit 4 3/4 R 0
Bit 3 3/4 R 0
Bit 2 SCLKOPT6 R/W 0
Bit 1 SCLKOPT5 R/W 0
Bit 0 SCLKOPT4 R/W 1
Reserved: Maintain as 0b00000 SCLKOPT [6:4]: Sleep Clock Optimization 111: (Optimized - do not change) 001: (default)
* LREG0x277 - RFCTRL77: RF Control Register 77
Bit Name Type POR Bit 7~6 Bit 5~4
Bit 7 3/4 R 0
Bit 6 3/4 R 0
Bit 5 SLPSEL1 R/W 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLPSEL0 SLPVCTRL1 SLPVCTRL0 SLPVSEL1 SLPVSEL0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0
Reserved: Maintain as 0b00 SLPSEL [1:0]: Power Saving Mode Selection 00: (default) Standby / Deep Sleep Mode 01: Undefined 10: Undefined 11: Power down Mode SLPVCTRL [1:0]: Sleep Voltage Control 00: Undefined 01: Controlled by LREG0x27 [1:0] 10: (default) automatically controlled by internal circuit 11: Undefined SLPVSEL [1:0]: Sleep Voltage Selection 00: (default - no not change)
Bit 3~2
Bit 1~0
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RF Transceiver Power-down and Wake-up
The MCU and RF Transceiver are powered down independently of each other. The method of powering down the MCU is covered in the previous MCU section of the datasheet. The RF Transceiver must be powered down before the MCU is powered down. The method of powering down the RF Transceiver is mentioned in the previous Power Saving Mode section of this datasheet. For a RF Transceiver interrupt to occur, in addition to the bits for the related enable and interrupt polarity control described in RF Transceiver Interrupt Configuration section being set, the global interrupt enable control and the related interrupt enable control bits in host MCU must also be set. If the bits related to the interrupt function are configured properly, the RF Transceiver will generate an interrupt signal on INT pin connected to the MCU I/O pin to get the attentions from MCU and then the interrupt subroutine will be serviced. If the related interrupt control bits in host MCU are not set properly, then the interrupt signal on RF Transceiver INT line will be a wake-up signal and no interrupt will be serviced.
Using the RF Transceiver Function
To use the RF Transceiver function, several important steps must be implemented to ensure that the RF Transceiver operates normally:
* The host MCU must be configured as the Master SPI. Therefore, the MCU SPI mode selection bits [M1, M0] in SPI
Interface Control Register can not be set to [1, 1] as slave mode.
* Although the SPI mode selection bits [M1, M0] can be set to [0, 0], [0, 1] and [1, 0], along with the SPI clock source
selection bit CKS, to force the host MCU SPI interface to operate as Master SPI with different baud rate, there are some limitations on the maximum SPI clock speed that can be selected to be suitable for the RF Transceiver slave SPI clock speed. As the maximum RF Transceiver slave SPI clock frequency is 5MHz, care must be taken for the combinations of the SPI clock source selection CKS and mode selection [M1, M0] when the system clock frequency is greater than 5MHz. For example, if the system clock operates at a frequency of 6MHz, the SPI mode selection [M1, M0] and clock source selection CKS should not be set to [0, 0] and 0. Doing so will obtain a Master SPI baud rate of 6MHz that is greater than the maximum clock frequency of the slave SPI which may result in SPI interface malfunction.
SPI Master/Slave/Baud rate selection bits in SBCR Register Bit Name Value Bit 6 M1 00, 01, 10 Bit 5 M0
00: SPI master mode; baud rate is fSPI 01: SPI master mode; baud rate is fSPI/4 10: SPI master mode; baud rate is fSPI/16 11: SPI slave mode (R) can not be used
SPI Clock source selection bit in SBCR Register Bit Name Value 0: fSPI = fSYS/2 1: fSPI = fSYS Bit 7 CKS 0, 1
* Since the MSB is first shifted in on SI line and shifted out on SO line for the RF Transceiver slave SPI read/write oper-
ations, the MSB/LSB selection bit MLS in MCU Master SPI SBCR register should be set to 1 for MSB shift first on SDI/SDO lines.
SPI MSB/LSB first selection bit in SBCR Register Bit Name Setting value Bit 5 MLS 1
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* As the RF Transceiver slave SPI timing diagram shows, the SPI data output mode selection SPI_MODE and the
clock polarity selection SPI_CPOL of the master SPI should be correctly set to fit the slave SPI protocol requirement. To successfully communicate with the RF Transceiver slave SPI, the SPI_MODE and SPI_CPOL of the MCU master SPI should be set to [1, 1].
SPI_MODE and SPI_CPOL setup in SPIR Register Bit Name Setting value Bit 1 SPI_MODE 1 Bit 0 SPI_CPOL 1
The relevant timing diagram for the above setting is shown in the preceding SPI Bus Timing diagram in SPI Serial Interface section.
* For the MCU master SPI to completely control the slave SPI SEN line, the MCU master SPI uses a general purpose
I/O line via application program instead of the SPI SCS line with hardware mechanism. To achieve this requirement, the software CSEN enable control bit SPI_CSEN of the Master SPI should be set to 0, then the master SPI SCS line will lose the SCS line characteristics and be configured as a general purpose I/O line.
SPI_CSEN software CSEN enable control bit in SPIR Register Bit Name Setting value Bit 5 SPI_CSEN 0
0: the software CSEN function is disabled and the SCS line is configured as an I/O line
* Finally set the SPI_EN bit to 1 to ensure that the pin-shared function for other three SPI lines known as SCK, SDI and
SDO are surely selected.
SPI_EN software SPI interface lines enable control bit in SPIR Register Bit Name Setting value Bit 5 SPI_EN 1
1: the pin-shared function of the SPI interface lines is enabled. After the above setup conditions have been implemented, the MCU can enable the SPI interface by setting the SBEN bit high. The MCU can then begin communication with the RF Transceiver using the SPI interface. The detailed MCU Master SPI functional description is provided within the SPI Serial Interface section of the MCU datasheet.
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Application Circuits with RF Transceiver
VCC_3V 47pF
15pF 47pF 32M
15pF
47pF 10nF
1uF
4.7uF VCC_3V
47pF 10nF
ANT 1.2nH 1pF 0.47pF
10nF 6.8nH
31 32 33 34 35 36 37 38 39 40
4.7nH 0.47pF VDD_3V
5.6nH
VDD_3V VDD_BG VDD_GR
VDD_A XTAL_N XTAL_P VDD_PLL VDD_CP VDD_VCO LOOP_C VDD_RF1 RF_P
VCC_3V BEAD
1 2 3 4 5 6 7 8 9 10
47uF VDD_3V 47uF 0.1uF 100uH 47uF VB 0.1uF VDD_3V 100K 0.1uF
RF_N VDD_RF2 NC VDD VSS VDD BAT_IN VSSLX LX RES
HT82M75REW
VDD_2V2 VDD_D GPIO0 GPIO1 GPIO2 PB1 PB2 PB3 PB4 PB5
30 29 28 27 26 25 24 23 22 21
10nF
PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
0.1uF
20 19 18 17 16 15 14 13 12 11
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VDD_3V VDD_3V VDD_3V 100K 0.1uF 220uF 0.1uF
0.1uF 100uH 0.1uF 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RES PA0 PA1 PA2 / TMR PA3 PA4 PA5 PB4 PB5 PB6 PB7 LX VSSLX BAT_IN VDD VSS 47uF
VB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCC_3V 10nF
PA6 PA7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GPIO2 GND_D GPIO1 GPIO0 VDD_D VDD_2V2
HT82K75REW
PB3 PB2 PB1 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PC0 PC1 VDD_RF2 N.C. RF_N
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.5pF 5.6nH 6.8nH 0.5pF ANT 1.2nH VCC_3V BEAD VDD_3V
RF_P N.C. VDD_RF1 DB5 LOOP_C DB5 VDD_VCO VDD_CP VDD_PLL GND_PLL XTAL_P XTAL_N DB4 VDD_A VDD_GR / VDD_BG VDD_3V
0.1uF
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC_3V 4.7uF
VCC_3V VCC_3V 6.8nH 0.1uF 10nF 32M VCC_3V 47pF 15pF 15pF 10nF 47pF 1uF 47pF
0.5pF
1.8pF
VCC_3V 10nF 47pF
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Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m](4) Read ROM code (locate by TBLP and TBHP) to data memory and TBLH TABRDC [m](5) Read ROM code (current page) to data memory and TBLH TABRDL [m] Read table (last page) to TBLH and Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF 2Note 2Note 2Note None None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. 4. Configuration option TBHP option is enabled 5. Configuration option TBHP option is disabled
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 91 June 11, 2010
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
Rev. 1.00
95
June 11, 2010
HT82M75REW/HT82K75REW
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.00
96
June 11, 2010
HT82M75REW/HT82K75REW
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev. 1.00
97
June 11, 2010
HT82M75REW/HT82K75REW
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.00
98
June 11, 2010
HT82M75REW/HT82K75REW
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s)
Rev. 1.00
99
June 11, 2010
HT82M75REW/HT82K75REW
TABRDC [m] Description Operation Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code TBHP is enabled) The low byte of ROM code addressed by the table pointers (TBLP and TBHP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s)
Rev. 1.00
100
June 11, 2010
HT82M75REW/HT82K75REW
Package Information
SAW Type 40-pin (6mm6mm for 0.85mm) QFN Outline Dimensions
D 31 b 30
D2 40 1
E e 21 A1 A3 A L K 20 11 10
E2
* GTK
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.031 0.000 3/4 0.007 3/4 3/4 3/4 0.173 0.173 0.014 0.008 Nom. 0.033 0.001 0.008 0.010 0.236 0.236 0.020 0.177 0.177 0.016 3/4 Dimensions in mm Min. 0.80 0.00 3/4 0.18 3/4 3/4 3/4 4.40 4.40 0.35 0.20 Nom. 0.85 0.02 0.20 0.25 6.00 6.00 0.50 4.50 4.50 0.40 3/4 Max. 0.90 0.05 3/4 0.30 3/4 3/4 3/4 4.55 4.55 0.45 3/4 Max. 0.035 0.002 3/4 0.012 3/4 3/4 3/4 0.179 0.179 0.018 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Rev. 1.00
101
June 11, 2010
HT82M75REW/HT82K75REW
64-pin LQFP (7mm7mm) Outline Dimensions
C D 48 33 G H
I 49 32 F
A B
E
64
17 K 1 16 a J
Symbol A B C D E F G H I J K a Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 0.13 1.35 3/4 0.05 0.45 0.09 0 Nom. 3/4 3/4 3/4 3/4 0.40 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Dimensions in inch Min. 0.350 0.272 0.350 0.272 3/4 0.005 0.053 3/4 0.002 0.018 0.004 0 Nom. 3/4 3/4 3/4 3/4 0.016 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 0.358 0.280 0.358 0.280 3/4 0.009 0.057 0.063 0.006 0.030 0.008 7 Max. 9.10 7.10 9.10 7.10 3/4 0.23 1.45 1.60 0.15 0.75 0.20 7
Rev. 1.00
102
June 11, 2010
HT82M75REW/HT82K75REW
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
103
June 11, 2010

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