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| SSM4513M/GM N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Low on-resistance D1 D2 D1 D2 N-CH BV DSS R DS(ON) ID 35V 36m 5.8A -35V 68m -4.3A Fast switching performance SO-8 S1 G1 G2 S2 P-CH BVDSS RDS(ON) Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G1 ID D1 D2 G2 S1 S2 The SSM4513M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well-suited for most low voltage applications. This device is available with Pb-free lead finish (second-level interconnect) as SSM4513GM. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 35 20 5.8 4.7 20 2.0 0.016 -55 to 150 -55 to 150 P-channel -35 20 -4.3 -3.4 -20 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 10/12/2004 Rev.2.01 www.SiliconStandard.com 1 of 8 SSM4513M/GM N-ch Electrical Characteristics @ T j=25 C (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage 2 o Test Conditions VGS=0V, ID=250uA Min. 35 1 - Typ. 0.03 7 6 2 3 8 7 16 3 470 90 60 Max. Units 36 60 3 1 25 100 10 750 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ T j RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=5A VGS=4.5V, ID=3A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=5A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=5A VDS=28V VGS=4.5V VDS=15V ID=1A RG=3.3 ,VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=1.7A, VGS=0V IS=5A, VGS=0V dI/dt=100A/s Min. - Typ. 17 11 Max. Units 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 10/12/2004 Rev.2.01 www.SiliconStandard.com 2 of 8 SSM4513M/GM P-ch Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=-250uA 2 Min. -35 -1 - Typ. -0.03 6 6 1 4 8 7 20 4 410 95 70 Max. Units 68 100 -3 -1 -25 100 10 660 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BVDSS/ Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Breakdown Voltage Temperature Coefficient Reference to 25C,ID=-1mA VGS=-10V, ID=-4A VGS=-4.5V, ID=-2A VDS=VGS, ID=-250uA VDS=-10V, ID=-4A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS=20V ID=-4A VDS=-28V VGS=-4.5V VDS=-15V ID=-1A RG=3.3 , VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=-1.7A, VGS=0V IS=-4A, VGS=0V dI/dt=-100A/s Min. - Typ. 21 16 Max. Units -1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board , t <10sec ; 135C/W when mounted on min. copper pad. 10/12/2004 Rev.2.01 www.SiliconStandard.com 3 of 8 SSM4513M/GM N-channel 30 30 T A =25 C o 10V 7.0V ID , Drain Current (A) 5.0V T A = 150 o C 10V 7.0V ID , Drain Current (A) 20 20 5.0V 4.5V 4.5V 10 10 V G =3.0V V G =3.0V 0 0 1 2 3 4 5 0 0 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 65 1.8 I D =3A 55 T A =25 o C Normalized RDS(ON) 1.4 I D =5A V G =10V RDS(ON0 ( m ) 45 1.0 35 25 2 4 6 8 10 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.5 5 4 3 T j =150 o C 2 T j =25 o C 1 0 0 0.2 0.4 0.6 0.8 1 1.2 Normalized VGS(th) (V) 1.1 IS(A) 0.7 0.3 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 10/12/2004 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 4 of 8 SSM4513M/GM N-channel f=1.0MHz 12 1000 VGS , Gate to Source Voltage (V) ID=5A V DS =2 8 V 9 C iss C (pF) 6 100 C oss C rss 3 0 0 4 8 12 16 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 10 0.2 1ms ID (A) 10ms 1 0.1 0.1 0.05 0.02 0.01 100ms 1s 0.1 PDM Single Pulse 0.01 t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja =135o C/W T A =25 o C Single Pulse 10s DC 10 100 0.01 0.1 1 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 10/12/2004 Rev.2.01 www.SiliconStandard.com 5 of 8 SSM4513M/GM P-Channel 30 30 T A =25 C o - 10V - 7.0V - 5.0V -ID , Drain Current (A) - 4.5V 20 T A = 150 C o - 10V - 7.0V -ID , Drain Current (A) 20 - 5.0V - 4.5V 10 10 V G = - 3.0V V G = - 3.0V 0 0 1 2 3 4 5 6 0 0 1 2 3 4 5 6 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 95 Fig 2. Typical Output Characteristics 1.8 I D = -2 A RDS(ON) (m ) 85 T A =25 C Normalized R DS(ON) 1.4 o I D = -4 A V G = - 10V 75 1.0 65 55 2 4 6 8 10 0.6 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage 4 Fig 4. Normalized On-Resistance v.s. Junction Temperature 1.5 3 Normalized -VGS(th) (V) 1.1 -IS(A) 2 T j =150 o C T j =25 o C 0.7 1 0 0.3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 10/12/2004 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 6 of 8 SSM4513M/GM P-Channel f=1.0MHz 12 1000 10 -VGS , Gate to Source Voltage (V) I D =-4A V DS =-28V C iss 8 C (pF) 6 100 C oss C rss 4 2 0 0.0 3.0 6.0 9.0 12.0 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 10 0.2 1ms -ID (A) 1 0.1 0.1 0.05 10ms 100ms 0.1 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135oC/W T A =25 o C Single Pulse 0.1 1 10 1s 10s DC 100 0.01 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 10/12/2004 Rev.2.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 of 8 SSM4513M/GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/12/2004 Rev.2.01 www.SiliconStandard.com 8 of 8 |
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