View BU9832GUL-W_4661434.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/13
STRUCTURE PRODUCT PART NUMBER PHYSICAL DIMENSION BLOCK DIAGRAM USE FEATURES
Silicon Monolithic Integrated Circuit 1,024x8 bit Electrically Erasable PROM B9832 Fig.1 (Plastic Mold) Fig.2 General purpose 1,024 words x 8 bits architecture serial EEPROM Wide operating voltage range (1.8V5.5V) Serial Peripheral Interface (CPOL,CPHA)=(0.0),(1.1) Self-timed write cycle with automatic erase Low power consumption Write ( 5V ) : 1.5mA (Typ.) Read ( 5V ) : 0.5mA (Typ.) Standby ( 5V ) : 0.1A(Typ.) Auto-increment of registers address for Read mode 32 byte Page Write mode DATA security Defaults to power up with write-disabled state Software instructions for write-enable/disable Write status register protect feature (WPB pin) Block writes protection by status register Write inhibit at low VCC WL-CSP package ------ VCSP50L2 High reliability fine pattern CMOS technology Initial data FFh in all address and 00h in status register Data retention : 40 years Endurance : 1,000,000 erase/write cycles
ABSOLUTE MAXIMUM RATING (Ta=25) Parameter Supply Voltage Power Dissipation Storage Temperature Operating Temperature Terminal Voltage *Degradation is done at 2.2mW/ Symbol VCC Rating -0.36.5 Unit V mW V
VCSP50L2 220 Tstg -65125 Topr -4085 -0.3VCC+0.3 for operation above 25
REV. B
2/13 RECOMMENDED OPERATING CONDITION Parameter Supply Voltage Input Voltage Symbol Vcc VIN Rating 1.85.5 0Vcc Unit V V
DC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-4085VCC=1.85.5V) Parameter "H" Input Voltage1 "L" Input Voltage1 "L" Output Voltage1 "L" Output Voltage2 "H" Output Voltage1 "H" Output Voltage2 Input Leakage Current Output Leakage Current Symbol Min. VIH1 VIL1 VOL1 VOL2 VOH1 VOH2 ILI ILO ICC1
0.7xVcc
Specification Unit Typ. Max.
Vcc+0.3 0.3xVcc
test condition 1.8VVcc5.5V 1.8VVcc5.5V IOL=2.1mA2.5VVcc5.5V IOL=100A1.8VVcc2.5V IOH=-0.4mA (2.5VVcc5.5V) IOH=-100A (1.8VVcc2.5V)
V V V V V V
-0.3 0 0
Vcc-0.5 Vcc-0.2
0.4 0.2 Vcc Vcc 1 1 1.0
-1 -1
A VIN=0VVcc A VOUT=0VVccCSB=Vcc
Vcc=1.8VfSCK=2MHztE/W=5ms
mA
Byte WritePage Write Write Status Register Vcc=2.5VfSCK=5MHztE/W=5ms
Operating Current Write
ICC2
2.0
mA
Byte WritePage Write Write Status Register Vcc=5.5VfSCK=5MHztE/W=5ms
ICC3
3.0
mA
Byte WritePage Write Write Status Register
ICC3 Operating Current Read ICC4 Standby Current ISB

1.5 2.0 2.0
mA mA A
Vcc=2.5VfSCK=5MHz ReadRead Status Register Vcc=5.5VfSCK=5MHz ReadRead Status Register
Vcc=5.5VCS=HOLD=WP=Vcc
SCK=SI=Vcc or GND, SO=OPEN This product is not designed for protection against radioactive rays.
MEMORY CELL CHARACTERISTICS(Ta=25Vcc=1.85.5V)
Parameter Write/Erase Cycle Data Retention 1 1 Min. 1,000,000 40 Specification Typ. Max. Unit Cycle Year
Input/Output Capacitance (Ta=25 frequency=5MHz)
Parameter Input Capacitance 1 Output Capacitance 1 Symbol CIN COUT Condition VIN=GND VOUT=GND Min. Max. Unit 8 pF 8 pF 1:Not 100% Tested
REV. B
3/13
9832
LOT NO.
Fig.1
PHYSICAL DIMENSION
REV. B
0.55
4/13
PIN CONFIGURATION
INSTRUCTION DECODE VOLTAGE DETECTION
CS
CONTROL CLOCK
SCK
GENERATION
WRITE INHIBITION
HIGH VOLTAGE GENERATOR
SI
INSTRUCTION REGISTER ADDRESS REGISTER DATA REGISTER
8bit 10bit
STATUS REGISTER
HOLD
ADDRESS DECODER R/W AMP
10bit
8,192 bit EEPROM
WP
8bit
Fig.2 BLOCK DIAGRAM
SO
PIN CONFIGURATION
C B
C1 B1 A1
C2
C3 B3
INDEX
A2 A3
POST
A 1
PIN NAME
Land No. A1 A2 A3 B1 B3 C1 C2 C3 PIN NAME WP GND SI SO SCK CS Vcc HOLD I/O IN FUNCTION
2
3
-3 BU9832GUL-W bottom view
Write Protect Input When WPEN bit is high in status register, WP input pin become active and is able to inhibit "Write Status Register"
Ground 0V
IN OUT IN IN IN
Start BitOp.codeAddressSerial Data Input Serial Data Output Serial Data Clock Input Chip Select Control Power Supp Hold Input Hold Input is able to suspend data transmission for a time.
REV. B
5/13
SYNCHRONOUS DATA TIMING
tCS tCSS
CSB
tSCKS tSCKWL tSCKWH tRC tFC
SCK
tDIS tDIH
SI SO
Hi-Z
Fig.4 DATA INPUT TIMING
SI data is latched into the chip at the rising edge of SCK clock. Address and data must be transferred from MSB.
tCS
CSB
tCSH
tSCKH
SCK
SI
tPD
tOH
tRO,tFO
tOZ Hi-Z
SO
Fig.5
INPUT AND OUTPUT TIMING
SO data toggles at the falling edge of SCK clock. Output data toggles from MSB.
"H"
CSB
"L"
tHFS
tHFH
tHRS
tHRH
SCK
tDIS
SI
n+1 tHOZ tHPD Hi-Z
n
n-1
SO HOLDB
Dn+1
Dn
Dn
Dn-1
Fig.6
HOLD TIMING
AC Condition
Parameter Symbol
Load Capacitance 1 Load Capacitance 2 Input Rise times Input Fall times Input Pulse Voltage
Input and Output Timing Reference Voltages
CL1 CL2 -
MIN -
Specification TYP 0.2Vcc/0.8Vcc 0.3Vcc/0.7Vcc
MAX 100 30 50 50
Unit pF pF ns ns V V
REV. B
6/13
AC OPERATING CHARACTERISTICS -4085 Parameter SCK clock Frequency SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time SCK Setup Time SCK Hold Time SI Setup Time SI Hold Time Output Data Delay Time1 Output Data Delay Time2 (CL2=30pF) Output Hold Time Output Disable Time Clock High Setup Time before HOLD Active. Clock Low Hold Time after HOLD Active.
Clock High Setup Time before HOLD not Active. Clock Low Hold Time after HOLD not Active. HOLD to Output High-Z HOLD to Output Valid
*Load capacitance1 CL1=100pF 2.5Vcc5.5V Min. 85 85 85 90 85 90 90 20 40 0 60 40 60 70 Typ. Max. 5 70 55 100 100 70 1 1 50 50 5 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ms
*1 Not 100% TESTED
Symbol fSCK tSCKWH tSCKWL tCS tCSS tCSH tSCKS tSCKH tDIS tDIH PD1 tPD2 tOH tOZ tHFS tHFH tHRS tHRH tHOZ tHPD *1 *1 *1 *1 tRC tFC tRO tFO tE/W
1.8Vcc2.5V Min. 200 200 200 200 200 200 200 40 50 0 120 90 120 140 Typ. Max. 2 150 145 250 250 150 1 1 100 100 5
SCK Rise Time SCK Fall Time Output Rise Time Output Fall Time Write Cycle Time
REV. B
7/13
Functional Description Status Register The device has status register. Status register consists of 8bits and is shown following parameters. 3bits(WPEN, BP0 and BP1) are set by "Write Status Register" commands, which are non-volatile. Specification of endurance and data retention are as well as memory array. WEN bit is set by "Write enable" and "Write Disable" commands. After power become on, the device is disable mode. R/B bit is a read-only and status bit. The device is clocked out value of the status register by "Read Status Register" command input. Bit7 WPEN Bit WPEN BP0/BP1 WEN Bit6 0 Bit5 0 Bit4 0 Bit3 BP1 Definition WP pin ENABLE Bit WPEN=0 no use WPEN=1 Protect Block write protection for memory array EEPROM Write enable/disable state bit WEN=0 write disable WEN=1 write enable READYBUSY status bit R/B=0 READY R/B=1 BUSY Table1. Status Register BP1 0 0 1 1 BP0 0 1 0 1 Block Write Protection None 300h-3FFh 200h-3FFh 000h-3FFh Bit2 BP0 Bit1 WEN Bit0 R/B x:Don't care
R/B
Table2. Block Write Protection WP pin The device inhibits to write the data into status register during WP is low. WPEN bit in status register needs to be high to enable WP pin function. HOLD pin HOLD pin is able to suspend data transmission for a time (Hold state). HOLD pin is normally high for transmission of the data. SCK and SI input are "Don't Care" and SO output state is Hi-Z for hold state. After HOLD pin is brought high to release hold state during SCK is low, the device resumes to transfer the data. For example, in case the device is hold state after A5 (the address data) input in read command, to resume the data transmission enable starting A4 (the address data) input after hold state is release. When CS is brought high with hold state, the device is reset and cannot resume the data transmission.
REV. B
8/13
INSTRUCTION CODE
Instruction WREN WRDI READ WRITE RDSR WRSR
Operation Write enable Write disable Read data from memory array Write data to memory array Read status register Write status register
Op.Code 0000 0110 0000 0100 0000 0011 0000 0010 0000 0101 0000 0001
Address
A9 A0 A9 A0
-
REV. B
9/13
TIMING CHART 1.WREN WRITE ENABLE
CSB
SCK
0
1
2
3
4
5
6
7
SI
0
0
0
0
0
1
1
0
SO
Hi-Z
Fig.7 WRITE ENABLE CYCLE TIMING
CSB
SCK
0
1
2
3
4
5
6
7
SI
0
0
0
0
0
1
0
0
SO
Hi-Z
Fig.8 WRITE DISABLE CYCLE TIMING
2.WRDI (WRITE DISABLE) The device has both of the enable and disable mode. After "Write Enable" is executed, the device becomes in the enable mode. After "Write Disable" is executed, the device becomes in the disable mode. After CS goes low, each of Op.code is recognized at the rising edge of 7th clock. Each of instructions is effective inputting seven or more SCK clocks. This "Write Enable" instruction must be proceeded before the any write commands. The device ignores inputting the any write commands in the disable mode. Once the any write commands is executed in the enable mode, the device becomes the disable mode. After the power become on, the device is in the disable mode.
REV. B
10/13
3.READ
CSB

14 23 24
SCK
0
1
2
3
4
5
6
7
8
30
SI
0
0
0
0
0
0
1
1
*
*
A9
A1
A0

SO
Hi-Z
D7
D6
D2
D1
D0
*=Don't care
Fig.9
READ CYCLE TIMING
The data stored in the memory are clocked out after "Read" instruction is received. After CS goes low, the address need to be sent following by Op.code of "Read". The data at the address specified are clocked out from D7 to D0, which is start at the falling edge of 23th clock. This device has the auto-increment feature that provides the whole data of the memory array with one read command, outputs the next address data following the addressed 8bits of data by keeping SCK clocking. When the highest address is reached, the address counter rolls over to the lowest address allowing the continuous read cycle.
REV. B
11/13
4.WRITE
CSB

SCK
0
1
2
3
4
5
6
7
8

23
24
30
31
SI
0
0
0
0
0
0
1
0
*
*
A9
A1
A0
D7
D6
D2
D1
D0
SO
Hi-Z
*=Don't care
Fig.10
WRITE CYCLE TIMING
This "Write" command writes 8bits of data into the specified address. After CS goes low,the address need to be sent following by Op.code of "Write". Between the rising edge of the 31th clock and it of the 32th clock, the rising edge of CS initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if CS is high except that period. It takes maximum 5ms in high voltage cycle (tE/W). The device does not receive any command except for "Read Status Register" command during this high voltage cycle. This device is capable of writing the data of maximum 32byte into memory array at the same time, which keep inputting two or more byte data with CS "L"after 8bits of data input. For this Page Write commands, the six higher order bits of address are set, the four low order address bits are internally incremented by 5bits of data input. If more than 32 words, are transmitted the address counter "roll over", and the previous transmitted data is overwritten.
REV. B
12/13
5. RDSR (READ STATUS REGISTER)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
0
0
0
0
0
1
0
1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SO
Hi-Z
WPBN
0
0
0
BP1 BP0 WEN R/B
Fig.11
READ STATUS REGISTER CYCLE TIMING
The data stored in the status register is clocked out after "Read Status Register" instruction is received. After CS goes low, Op.code of "Read Status Register" need to sent. The data stored in the status register is clocked out of the device on the falling edge of 7th clock. Bit6, Bit5 and Bit4 in the status register are read as 0. This device has the auto-increment feature as well as "Read" that outputs the 8bits of the same data following it to keep SCK clocking. It is possible to see ready and busy state by executing this command during tE/W.
REV. B
13/13
5.WRSR (WRITE STATUS RESISTER)
CSB
SCK
0
1
2
3
4
5
6
7
8
Bit7
9
Bit6
10
Bit5
11
Bit4
12
Bit3
13
Bit2
14
Bit1
15
Bit0
SI
Hi-Z
0
0
0
0
0
0
0
1
WPEN
*
*
*
BP1 BP0
*
*
SO
*=Don't care
Fig.12
WRITE STATUS REGISTER WRITE CYCLE TIMING
This "Write Status Register" command writes the data, two (BP1, BP0) of the eight bits, into the status register. Write protection is set by BP1 and BP0 bits. After CS goes low, Op.code of "Read Status Register" need to sent. Between the rising edgeof the 15th clock and it of the 16th clock, the rising edge of CS initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if CS is high exceptthat period. It takes maximum 5ms in high voltage cycle (tE/W) as well as "Write".Block write protection is determined by BP1 and BP0 bits, which is selected from quarter, half and the entire memory array. (See Table2 BLOCK WRITE PROTECTION.)
REV. B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
R0039A

▲Up To Search▲

Price & Availability of BU9832GUL-W

	To Download BU9832GUL-W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .