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| Features * Secure key storage to complement Atmel AT88SA100S and Atmel AT88SA102S Devices * Superior SHA-256 Hash Algorithm * Guaranteed Unique 48-bit Serial Number * High speed single wire interface, optionally shared with client * Supply Voltage: 2.7 - 5.25V * 1.8V - 5.5V communications voltage * <100nA Sleep Current * 4KV ESD protection * Multi-level hardware security * Secure personalization * Green compliant (exceeds RoHS) 3-pin SOT-23 and 8-pin TSSOP or SOIC packages Atmel CryptoAuthentication Host Security Chip Atmel AT88SA10HS Applications * Consumable device (battery, toner, other supplies) authentication * Network & Computer Access control * Authenticated communications for control networks * Anti-clone authentication for daughter cards * Physical access control (electronic lock & key) 1. Introduction The Atmel(R) CryptoAuthentication family of chips is the first cost-effective authentication devices to implement the SHA-256 hash algorithm, which is part of the latest set of recommended algorithms by the US Government. The 256-bit key space renders any exhaustive attacks impossible. The Atmel AT88SA10HS host version of CryptoAuthentication chips is capable of validating the response coming from the SHA-256 engine within an authentic CryptoAuthentication client (SA100S or SA102S), even if that response includes within the computation the serial number of the client. For detailed information on the cryptographic protocols, algorithm test values and usage models refer to "Atmel AT88SA100S" and "Atmel AT88SA102S" Datasheets, along with the application notes dedicated to this product family. The host CryptoAuthentication performs three separate operations (named HOST0, HOST1 & HOST2) to implement this validation. The AT88SA10HS chip takes both the challenge and response as inputs and returns a single Boolean indicating whether or not the response is valid, in order to prevent the host chip from being used to model a valid client. The host system is responsible for generating the random challenge that is sent to both the client and host CryptoAuthentication devices as AT88SA10HS does not include a random number generator. Note: The chip implements a failsafe internal watchdog timer that forces it into a very low power mode after a certain time interval regardless of any current activity. System programming must take this into consideration. Refer to Section 4.5 for more details. 8595F-SMEM-8/10 1.1. Memory Resources Fuse Block of 128-fuse bits that can be written through the one wire interface. Fuse[87] has special meanings. See Section 1.2 for more details. Fuses[88:95] are part of the manufacturer ID value fixed by Atmel(R). Fuses[96:127] are part of the serial number programmed by Atmel which is guaranteed to be unique. See Section 1.3 for more details on the Manufacturing ID and Serial Number. Metal mask programmed memory. Unrestricted reads are permitted on the first 64-bits of this array. The physical ROM will be larger and will contain other information that cannot be read. The following three fields are stored in the ROM: 2-bytes of ROM that specifies part of the manufacturing ID code. This Atmel assigned value is always the same for all chips of a particular model number. For the Atmel AT88SA10HS, this value is 0x23 01. (Appears on the bus: 0x01 23) ROM MfrID can be read by accessing ROM bytes zero and one of Address zero. 2-bytes of ROM that can be used to identify chips among others on the wafer. These bits reduce the number of fuses necessary to construct a unique serial number. The MaskSN is read by accessing ROM bytes two and three of Address zero. The serial number can always be read by the system but is never included in the message digested by the HOST command. 4-bytes of ROM that are used by Atmel to identify the model mask and/or design revision of the AT88SA10HS chip. These bytes can be freely read as the four bytes returned by ROM Address one, however system code should not depend on this value as it may change from time to time. ROM ROM MfrID ROM SN RevNum 1.2. Fuse Map AT88SA10HS incorporates 128 one-time fuses within the chip. Once burned, there is no way to reset the value of a fuse. All fuses, with the exception of the Fuse MfrID and Fuse SN bits initialized by Atmel, have a value of one when shipped from the Atmel factory and transition to zero when they are burned. These fuses are burned at system personalization and cannot be changed after that time. Table 1-1. Fuse # 0 63 64 86 87 88 95 96 127 Fuse Map Name Secret Fuses Status Fuses Fuse Disable Fuse MfrID Fuse SN Description These fuses can be securely written by the BurnSecure command but can never be read with the Read command These fuses can be written with the BurnSecure command and can always be read with the Read command The HOST commands ignore the values of Fuse[0-63] until this bit is burned. Once this bit is burned, the BurnSecure command is disabled See Section 1.3. Set by Atmel, can't be modified in the field See Section 1.3. Set by Atmel, can't be modified in the field Secret Fuses These 64-fuses are used to augment the mask programmed keys stored in the chip by Atmel. Knowledge of both the mask keys and the values of the Secret Fuses are required to calculate the response value expected by HOST2. The BurnSecure command can be used to burn an arbitrary selection of these 64-bits. 2 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip Status Fuses These 23-fuses should be used to store information which is not secret, as their value can always be determined using the Read command. Typical usage would be model or configuration information. They cannot be automatically included in the messages to be hashed by the HOST commands, but the system may read them and pass them back to HOST1 in the input stream if desired. This fuse is used to prevent access to fuses on chips in which a partial set of fuses has been burned. This fuse must be burned using the BurnSecure command. Fuse Disable 1.3. Chip Identification The chip includes a total of 72-bits of information that can be used to distinguish between individual chips in a reliable manner. The information is distributed between the ROM and fuse blocks in the following manner. Serial Number This 48-bit value is composed of ROM SN (16-bits) and Fuse SN (32-bits). Together they form a serial number that is guaranteed to be unique for all devices ever manufactured within the Atmel(R) CryptoAuthentication family. This value is optionally included in the MAC calculation. Manufacturing ID This 24-bit value is composed of ROM MfrID (16-bits) and Fuse MfrID (8-bits). Typically this value is the same for all chips of a given type. It is always included in the cryptographic computations. 1.4. Key Values The values stored in the Atmel AT88SA10HS internal key array are hardwired into the masking layers of the chip during wafer manufacture. All chips have the same keys stored internally, though the value of a particular key cannot be determined externally from the chip. For this reason, customers should ensure they program a unique (and secret) number into the 64-secret fuses and they should store the Atmel provided key values securely. Individual key values are made available to qualified customers upon request to Atmel and are always transmitted in a secure manner. When the serial number is included in the MAC calculation, the response is considered to be diversified and the host needs to know the base secret in order to be able to verify the authenticity of the client. A diversified response can also be obtained by including the serial number in the computation of the value written to the secret fuses. The AT88SA10HS provides a secure hardware mechanism to validate responses to determine if they are authentic. 1.5. SHA-256 Computation AT88SA10HS performs only one cryptographic calculation - a keyed digest of an input challenge. It optionally includes various other information stored on the chip within the digested message. The AT88SA10HS computes the SHA-256 digest based on the algorithm documented here: http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf As a security measure, the 24-bit MfrID code (both ROM and Fuse bits) is automatically included in every message digested by the AT88SA10HS. The secret fuses are conditionally appended, depending on the parameters to the HOST command. For complete sample calculations, refer to"Atmel AT88SA100S" and/or "Atmel AT88SA102S" datasheets. 3 8595F-SMEM-8/10 1.6. Security Features Atmel(R) AT88SA10HS incorporates a number of physical security features designed to protect the keys from release. These include an active shield over the entire surface of the part, internal memory encryption, internal clock generation, glitch protection, voltage tamper detection and other physical design features. Pre-programmed keys stored on AT88SA10HS are encrypted in such a way as to make retrieval of their values via outside analysis very difficult. Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two signals. 2. IO Protocol Communications to and from AT88SA10HS; take place over a single asynchronously timed wire using a pulse count scheme. The overall communications structure is a hierarchy: Table 2-1. Tokens Flags Blocks Packets IO Hierarchy Implement a single data bit transmitted on the bus, or the wake-up event Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any), which may be transmitted Data following the command and Transmit flags. They incorporate both a byte count and a checksum to ensure proper data transmission Bytes forming the core of the block without the count and CRC. They are either the input or output parameters of an Atmel AT88SA10HS command or status information from the Atmel AT88SA10HS Refer to Applications Notes on Atmel's website for more details on how to use any microprocessor to easily generate the signaling necessary to send these values to the chip. 2.1. IO Tokens There are a number of IO tokens that may be transmitted along the bus: Input: (To AT88SA10HS) Wake Zero One Wake the AT88SA10HS up from sleep (low power) state Send a single bit from system to the AT88SA10HS with a value of zero Send a single bit from system to the AT88SA10HS with a value of one Output: (From AT88SA10HS) ZeroOut Send a single bit from the AT88SA10HS to the system with a value of zero OneOut Send a single bit from the AT88SA10HS to the system with a value of one The waveforms are the same in either direction, however there are some differences in timing based on the expectation that the host has a very accurate and consistent clock while AT88SA10HS has significant variation in its internal clock generator due to normal manufacturing and environmental fluctuations. The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by the AT88SA10HS. Refer to Applications Notes on Atmel's website for more details. 4 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip 2.2. AC Parameters WAKE tWLO tWHI data comm LOGIC O tSTART tZHI tZLO tBIT LOGIC 1 tSTART NOISE SUPPRESION tLIGNORE tHIGNORE 3. Absolute Maximum Ratings* Operating Temperature .................. -40C to +85C Storage Temperature .................. -65C to + 150C Voltage on Any Pin with Respect to Ground ............... - 0.5 to VCC+0.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 5 8595F-SMEM-8/10 Table 3-1. Parameter AC Parameters Symbol Direction Min Typ Max Unit Notes Wake Low Duration t WLO To Atmel AT88SA10HS To Atmel AT88SA10HS To Atmel AT88SA10HS From Atmel AT88SA10HS 60 2.5 45 s Signal can be stable in either high or low levels during extended sleep intervals Wake Delay to t WHI Data Comm. Start pulse duration ms Signal should be stable high for this entire duration. tWHI must not exceed tTIMEOUT or the chip will transition to sleep s s s s s s s If the bit time exceeds tTIMEOUT then Atmel AT88SA10HS will enter sleep mode and the Wake token must be resent t START 4.1 4.6 4.1 4.6 4.1 4.6 37 4.34 6.0 4.34 6.0 4.34 6.0 39 4.56 8.6 4.56 8.6 4.56 8.6 - Zero transmission high pulse t ZHI To Atmel AT88SA10HS From Atmel AT88SA10HS Zero transmission low pulse t ZLO To Atmel AT88SA10HS From Atmel AT88SA10HS Bit time t BIT To Atmel AT88SA10HS From Atmel AT88SA10HS 41 28 54 60 78 95 s s Atmel AT88SA10HS will initiate the first low going transition after this time interval following the end of the Transmit flag After Atmel AT88SA10HS transmits the last bit of a block, system must wait this interval before sending the first bit of a flag ns Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Pulses shorter than this in width will be ignored by the chip when in sleep mode Turn around delay t TURNAROUND From Atmel AT88SA10HS To Atmel AT88SA10HS 15s 46ms High side glitch filter @ active t HIGNORE_A To Atmel AT88SA10HS To Atmel AT88SA10HS To Atmel AT88SA10HS To Atmel AT88SA10HS 45 Low side glitch t LIGNORE_A filter @ active Low side glitch t LIGNORE_S filter @ sleep IO Timeout 45 ns 2 45 65 85 s t TIMEOUT ms Refer to Section 4.4.1 Table 3-2. Parameter AC Parameters continued Symbol Direction Min Typ Max Unit Notes Watchdog reset Pause Length t WATCHDOG t PAUSE To Atmel AT88SA10HS - 3 18 4 25 5.7 32 s Max. time from Wake until chip is forced into sleep mode. See Section 4.5 ms Duration during which the chip will ignore IO on the bus. See PauseShort command, Section 5.7 6 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip 4. DC Parameters Table 4-1. DC Parameters Parameter Symbol Min Typ Max Unit Notes Operating temperature Power Supply Voltage Fuse Burning Voltage Active Power Supply Current TA Vcc VBURN ICC -40 2.7 3.0 - 85 5.25 5.25 6 100 C V V mA nA When chip is in sleep mode, Vcc = 5.25V, Vsig = 0.0 to 0.5V or Vsig = Vcc-0.5V to Vcc A Voltage is applied to Vcc pin Sleep Power Supply Current I SLEEP @ -40C to 55C Sleep Power Supply Current I SLEEP @ 85C 1 When chip is in sleep mode, Vcc = 5.25V, Vsig = 0.0 to 0.5V or Vsig = Vcc-0.5V to Vcc Input Low Voltage @ Vcc = 5.25V Input Low Voltage @ Vcc = 2.7V Input High Voltage @ Vcc = 5.25V Input High Voltage @ Vcc = 2.7V Input Low Voltage when Active Input High Voltage when Active Output Low voltage VIL VIL VIH VIH VIL -0.5 -0.5 .25 * Vcc 1.0 -0.5 .15 * Vcc 0.5 5.25 3.0 0.5 V V V V V Voltage levels for Wake token when chip is in sleep mode Voltage levels for Wake token when chip is in sleep mode Voltage levels for Wake token when chip is in sleep mode Voltage levels for Wake token when chip is in sleep mode When chip is in active mode, Vcc = 2.7 - 5.25V VIH 1.2 5.25 V When chip is in active mode, Vcc = 2.7 - 5.25V VOL 0.4 V When chip is in active mode, Vcc = 2.7 - 5.25V Maximum Input Voltage ESD VMAX V ESD 4 5.25 V KV Human Body Model, Sig & Vcc pins 7 8595F-SMEM-8/10 4.1. IO Flags The system is always the bus master, so before any IO transaction, the system must send an 8-bit flag to the chip to indicate the IO operation that is to be performed, as follows: Value 0x66 0x99 0xCC Name Command Transmit Sleep Meaning After this flag, the system starts sending a command block to the chip. The first bit of the block can follow immediately after the last bit of the flag After a turn-around delay, the chip will start transmitting the response for a previously transmitted command block Upon receipt of a sleep flag, the chip will enter a low power mode until the next Wake token is received All other values are reserved and will be ignored. Note: The values of flag for the Atmel AT88SA10HS host are different from that of the two clients, the Atmel AT88SA100S and Atmel AT88SA102S. In this manner, both Atmel AT88SA102S (or Atmel AT88SA100S) and Atmel AT88SA10HS can share the same communications pin on the system controller. While the AT88SA10HS will wake up when communications are sent to the client, it will ignore all such transactions. It is possible that data values transmitted to a client authentication chip (either the Atmel(R) AT88SS100S or the Atmel AT88SA102S) could be interpreted by the Atmel AT88SA10HS host chip as a legal Transmit flag. In this case there could be a bus conflict as both the host and client chips drive the signal wire at the same time. To prevent this, the PauseShort command should be used to prevent the AT88SA10HS host chip from looking at the signal wire during any IO transaction to the client. 4.1.2. Command Timing After a command flag is transmitted, a command block should be sent to the chip. During parsing of the parameters and subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin. The delays for these operations are listed in the table below: Table 4-2. Parameter Parsing Delay Host0Delay Host1Delay Host2Delay MemoryDelay SecureDelay PersonalizeDelay Command Timing Symbol t PARSE t EXEC_HOST0 t EXEC_HOST1 t EXEC_HOST2 t EXEC_READ t EXEC_SECURE t PERSON Max 100 13 7 0.5 3 36 13 Unit Notes s ms ms ms ms ms ms Delay to check CRC and parse opcode and parameters before an error indication will be available Delay to execute any of the HOST0 command Delay to execute any of the HOST1 command Delay to execute any of the HOST2 command Delay to execute Read command Max delay to execute BurnSecure command at VCC > 4.5V See Section 5.6 for more details Delay to execute GenPersonalizationKey In this document, tEXEC is used as shorthand for the delay corresponding to whatever command has been sent to the chip. 8 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip 4.1.3. Transmit Flag The Transmit flag is used to turn around the signal so that the Atmel(R) AT88SA10HS can send data back to the system, depending on its current state. The bytes that the AT88SA10HS returns to the system depend on its current state as follows: Table 4-3. Return Codes Error/Status Description 0x11 - Indication that a proper Wake token has been received by the Atmel AT88SA10HS Return bytes per "Output Parameters" in Command section of this document. In some cases this is a single byte with a value of 0x00 indicating success. The Transmit flag can be resent to the Atmel AT88SA10HS repeatedly if a reread of the output is necessary Command was properly received but could not be executed by the Atmel AT88SA10HS. Changes in the Atmel AT88SA10HS state or the value of the command bits must happen before it is re-attempted Command was NOT properly received by the Atmel AT88SA10HS and should be re-issued by the system. No attempt was made to execute the command State Description After Wake, but prior to first command After successful command execution Execution error 0x0F After CRC or other communications error 0xFF The AT88SA10HS always transmits complete blocks to the system, so in the above table, the status/error bytes result in 4 bytes going to the system - count, error, CRC x 2. After receipt of a command block, the AT88SA10HS will parse the command for errors, a process which takes tPARSE (Refer to Section 4.2.2). After this interval the system can send a Transmit token to the AT88SA10HS - if there was an error, the AT88SA10HS will respond with an error code. If there is no error, the AT88SA10HS internally transitions automatically from t PARSE to t EXEC and will not respond to any Transmit tokens until both delays are complete. 4.1.4. Sleep Flag The sleep flag is used to transition the AT88SA10HS to the low power state, which causes a complete reset of the AT88SA10HS's internal command engine and input/output buffer. It can be sent to the AT88SA10HS at any time when the AT88SA10HS will accept a flag. To achieve the specified I SLEEP, Atmel recommends that the input signal be brought below VIL when the chip is asleep. To achieve ISLEEP if the sleep state of the input pin is high, the voltage on the input signal should be within 0.5V of VCC to avoid additional leakage on the input circuit of the chip. The system must calculate the total time required for all commands to be sent to the AT88SA10HS during a single session, including any inter-bit/byte delays. If this total time exceeds tWATCHDOG then the system must issue a partial set of commands, then a Sleep flag, then a Wake token, and finally after the Wake delay, issue the remaining commands. 9 8595F-SMEM-8/10 4.2. IO Blocks Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way: Byte Number 0 Name Count Meaning Number of bytes to be transferred to the chip in the block, including count, packet and checksum, so this byte should always have a value of (N+1). The maximum size block is 39 and the minimum size block is four. Values outside this range will cause unpredictable operation. Command, parameters and data, or response. Refer to Section 4.1.3 & Section 4 for more details. CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial register value should be 0 and after the last bit of the count and packet have been transmitted the internal CRC register should have a value that matches that in the block. The first byte transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the most significant byte of the CRC. 1 to (N-2) Packet N-1, N Checksum 4.3. IO Flow The general IO flow for the commands is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. System sends Wake token System sends Transmit flag Receive 0x11 value from Atmel AT88SA10HS to verify proper wakeup synchronization. System sends Command flag System sends complete command block System waits tPARSE for the Atmel AT88SA10HS to check for command formation errors System sends Transmit flag. If command format is OK, the Atmel AT88SA10HS ignores this flag because the computation engine is busy. If there was an error, the Atmel AT88SA10HS responds with an error code System waits tEXEC, Refer to Section 4.1.1 System sends Transmit flag Receive output block from the Atmel AT88SA10HS, system checks CRC If CRC from Atmel AT88SA10HS is incorrect, indication transmission error, system resends Transmit flag System sends sleep flag to the Atmel AT88SA10HS Where the command in question has a short execution delay the system should omit steps six, seven and eight and replace this with a wait of duration tPARSE + tEXEC. 4.4. Synchronization Because the communications protocol is half duplex, there is the possibility that the system and the Atmel(R) AT88SA10HS will fall out of synchronization with each other. In order to speed recovery, AT88SA10HS implements a timeout that forces the AT88SA10HS to sleep. 4.4.1. IO Timeout After a leading transition for any data token has been received, AT88SA10HS will expect the remaining bits of the token to be properly received by the chip within the tTIMEOUT interval. Failure to send enough bits or the transmission of an illegal token (a low pulse exceeding tZLO) will cause the chip to enter the sleep state after the tTIMEOUT interval. The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the IO Timeout circuitry is enabled until the last expected data bit is received. Note that the timeout counter is reset after every legal token, so the total time to transmit the command may exceed the tTIMEOUT interval while the time between bits may not. 10 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip In order to limit the active current if the Atmel(R) AT88SA10HS is inadvertently awakened, the IO Timeout circuitry is also enabled when the AT88SA10HS receives a wake-up. If the first token does not come within the tTIMEOUT interval, the AT88SA10HS will go back to the sleep mode without performing any operations. The IO Timeout circuitry is disabled when the chip is busy executing a command. 4.4.2. Synchronization Procedures When the system and the AT88SA10HS fall out of synchronization, the system will ultimately end up sending a Transmit flag which will not generate a response from the AT88SA10HS. The system should implement its own timeout which waits for tTIMEOUT during which time the AT88SA10HS should go to sleep automatically. At this point, the system should send a Wake token and after tWLO + tWHI, a Transmit token. The 0x11 status indicates that the resynchronization was successful. It may be possible that the system does not get the 0x11 code from the AT88SA10HS for one of the following reasons: 1. The system did not wait a full tTIMEOUT delay with the IO signal idle in which case the Atmel AT88SA10HS may have interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the tTIMEOUT delay and re-issue the Wake token. 2. The Atmel AT88SA10HS went into the sleep mode for some reason while the system was transmitting data. In this case, the Atmel AT88SA10HS will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct CRC. Recommended resolution is to wait the tTIMEOUT delay and re-issue the Wake token. 3. There are some internal error conditions within the Atmel AT88SA10HS which will be automatically reset after a tWATCHDOG interval, see below. There is no way to externally reset the Atmel AT88SA10HS - the system should leave the IO pin idle for this interval and issue the Wake token. 4.5. Watchdog Failsafe After the Wake token has been received by the AT88SA10HS, a watchdog counter is started within the chip. After tWATCHDOG, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again. This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state machines of the AT88SA10HS including any IO synchronization issue, power consumption will fall to the low sleep level automatically. 4.6. Byte & Bit Ordering The AT88SA10HS is a little-endian chip: * All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order received * Data is transferred to/from the Atmel AT88SA10HS least significant bit first on the bus * In this document, the most significant bit and/or byte appears towards the left hand side of the page 11 8595F-SMEM-8/10 5. Commands The command packet is broken down in the following way: Byte 0 1 2-3 4+ Name Opcode Param1 Param2 Data Meaning The Command code The first parameter - always present The second parameter - always present Optional remaining input data If a command fails because the CRC within the block is incorrect or there is some other communications error, then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be all ones. In this situation, the system should re-transmit the command block including the proceeding Transmit flag - providing there is sufficient time before the expiration of the watchdog timeout. If the opcode is invalid, one of the parameters is illegal, or the Atmel(R) AT88SA10HS is in an illegal state for the execution of this command, then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be 0x0F. In this situation, the condition must be corrected before the (modified) command is sent back to the AT88SA10HS. If a command is received successfully, the system will be able to retrieve the output block as described in the individual command descriptions below after the appropriate execution delay. In the individual command description tables following, the "Size" column describes the number of bytes in the parameter documented in each particular row. The total size of the block for each of the commands is fixed, though that value is different for each command. If the block size for a particular command is incorrect, the chip will not attempt the command execution and returns an error. 5.1. HOST0 Concatenates the key stored in AT88SA10HS with an input 256-bit challenge and generates the digest of this message. The result is left in internal memory and cannot be read. In general, the challenge should be a random number generated by the host system, which will be sent to both the host (AT88SA10HS) and client (Atmel AT88SA100S or Atmel AT88SA102S). Table 5-1. Input Parameters Name Opcode Param1 Param2 Data Table 5-2. Name Success HOST0 Overwrite KeyID Challenge Size 1 1 2 32 Notes 0x08 If non-zero, overwrite part of internally generated key with secret fuses The internal key to be used to generate the digest Challenge to be sent to the client Atmel AT88SA100S or Atmel AT88SA102S Output Parameters Size 1 Notes Upon successful completion of HOST0, a value of zero will be returned by Atmel AT88SA10HS 12 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip The 512-bit message block that will be hashed with the SHA-256 algorithm will consist of: 256-bits 256-bits key[KeyID] challenge If the overwrite parameter is 0, then the 512-bit message block that will be hashed using the SHA-256 algorithm will consist of: 256-bits 256-bits key[KeyID] challenge If the overwrite parameter has a value of 0x01, then the 512-bit message block that will be hashed using the SHA256 algorithm will consist of: 192-bits 64-bits 256-bits key[KeyID] Fuse[0-63] challenge All other values of the overwrite parameter are not recommended for use. 5.2. HOST1 Completes the two block SHA-256 digest started by HOST0 and leaves the resulting digest within the internal memory of the Atmel(R) AT88SA10HS. This command returns an error if HOST0 has not been successfully run previously within this Wake cycle. As a security precaution, this command does not return the digest. A subsequent command is required to compare the response generated by the client with the one generated by the host. Table 5-3. Input Parameters Name Opcode Param1 Param2 Data Table 5-4. Name Success HOST1 Mode Zero OtherInfo Output Parameters Size 1 Notes Upon successful completion of HOST1, a value of 0 will be returned by Atmel AT88SA10HS Size 1 1 2 13 Notes 0x40 Controls composition of message, see below for details Must be 0x00 00 Input portion of message to be digested 13 8595F-SMEM-8/10 The contents of the second block to be digested are listed below. Note: Size 32-bits 64-bits 24-bits 8-bits 32-bits 1 6-bits 16-bits To simplify this documentation; the bit addresses for OtherInfo are listed in the table below Source OtherInfo[0-31] Fuse[0-63] OtherInfo[32-55] Fuse[88-95] OtherInfo[56-87] ROM MfrID OtherInfo[88-103] Notes Opcode, param1 & param 2 values sent to Atmel AT88SA100S/AT88SA102S If enabled by bit five of the input mode parameter and if Fuse[87] is burned, else forced to zero Status fuse values from Atmel ATSA100S/AT88SA102S, or zeros Fuse MfrID, should match between Atmel AT88SA10HS and Atmel AT88SA100S/AT88SA102S Fuse SN from Atmel AT88SA100S/AT88SA102S (Fuse[96-127]), or zeros Should match between Atmel AT88SA10HS and Atmel AT88SA100S/AT88SA102S ROM SN from Atmel AT88SA100S/AT88SA102S, or zeros These bits are followed by the necessary `1' bit, `0' padding and 64-bit length as specified in the SHA-256 specification. 5.2.1.1. Mode Encoding Bit five of the mode is used to indicate whether or not the secret fuse bits are to be included in the calculation. The remaining bits of the mode field are ignored by Atmel(R) AT88SA10HS and should be zero. Table 5-5. Bit[5] 0 1 Mode Encoding Fuse Block No fuse values inserted Insert the values of Fuse[0-63] in the message If Fuse[87] has not been burned, then the values of Fuse[0-63] will be replaced by zeros in the above message generation step as a security measure. 5.3. HOST2 Compares the value previously generated by the AT88SA10HS using HOST0 and HOST1 with that on the input stream coming from the client and returns status to indicate whether or not the two matched. This command returns an error if HOST1 has not been previously successfully run within this Wake cycle. If the two digests do not match, the AT88SA10HS provides no information as to the source of the mismatch, which must be deduced from the inputs to the three HOSTX commands. On a match failure, the entire set of HOST0, HOST1 & HOST2 commands must be re-executed - HOST2 cannot be repeatedly executed. 14 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip Table 5-6. Input Parameters Name Opcode Param1 Param2 Data Table 5-7. Name Success HOST2 Zero1 Zero2 ClientResponse Output Parameters Size 1 Notes If the input ClientResponse matches the internally generated response, a value of zero will be returned by Atmel AT88SA10HS after a THOST delay. If the two digests do NOT match, a value of 0x0F will be returned after a THOST delay Size 1 1 2 32 Notes 0x80 Must be 0x00 Must be 0x00 00 Response from the client 5.4. Read Reads 4-bytes from Fuse or ROM; returns an error if an attempt is made to read any fuses or ROM locations which are illegal. Table 5-8. Input Parameters Name Opcode Param1 Param2 Data Table 5-9. Name Contents Read Mode Address Ignored Output Parameters Size 4 Notes The contents of the specified memory location Size 1 1 2 0 Notes 0x02 Fuse or ROM Which 4-bytes within array. Only bits zero and one are used, all others must be zeros Table 5-10. Mode Encoding Name ROM Fuse Value 0x00 0x01 Notes Reads four bytes from the ROM. Bit one of the address parameter must be zero Reads the value of 32-fuses. Bit one of the address parameter must be one 5.5. GenPersonalizationKey Loads a personalization key into internal memory and then uses that key along with an input seed to generate a decryption digest using SHA-256. Neither the key nor the decryption digest can be read from the chip. Upon completion, an internal bit is set indicating that a secure personalization digest has been loaded and is ready to use by the BurnSecure command. This bit is cleared (and the digest lost) when the watchdog timer expires or the power is cycled. This command will fail if Fuse[87] has been burned. 15 8595F-SMEM-8/10 Table 5-11. Input Parameters Name Opcode Param1 Param2 Data GenPers Zero KeyID Seed Size 1 1 2 16 Notes 0x20 Must be 0x00 Identification number of the personalization key to be loaded Seed for digest generation. The least significant bit of the last byte is ignored by Atmel AT88SA10HS Table 5-12. Output Parameters Name Success Size 1 Notes Upon successful execution, a value of zero will be returned by Atmel AT88SA10HS The SHA-256 message body used to create the resulting digest internally stored in the chip consists of the following 512-bits: 256-bits 64-bits 127-bits 1-bits 64-bits PersonalizeKey[KeyID] Fixed value of all ones Seed from input stream `1' pad length of message in bits, fixed at 447 5.6. BurnSecure Burns any combination of the first 88-fuse bits. Verification that the proper secret fuse bits have been burned must occur using the MAC command - there is no way to read the values in the first 64-fuses to verify their state. The 24-status fuses can be verified with the Read command. The fuses to be burned are specified by the 88-bit input map parameter. If a bit in the map is set to a `1', then the corresponding fuse is burned. If a bit in the map parameter is zero, then the corresponding fuse is left in its current state. The first bit sent to Atmel(R) AT88SA10HS corresponds to Fuse[0] and so on up to Fuse[87]. Note: Since a `1' bit in the Map parameter results in a `0' data value in the actual fuse array, the value in the Map parameter should be the inverse of the desired secret or status value. See Section 1.2 for more details To facilitate secure personalization of the AT88SA10HS, this map may be encrypted before being sent to the chip. If this mode is desired, then the Decrypt parameter should be set to one in the input parameter list. The decryption (transport) key is computed by the GenPersonalizationKey command, which must have been run immediately prior to the execution of BurnSecure. In this case, prior to burning any fuses, the input Map parameter is XOR'd with the first 88-bits of that digest from the GenPersonalizationKey command. The GenPersonalizationKey and BurnSecure commands must be run within a single Wake cycle prior to the expiration of the watchdog timer. The power supply pin must meet the VBURN specification during the entire BurnSecure command in order to burn fuses reliably. If VCC is greater than 4.5V, then the BurnTime parameter should be set to 0x00 and the internal burn time will be 250s. If Vcc is less than 4.5V but greater than VBURN then the BurnTime parameter should be set to 0x8000 and the internal burn time will be 190ms per fuse bit burned. The chip does NOT internally check the supply voltage level. 16 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip The total BurnSecure execution delay is directly proportional to the total number of fuses being burned. If VCC is less than 4.5V, then the total BurnSecure execution time may exceed the interval remaining before the expiration of the watchdog timer. In this case, the BurnSecure command should be run repeatedly, with each repetition burning only as many fuses as there is time available. The system software is responsible for counting the number of `1' bits in the clear-text version of the map parameter sent to the chip - no error is returned if the fuse burn count is too high. Other than Fuse[87] (see below), the fuses may be burned in any order. Prior to execution of BurnSecure, Atmel(R) AT88SA10HS verifies that Fuse[87] is un-burned. If it has been burned, then the BurnSecure command will return an error. Fuse[87] must be burned during the last repetition of BurnSecure, optionally in combination with other fuses. There are a series of very small intervals during tEXEC_SECURE when the fuse element is actually being burned. The power supply must not be removed during this interval and the watchdog timer must not be allowed to expire during this interval, or the fuse may end up in a state where it reads as un-burned but cannot be burned. Table 5-13. Input Parameters Name Opcode Param1 Param2 Data BURNSECURE Decrypt BurnTime Map Size 1 1 2 11 Notes 0x10 If one, decrypt Map data before usage. If zero, the map is transmitted in plain text Must be 0x00 00 if VCC > 4.5V, must be 0x80 00 otherwise Which fuses to burn, may be encrypted Table 5-14. Output Parameters Name Success Size 1 Notes Upon successful execution, a value of zero will be returned by Atmel AT88SA10HS This command takes a constant time to execute regardless of the number of fuses being burned. 5.7. PauseShort Forces the chip into a busy mode for a period of tPAUSE. During execution of this command the chip will ignore all activity on the IO signal. This command is used to prevent bus conflicts in a system that also includes one or more Atmel AT88SA100S or Atmel AT88SA102S client chips sharing the same signal wire. Table 5-15. Input Parameters Name Opcode Param1 Param2 Data PAUSESHORT Ignored Ignored Ignored Size 1 1 2 0 Notes 0x00 Must be 0x00 Must be 0x00 00 Table 5-16. Output Parameters Name Success Size 1 Notes After a delay of tPAUSE, the Atmel AT88SA10HS will return a value of zero in response to a Transmit flag 17 8595F-SMEM-8/10 6. Pinout Table 6-1. Pin # 1 SOT Pin Definitions Name Signal Description IO channel to the system, open drain output. It is expected that an external pull-up resistor will be provided to pull this signal up to VCC for proper communications. When the chip is not in use this pin can be pulled to either VCC or VSS Power supply, 2.7 - 5.25V. This pin should be bypassed with a high quality 0.1F capacitor close to this pin with a short trace to VSS. Refer to Applications Notes on Atmel's website for more details Connect to system ground 2 3 Table 6-2. Pin # 4 5 VCC VSS TSSOP and SOIC Pin Definitions Name VSS Signal Description Connect to system ground IO channel to the system, open drain output. It is expected that an external pull-up resistor will be provided to pull this signal up to VCC for proper communications. When the chip is not in use this pin can be pulled to either VCC or VSS Power supply, 2.7 - 5.25V. This pin should be bypassed with a high quality 0.1F capacitor close to this pin with a short trace to VSS. Additional applications information at www.atmel.com 8 VCC 18 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip 7. Package Drawing 3TS1 - Shrink SOT 3 GND C L E1 E SDA 1 e1 2 VCC Top View End View b A2 SEATING PLANE A e D A1 Side View L1 Notes: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.25mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15mm from the lead tip. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE This drawing is for general information only. Refer to JEDEC Drawing TO-236, Variation AB for additional information. A A1 A2 D E E1 L1 e1 b 0.89 0.01 0.88 2.80 2.10 1.20 2.90 1.30 0.54 REF 1.90 BSC 0.30 - 1.12 0.10 1.02 3.04 2.64 1.40 1,2 1,2 0.50 3 12/11/09 TITLE R Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. 3TS1, 3-lead, 1.30mm Body, Plastic Thin Shrink Small Outline Package (Shrink SOT) TBG 3TS1 B 19 8595F-SMEM-8/10 8A2 -TSSOP 4321 Pin 1 indicator this corner E1 E L1 5678 L End View Top View SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 RE3 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5 b A D E E1 A e D A2 A2 b e L L1 Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 12/11/09 TITLE GPC DRAWING NO. 8A2 REV. D Package Drawing Contact: packagedrawings@atmel.com 8A2, 8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) TNR 20 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 Atmel AT88SA10HS Host Authentication Chip 8S1 - JEDEC SOIC C 1 E E1 N L Top View End View e b A A1 SYMBOL A A1 b C D COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE D E1 E e Side View L Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C 21 8595F-SMEM-8/10 8. Ordering Codes Ordering Code AT88SA10HS-TSU-T Package Type SOT, Tape & Reel Voltage Range 2.7V-5.25V Temperature Range Green compliant (exceeds RoHS)/Industrial (-40C to 85C) Green compliant (exceeds RoHS)/Industrial (-40C to 85C) Green compliant (exceeds RoHS)/Industrial (-40C to 85C) AT88SA10HS-TH-T TSSOP, Tape & Reel 2.7V-5.25V AT88SA10HS-SH-T SOIC, Tape & Reel 2.7V-5.25V 9. Revision History Doc. Rev. 8595F 8595E 8595D 8595C 8595B 8595A Date 08/2010 06/2010 05/2010 04/2010 02/2010 04/2009 Comments Update IO Timeout description Update to Table 3: AC Parameters Expansion of IO Timeout specification Added 8ld TSSOP Updated parameter tables and added 8ld SOIC Initial document release 22 Atmel AT88SA10HS Host Authentication Chip 8595F-SMEM-8/10 He ad q ua rt e rs Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com In t er n at io n al Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) (3) 3523-3551 Fax: (+81) (3) 3523-7581 P ro d u ct Co n t a ct Technical Support securemem@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2010 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, and others are registered trademarks, CryptoAuthenticationTM and others, are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8595F-SMEM-8/10 |
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