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| iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 1/59 FEATURES o o o o o o o o o o o o o o o o 3 chan. simultaneous sampling 13 bit sine-to-digital conversion Differential and single-ended PGA inputs to 200 kHz Input adaptation to current or voltage signals Adjustable signal conditioning for offset, amplitude and phase Input signal stabilization by LED or MR bridge supply tracking (via controlled 50 mA and 2 x 10 mA highside sources) 2 or 3 track nonius calculation of up to 25 bit singleturn position Data update within 7 s supported by flash period counting Serial 2-wire interface to multiturn sensors (BiSS, SSI, 2-bit) Fast, serial I/O interface with fail-safe RS422 transceiver (SSI to 4 MHz, BiSS C to 10 MHz) Differential 1 Vpp sin/cos outputs to 100 , short-circuit-proof Position preset function, selectable up/down code direction Signal and system monitoring with configurable error/warning messaging and diagnosis memory Device setup via I/O interface (BiSS) or serial EEPROM Reverse-polarity-proof and tolerant against faulty output wiring Power-good switch protecting the peripheral circuitry Single 5 V supply, operation from -40 to +95 (+110) C APPLICATIONS o Multi-channel sine-to-digital converter o Optical and magnetic position sensors o Singleturn and multiturn absolute encoders o Linear scales for absolute position o Resolver systems PACKAGES QFN48 7x7 BLOCK DIAGRAM Copyright (c) 2010 iC-Haus http://www.ichaus.com iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 2/59 DESCRIPTION Encoder device iC-MN is a 3-channel, simultaneous sampling sine-to-digital converter which interpolates sine/cosine sensor signals using a high precision SAR converter with a selectable resolution of up to 13 bits. Each input has a separate sample-and-hold stage which halts the track signal for the subsequent sequential digitization. Various 2- and 3-track Vernier scale computations (after Nonius) can be configured for the calculation of high resolution angle positions; these computations permit angle resolutions of up to 25 bits. The absolute angle position is output via the serial Interface with clock rates of up to 4 Mbit/s (SSI compatible; up to 10 Mbit/s with BiSS C protocol). The RS422 transceiver required to this end is integrated on the chip and has both a differential clock input and a differential line driver for data output. Programmable instrumentation amplifiers with a selectable gain and offset and phase correction can be adjusted separately for each channel; these allow differential or single-ended input signals. At the same time the inputs can either be set to high impedance for voltage signals from magneto resistor sensor bridges, for example, or to low impedance for adaptation and use with photosensors which provide current signals, for instance. This enables the device to be directly connected up to a number of different optical and magnetic sensors. For the purpose of input signal stabilization the conditioned signals are fed into signal level controllers featuring current source outputs of up to 50 mA (master channel) and of up to 10 mA (for the nonius and segment channels each). These ACOx source pins either power the LEDs of an optical encoder or the magneto resistor bridges of a magnetic encoder. If the control thresholds are reached this event can be released for alarm messaging using the serial interface or the NERR output. Both major chip functions and sensor errors are also monitored and can be enabled for alarm indication. In this manner typical sensor errors, such as signal loss due to wire breakage, short circuiting, dirt or aging, for example, can be signaled by alarms. The device features further digital encoder functions covering the correction of phase errors between the tracks, for example, or the zeroing or presetting of a specific position offset for data output. Using the SSI master also integrated on the chip position data from multiturn sensors, provided by a second iC-MN, for example, can be read in and synchronized. iC-MN is protected against a reversed power supply voltage; the integrated supply switch for loads of up to 20 mA extends this protection to cover the overall system. The device is configured via an external EEPROM. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 3/59 CONTENTS PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS OPERATING REQUIREMENTS: I/O Interface CONFIGURATION PARAMETERS REGISTER MAP (EEPROM) OPERATING MODES and CALIBRATION PROCEDURES Calibration Using Comparated Sine/Cosine Signals . . . . 5 6 6 7 15 16 17 S/D CONVERSION with MULTITURN SYNCHRONIZATION Op. Mode Descriptions Of Multiturn Modes MODE_ST Code 0x0C . . . . . . . . . . . . MODE_ST Code 0x0D . . . . . . . . . . . . MODE_ST Code 0x0E . . . . . . . . . . . . MODE_ST Code 0x0F . . . . . . . . . . . . S/D CONVERSION with DIRECT OUTPUT Op. Mode Descriptions Of Direct Output Modes . . . . . . . . . . . . . . . . MODE_ST Code 0x0C . . . . . . . . . . MODE_ST Code 0x0D . . . . . . . . . . MODE_ST Code 0x0E . . . . . . . . . . MODE_ST Code 0x0F . . . . . . . . . . TRACK OFFSET CALIBRATION I/O INTERFACE Protocol . . . . . . . . . . . . . . . . . . . . . Output Data Length . . . . . . . . . . . . . . Output Options . . . . . . . . . . . . . . . . . I/O INTERFACE with EXTENDED FUNCTIONS Protocol . . . . . . . . . . . . . . . . . . . . . Output Data Length . . . . . . . . . . . . . . Output Options . . . . . . . . . . . . . . . . . Safety Application Settings . . . . . . . . . . Busy Register . . . . . . . . . . . . . . . . . . CONFIGURATION OF DIGITAL DRIVER OUTPUTS COMMAND and STATUS REGISTERS Execution Of Internal Commands . . Execution Of Protocol Commands . Automatic Reset Function . . . . . . Status Register . . . . . . . . . . . . Non-Volatile Diagnosis Memory . . . . . . . . 33 33 33 33 33 33 34 21 22 . . . . . . . . . . . . . . . 34 34 34 34 34 35 36 36 36 37 38 38 39 39 40 40 SIGNAL CONDITIONING for MASTER-, SEGMENT- and NONIUS-Channel (x= M,S,N) 23 Current Signals . . . . . . . . . . . . . . . . . Voltage Signals . . . . . . . . . . . . . . . . . Gain Adjustment . . . . . . . . . . . . . . . . Offset Calibration . . . . . . . . . . . . . . . . Phase Correction . . . . . . . . . . . . . . . . ANALOG PARAMETERS Signal Level Controller . . . . . . . . . . . . . Bias Current Source . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . Signal Noise Filters . . . . . . . . . . . . . . . SINE-TO-DIGITAL CONVERSION MODES Internal Bit Lengths .............. 23 23 24 24 26 27 27 28 28 28 29 29 41 42 42 42 42 43 43 44 45 46 46 47 48 S/D CONVERSION with NONIUS CALCULATION Output Data Verification . . . . . . . . . . . . Op. Mode Descriptions Of Nonius Modes . . MODE_ST Codes 0x00, 0x01, 0x02 . . . . . MODE_ST Codes 0x03, 0x04 . . . . . . . . . MODE_ST Codes 0x05, 0x06, 0x7 . . . . . . MODE_ST Codes 0x08, 0x09, 0xA . . . . . . MODE_ST Code 0x0B . . . . . . . . . . . . . Principle PPR And Bit Length Dependencies Digital Frequency Monitoring . . . . . . . . . 30 30 30 30 30 31 31 31 31 32 . . . . . . . . . . . . . . . . . . . . . . . . . ERROR AND WARNING BIT Visibility Of Latched Status Messages . . . . MT INTERFACE Configuration Of Data Lengths . . . . . . . . Error Handling . . . . . . . . . . . . . . . . . MT Interface with 2-bit mode . . . . . . . . . iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 4/59 MT INTERFACE with EXTENDED FUNCTIONS Direct Communication To Multiturn Sensor . PRESET FUNCTION STARTUP BEHAVIOR EEPROM INTERFACE Memory Map And Register Access . . . . . . Direct Addressing . . . . . . . . . . . . . . . 49 49 50 51 APPLICATION NOTES: PLC Operation 52 52 52 PLC Operation . . . . . . . . . . . . . . . . . DESIGN REVIEW: Notes On Chip Functions 57 57 58 Bank-Wise Addressing . . . . . . . . . . . . . APPLICATION NOTES: Configuration As BiSS C-Slave Including EDS (Electronic Data Sheet) 52 55 iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 5/59 PACKAGES PIN CONFIGURATION QFN48 PIN FUNCTIONS No. Name Function 1 NSINS Signal Input Sine - (Segment) 2 PSINS Signal Input Sine + (Segment) 3 PCINS Signal Input Cosine + (Segment) 4 NCINS Signal Input Cosine - (Segment) 5 NSINM Signal Input Sine - (Master) 6 PSINM Signal Input Sine + (Master) 7 PCINM Signal Input Cosine+ (Master) 8 NCINM Signal Input Cosine - (Master) 9 NSINN Signal Input Sine - (Nonius) 10 PSINN Signal Input Sine + (Nonius) 11 PCINN Signal Input Cosine + (Nonius) 12 NCINN Signal Input Cosine - (Nonius) 13 n.c. 14 n.c. 15 n.c. 16 n.c. 17 DIR Sense of Rotation Preselection Input, Calibration Signal IPB 18 PRES Preset Input 19 SCL EEPROM Interface, clock line 20 SDA EEPROM Interface, data line PIN FUNCTIONS No. Name Function 21 MAO I/O Interface, clock output 22 SLI I/O Interface, data input 23 NMA* I/O Interface, clock input 24 MA* I/O Interface, clock input + 25 NSLO* I/O Interface, data output 26 SLO* I/O Interface, data output + 27 MTSLI Multiturn Interface, data input 28 T3 External Trigger Input, Test Signal Input 29 MTMA Multiturn Interface, clock output 30 T2 Test Signal Input 31 GND* Ground 32 VDD* +4.5 to 5.5 V Supply Voltage 33 NERR* Error Message Output, System Error Message Input 34 n.c. 35 n.c. 36 n.c. 37 NSOUT* Analog Output Sine - (Master) 38 PSOUT* Analog Output Sine + (Master) 39 NCOUT* Analog Output Cosine - (Master) 40 PCOUT* Analog Output Cosine + (Master) 41 T0 Test Signal Output 42 T1 Test Signal Output 43 ACOM* Signal Level Controller Outp. (Master) 44 VACO* +4.5 to 5.5 V Signal Level Controller Supply 45 ACON* Signal Level Controller Output 46 ACOS* Signal Level Controller Output, VREFin Ref. Voltage Input/Output 47 GNDA Sub-System Ground Output 48 VDDA Sub-System Positive Supply Output *: n.c. : Pin is immune against faulty output or supply connection. Pin is not connected. Wiring unused input pins can be recommended, especially for pins SLI, DIR, PRES and T2 (to GNDA). For calibrating the internal bias current source a pull-down resistor of 5 k 1 % connected from pin DIR to GNDA is useful (see Figure 10). To improve heat dissipation the thermal pad of the QFN package (bottom side) should be joined to an extended copper area which must have GNDA potential. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 6/59 ABSOLUTE MAXIMUM RATINGS These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Voltage at VDD, GND, NSLO, SLO, NERR, PSOUT, NSOUT, PCOUT, NCOUT, VACO Voltage at MA, NMA Pin-to-Pin Voltage vs. VDD, GND, NSLO, SLO, NERR, PSOUT, NSOUT, PCOUT, NCOUT, VACO Voltage at NSINS, PSINS, PCINS, referenced to AGND, V() < VDD + 0.3 V NCINS, NSINM, PSINM, PCINM, NCINM, NSINN, PSINN, PCINN, NCINN, DIR, PRES, SCL, SDA, MAO, SLI, MTSLI, T2, MTMA, T3, T0, T1, ACOM, ACON, ACOS, GNDA, VDDA Current in VDD Current in VDDA, GNDA, PSOUT, NSOUT, PCOUT, NCOUT Current in PSINM, NSINM, PCINM, NCINM, PSINS, NSINS, PCINS, NCINS, PSINN, NSINN, PCINN, NCINN, DIR, PRES, SCL, SDA, MAO, SLI, T3, T2, NERR, T0, T1 Current in SLO, NSLO, VACO Current in MA, NMA Current in ACOM Current in ACOS, ACON ESD Susceptibility at all pins Junction Temperature Storage Temperature Range HBM 100 pF discharged through 1.5 k -40 -40 -0.3 Conditions Min. referenced to GND -6 Max. 6 V Unit G001 V() G002 V() G003 V() referenced to GND -9 14 6 V V G004 V() 6 V G005 I(VDD) G006 I() G007 I() -100 -50 -20 400 50 20 mA mA mA G008 I() G009 I() G010 I(ACOM) G011 I() G012 Vd() G013 Tj G014 Ts -120 -0.6 -100 -50 120 1 20 20 2 150 150 mA mA mA mA kV C C THERMAL DATA Operating conditions: VDD = 5 V 10 % Item No. T01 T02 Symbol Ta Rthja Parameter Conditions Min. Operating Ambient Temperature Range package QFN48 Thermal Resistance Chip to Ambient; QFN48 QFN48 surface mounted to PCB according to JEDEC 51 -40 30 Typ. Max. 110 C K/W Unit All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 7/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. 001 002 003 004 Symbol Parameter Conditions Min. VDD, VACO I(VDD) I(VDDA) Vc()hi Permissible Supply Voltage Supply Current in VDD Permissible Load Current at VDDA Clamp Voltage hi Vc()hi = V() - VDD, I() = 1 mA (all pins with the exception of MA, NMA) Clamp Voltage hi MA, NMA Clamp Voltage lo (all pins with the exception of VDDA, MA, NMA) Clamp Voltage lo at VDDA Clamp Voltage lo at MA, NMA Vc()hi = V() - VDD, I() = 10 mA I() = -1 mA Tj = 27 C, no load -20 0.4 4.5 45 Typ. Max. 5.5 60 0 1.5 V mA mA V Unit Total Device 005 006 Vc()hi Vc()lo 12.5 -1.5 16 -0.3 V V 007 008 Vc()lo Vc()lo I() = -1 mA I() = -10 mA -1.5 -17 0.75 -0.1 -100 16.4 -10 10 0.125 1.1 1.6 2.2 3.2 1.35 2.25 1.6 2.3 3.2 4.6 0.15 1.5 2.5 20 -0.2 -10 VDDA - 1.5 VDDA + 0.1 100 23.6 -300 300 1 2.1 3.0 4.2 6.0 1.65 2.75 150 V V V V nA k A A Signal Conditioning and Inputs: PSINx, NSINx, PCINx, NCINx (x = M, S, N) 101 Vin()sig Permissible V-Mode Input Voltage UIN = 1, TUIN = 0 UIN = 1, TUIN = 1, DCPOS = 1 102 103 104 Iin() Rin() Iin()sig V-Mode Input Current V-Mode Input Resistance UIN = 1, TUIN = 0 vs. VREFin, Tj = 27 C, UIN = 1, TUIN = 1 Permissible I-Mode Input Current UIN = 0; DCPOS = 0 DCPOS = 1 Permissible Signal Contrast Ratio ratio of Iin()pk vs. Iin()dc I-Mode Input Resistance Tj = 27 C, vs. VREFin; UIN = 0, RIN = 00 UIN = 0, RIN = 01 UIN = 0, RIN = 10 UIN = 0, RIN = 11 DCPOS = 1 DCPOS = 0 referred to side of input 105 106 SCR() Rin() k k k k %/K V V V 107 108 109 110 TCRin VREFin Vin()os Vin()diff Temperature Coefficient Rin Input Reference Voltage Input Offset Voltage Recommended Differential Input Vin()diff = V(PSINx) - V(NSINx), Vin()diff = V(PCINx) - V(NCINx); Voltage TUIN = 0 TUIN = 1 Recommended Internal Signal Level Selectable Gain Factors Differential Gain Accuracy (Master) Differential Gain Accuracy (Segment, Nonius) G * Vin()diff TUIN = 0 TUIN = 1 referenced to fine gain range referenced to fine gain range referenced to fine gain range, guaranteed monotony referenced to fine gain range, guaranteed monotony referenced to fine gain range, guaranteed monotony referenced to fine gain range, guaranteed monotony referenced to coarse gain range 20 80 6 6 1.5 -1 -2 -20 -1 -20 -1 -8 1000 4000 mVpp mVpp Vpp 111 112 113 114 115 116 117 118 119 Vcore() GF, GC GFdiff GFdiff 300 75 1 2 20 1 20 1 8 LSB LSB LSB LSB LSB LSB % GFSabs Absolute Gain Accuracy Sine (Master) GFCabs Absolute Gain Accuracy Cosine (Master) GFSabs Absolute Gain Accuracy Sine (Segment, Nonius) GFCabs Absolute Gain Accuracy Cosine (Segment, Nonius) GCabs Gain Accuracy iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 8/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. 120 Symbol VOScal Parameter Offset Calibration Range Conditions Min. measured at output, source V(ACOx) = 3 V, REFVOS = 00; ORS_x/ORC_x = 00 ORS_x/ORC_x = 01 ORS_x/ORC_x = 10 ORS_x/ORC_x = 11 measured at output, source V05, REFVOS = 01; ORS_x/ORC_x = 00 ORS_x/ORC_x = 01 ORS_x/ORC_x = 10 ORS_x/ORC_x = 11 measured at output, source V025, REFVOS = 10; ORS_x/ORC_x = 00 ORS_x/ORC_x = 01 ORS_x/ORC_x = 10 ORS_x/ORC_x = 11 measured at output, source VDC = 125 mV, REFVOS = 11; ORS_x/ORC_x = 00 ORS_x/ORC_x = 01 ORS_x/ORC_x = 10 ORS_x/ORC_x = 11 -0.5 -2 -100 -100 sine vs. cosine signal -0.25 -2 10.4 0.25 2 Typ. Max. Unit 450 900 2700 5400 mV mV mV mV 121 VOScal2 Offset Calibration Range 1500 3000 9000 18000 mV mV mV mV 122 VOScal3 Offset Calibration Range 750 1500 4500 9000 mV mV mV mV 123 VOScal4 Offset Calibration Range 375 750 2250 4500 0.5 2 100 100 mV mV mV mV LSB LSB LSB LSB LSB LSB 124 125 126 127 128 129 130 VOSdiff VOSdiff VOSint VOSint PHIcal PHIdiff PHIdiff Differential Linearity Error of Offset Correction Master Differential Linearity Error of Offset Correction Segment, Nonius Integral Linearity Error of Offset Correction Master Integral Linearity Error of Offset Correction Segment, Nonius Phase Correction Range Differential Linearity Error of Phase Correction Master Differential Linearity Error of Phase Correction Segment, Nonius Integral Linearity Error of Phase Correction Master Integral Linearity Error of Phase Correction Segment, Nonius Permissible Input Frequency Input Amplifier Cut-off Frequency (-3 dB) angle accuracy better 8 bit 131 132 133 134 PHIint PHIint fin()max fhc() -20 -20 200 250 20 20 LSB LSB kHz kHz iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 9/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. Symbol Parameter Conditions Min. Vs()hi = V(VACO) - V(); ACOR_M(6:5) = 00, I() = -5 mA ACOR_M(6:5) = 01, I() = -10 mA ACOR_M(6:5) = 10, I() = -25 mA ACOR_M(6:5) = 11, I() = -50 mA V() = 0...V(VACO) - 1 V; ACOR_M(6:5) = 00 ACOR_M(6:5) = 01 ACOR_M(6:5) = 10 ACOR_M(6:5) = 11 -9.5 -19 -46 -85 -7 -14.5 -36 -73 Typ. Max. Unit Signal Level Controller: ACOM 401 Vs()hi Saturation Voltage hi 1 1 1 1 -5 -10 -25 -50 50 V V V V mA mA mA mA A ms 402 Isc()hi Short-circuit Current hi 403 404 405 Ilk() Tctrl Residual Current With Reversed Supply Control Time Constant quadratic or sum regulation quadratic regulation: ACOT_M(8:7) = 00, Op.mode ANA_M 2.7 1.6 3 Vscq()avg Controlled Average S/C Signal Amplitude: SQRT of [V(PSOUT)V(NSOUT)]2 + [V(PCOUT)V(NCOUT)]2 Vt()min Vt()max It()min It()max Signal Monitoring AM_Min Signal Monitoring AM_Max Control Monitoring ACM_Min Control Monitoring ACM_Max 3.3 V 406 407 408 409 referred to Vscq() referred to Vscq() referenced to range ACOR_M() referenced to range ACOR_M() Vs()hi = V(VACO) - V(); ACOR_x(5) = 0, I() = -5 mA ACOR_x(5) = 1, I() = -10 mA V() = 0...V(VACO) - 1 V; ACOR_x(5) = 0 ACOR_x(5) = 1 -9.5 -19 40 135 3 90 % % %Isc %Isc Signal Level Controller: ACOS, ACON 501 Vs()hi Saturation Voltage hi 1 1 -7 -14.5 -5 -10 50 V V mA mA A ms 502 Isc()hi Short-circuit Current hi 503 504 505 Ilk() Tctrl Residual Current with Reverse Polarity Control Time Constant control to sine square or sum quadratic regulation: ACOT_x(7:6) = 00, operating mode ANA_x 2.7 1.6 3 Vscq()avg Controlled Average S/C Signal Amplitude: SQRT of [V(PSOUT)V(NSOUT)]2 + [V(PCOUT)V(NCOUT)]2 Vt()min Vt()max It()min It()max Signal Monitoring AN_Min, AS_Min Signal Monitoring AN_Max, AS_Max Control Monitoring ACN_Min, ACS_Min Control Monitoring ACN_Max, ACS_Max 3.3 V 506 507 508 509 510 referred to Vscq() referred to Vscq() referenced to range ACOR_x() referenced to range ACOR_x() 0.75 40 135 3 90 VDDA -2 % % %Isc %Isc V Vin(ACOS) Permissible Ref. Input Voltage at CVREF = 11 ACOS iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 10/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. Symbol Parameter Conditions Min. Typ. Max. Unit Sample-&-Hold Stage, Signal Filter and Sine-To-Digital Conversion 601 fc1() Cut-off Frequency of M/S/N ENF(1) = 1; fin (master channel) < 20 Hz Channel Signal Filter fin (master channel) > 1300 Hz (-3 dB lowpass filter) 602 603 604 605 amax AAabs AAR tcnv Permissible Angle Acceleration for 3(2) track nonius calculation Absolute Angular Accuracy Repeatability Conversion Time (1 Channel) Used bit length UBL_x: 0x0D: 13 bit 0x0C: 12 bit 0x0B: 11 bit 0x0A: 10 bit 0x09: 9 bit 0x08: 8 bit 0x07: 7 bit 0x06: 6 bit 0x05: 5 bit 0x04: 4 bit termination of calculation and synchronization (Nonius or MT modes) to follow-up S&H trigger RLdiff = 100 , VDD = 4.5 V, DC level = VDD/2 ENF(0) = 1; fin (master channel) < 20 Hz fin (master channel) > 1300 Hz CL = 500 pF, Vpp = 0.5 V, ENF0 = 1 500 -8 V() = GND V() = VDD RLdiff = 100 , CL = 25 pF -50 VTs > VTth Op.Mode ANA_M, ANA_N, ANA_S Op.Mode ANA_M, ANA_N, ANA_S; CL = 200 pF IBP calibrated to 200 A referenced to GNDA referenced to GNDA referenced to GNDA 92.5 48 460 -40 15 ENF(1) = 1 Used bit length UBL_x = 0x0D: 13 bit 4 300 1000 2 1 4.25 3.88 3.5 3.13 2.75 2.5 2.25 2.0 1.75 1.5 1.25 kHz kHz Mrad/s2 LSB LSB s s s s s s s s s s s 606 trec() Recovery Time Sampling-toSampling Output Amplitude Cut-off Frequency of Line Driver Signal Filter (-3 dB lowpass filter) Cut-off Frequency of Line Driver (-3 dB) Offset Voltage Short-circuit Current hi Short-circuit Current lo Slew Rate Residual Current with Reverse Polarity Output Signal with Temperature Error Output Impedance Permissible Output Frequency During Calibration Bias Current Source Reference Voltage VPAH Reference Voltage V05 Reference Voltage V025 Analog Line Driver Outputs: PSOUT, NSOUT, PCOUT, NCOUT 701 702 Vout() fc2() 300 8 600 mV kHz kHz kHz 8 -20 20 5 50 50 5 2 -15 40 mV mA mA V/s A %VDD k kHz 703 704 705 706 707 708 709 710 711 fc3() Voffs() Isc()hi Isc()lo SR() Ilk() Vout()err Rout() fout()cal Bias Current Source and Reference Voltages 801 802 803 804 IBP VPAH V05 V025 100 50 512 50 107.5 52 570 % %VDD mV %V05 iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 11/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. 901 902 903 904 Symbol Parameter Conditions Min. VDDon VDDoff VDDhys Turn-on Threshold VDD (power on release) Turn-off Threshold VDD (power down reset) Hysteresis increasing voltage VDD decreasing voltage VDD VDDhys = VDDon - VDDoff includes tbusy()cfg; MODE_MT = 00 MODE_MT = 00 3.6 3.1 400 21 29 8 115 5 10 105 1 610 635 3.8 640 665 -1.95 7 670 695 20 Typ. 3.9 3.4 Max. 4.3 3.8 V V mV ms ms MHz mV mV mV mV mV/K Unit Power-Down-Reset tready()cfg Operation Start-Up Time Clock Oscillator A01 B01 B02 B03 B04 fosc Vs() Rs() Vs() Rs() Clock Frequency Switch Drop-Off Voltage vs. VDD V() = V(VDD) - V(VDDA), I(VDDA) = 0 (unloaded) VDDA Switch On-Resistance Switch Drop-Off Voltage vs. GNDA (unloaded) GNDA Switch On-Resistance VDD vs. VDDA, load current to 20 mA V() = V(GNDA) - V(GND), I(GNDA) = 0 ground current to 20 mA VTSw() = VDDA - V(T1), Tj = 27 C, operating mode TWIB VTSe() = VDDA - V(T1), Tj = 27 C, operating mode TEIB Supply Switch and Reverse Polarity Protection: VDDA, GNDA Temperature Monitoring C01 VTSw Sensor Voltage for Warning Temperature C02 VTSe Sensor Voltage for Shutdown Temperature C03 TCs C04 VTth Sensor Voltage Temperature Coefficient Activation Threshold Temperature VTth() = VDDA - V(T0), Tj = 27 C; CFGTA(4:0) = 0x00 Warning CFGTA(4:0) = 0x0F CFGTA(4:0) = 0x1F Activation Threshold Temperature Coefficient Warning Temperature Hysteresis Relative Shutdown Temperature Shutdown Temperature Hysteresis Saturation Voltage lo Short-circuit Current lo Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-up Current Input Pull-up Voltage Clock Frequency Duration Of Startup Configuration error free EEPROM access Vt(hys) = Vt()hi - Vt()lo V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -5 A I() = 4 mA T = Te - Tw 225 400 585 285 498 725 1.32 355 615 895 mV mV mV /K C05 TCth C06 Thysw C07 T C08 Thyse 4 5 9 15 15 30 19 20 39 C C C EEPROM Interface: SCL, SDA D01 Vs()lo D02 Isc()lo D03 Vt()hi D04 Vt(lo) D05 Vt()hys D06 Ipu() D07 Vpu() D08 fclk(SCL) D09 tbusy()cfg 450 4 800 150 -750 45 250 -300 62.5 13 -60 400 80 15 60 2 mV mA V mV mV A mV kHz ms iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 12/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. Symbol Parameter Conditions Min. Typ. Max. Unit I/O Interface: RS442 Line Driver Outputs SLO, NSLO E01 Vs()hi Saturation Voltage hi Vs() = VDD - V(); DSC(1:0) = 00, I() = -1.2 mA DSC(1:0) = 01, I() = -4 mA DSC(1:0) = 10, I() = -20 mA DSC(1:0) = 11, I() = -50 mA E02 Vs()lo Saturation Voltage lo DSC(1:0) = 00, I() = 1.2 mA DSC(1:0) = 01, I() = 4 mA DSC(1:0) = 10, I() = 20 mA DSC(1:0) = 11, I() = 50 mA E03 Isc()hi Short-circuit Current hi V() = 0 V; DSC(1:0) = 00 DSC(1:0) = 01 DSC(1:0) = 10 DSC(1:0) = 11 E04 Isc()lo Short-circuit Current lo V() = VDD DSC(1:0) = 00 DSC(1:0) = 01 DSC(1:0) = 10 DSC(1:0) = 11 E05 E06 Ilk()tri tr() Tristate Leakage Current Rise Time hi DTRI(1:0) = 11 RL = 100 to GND, DSC(1:0) = 11; DSR(1:0) = 00 DSR(1:0) = 01 DSR(1:0) = 10 DSR(1:0) = 11 RL = 100 to VDD, DSC(1:0) = 11; DSR(1:0) = 00 DSR(1:0) = 01 DSR(1:0) = 10 DSR(1:0) = 11 200 200 400 900 200 200 400 900 -3 -10 -45 -120 1.2 4 20 50 -10 10 22 60 250 5 22 60 250 -100 -1.2 -4 -20 -50 3 10 45 120 10 30 40 140 350 15 40 140 350 100 mV mV mV mV mV mV mV mV mA mA mA mA mA mA mA mA A ns ns ns ns ns ns ns ns A E07 tf() Fall Time lo E08 Ilk() Residual Current with Reverse Polarity Permissible Input Voltage Input Resistance Differential Input Hysteresis MA vs. GND, NMA vs. GND Vhys() = ( V(MA) - V(NMA) ) / 2 I/O Interface: RS442 Line Receiver MA, NMA F01 F02 F03 F04 F05 F06 F07 F08 F09 Vin() Rin() Vhys() Vt()hi Vt()lo fclk() fclk() tp(MASLO) tbusy_s -7 15 50 800 4 10 10 50 20 12 25 200 2 V k mV V mV MHz MHz ns Input Threshold Voltage hi at MA pin NMA open Input Threshold Voltage lo at MA pin NMA open Permissible Clock Frequency: SSI protocol Permissible Clock Frequency: BiSS protocol Propagation Delay: MA edge vs. SLO output Processing Time Singlecycle Data (delay of start bit) MODE_ST = 0x05 to 0x0B, 0x0D to 0x0F NBISS = 0 RL(SLO/NSLO) = 120 Nonius modes: MODE_ST = 0x00 to 0x02 MODE_ST = 0x03 to 0x04, 2 track MODE_ST = 0x03 to 0x04, 3 track MODE_ST = 0x05 to 0x0B MT modes: MODE_ST = 0x0C, 3 track MODE_ST = 0x0D to 0x0F with read access to EEPROM powering up without EEPROM tcnv *1 tcnv *2 tcnv *3 0 tcnv *3 0 2 2 s s s s s s ms ms F10 F11 tbusy_r tidle Processing Time Register Access (delay of start bit) Interface Blocking Time iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 13/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. Symbol Parameter Conditions Min. Saturation Voltage hi Saturation Voltage lo Short-circuit Current hi Short-circuit Current lo Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input-Pull-Down-Current at T2 Input-Pull-Down-Voltage at T2 Input Pull-up Current at T3 Input Pull-up Voltage at T3 Saturation Voltage hi Saturation Voltage lo Short-circuit Current hi Short-circuit Current lo Analog Buffer Offset Voltage at T0 Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-down Current Input Pull-Down Voltage Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-down Current Saturation Voltage hi Saturation Voltage lo Input Pull-down Voltage V() = 1 V ... VDD Vs()hi = VDD - V(); I() = 1.6 mA during test function, I() = 1.6 mA during test function, I() = 5 A 0.8 150 20.5 250 120 296 295 275 600 V() = 1 V...VDD I() = 5 A 0.8 150 4 250 30 75 650 2 Vos() = V(T1) - V(T0), operating mode TBOS V() = 1 V...VDD I() = 5 A V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -5 A Vs()hi = VDD - V(), I() = -4 mA I() = 4 mA -60 15 -25 -65 30 800 150 4 250 30 75 650 -5 650 500 600 -15 60 25 Vs()hi = VDD - V(), I() = -4 mA I() = 4 mA -85 20 Typ. Max. 450 450 -30 65 2 mV mV mA mA V mV mV A mV A mV mV mV mA mA mV Unit I/O Interface: Clock Line Output MAO G01 Vs()hi G02 Vs()lo G03 Isc()hi G04 Isc()lo H01 Vt()hi H02 Vt()lo H03 Vt()hys H04 Ipd() H05 Vpd() H06 Ipu() H07 Vpu() I01 I02 I03 I04 I05 Vs()hi Vs()lo Isc()hi Isc()lo Voffs() Test Signal Inputs: T2, T3 Test Signal Outputs: T0, T1 I/O Interface: Input SLI J01 J02 J03 J04 J05 K01 K02 K03 K04 K05 K06 K07 Vt()hi Vt()lo Vt()hys Ipd() Vpd() Vt()hi Vt()lo Vt()hys Ipd() Vs()hi Vs()lo Vpd() 2 V V mV A mV V V mV A mV mV mV Digital Inputs: DIR, PRES iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 14/59 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = VACO = 5 V 10 %, Tj = -40...125 C, IBP calibrated to 200 A, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. L01 L02 L03 L04 L05 L06 L07 L08 Symbol Parameter Conditions Min. Vs()lo Isc()lo Vt()hi Vt()lo Vt()hys Ipu() Vpu() Ilk() Saturation Voltage lo Short-circuit Current lo Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-up Current Input Pull-up Voltage Residual Current with Reverse Polarity Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-down Current MTSLI Input Pull-down Voltage MTSLI Input Pull-up Current MTMA Input Pull-up Voltage MTMA Saturation Voltage hi at MTMA Saturation Voltage lo at MTMA Short-circuit Current hi at MTMA Short-circuit Current lo at MTMA SSI Clock Frequency at MTMA BiSS Clock Frequency at MTMA MODE_MT = 01 Max. BiSS Read Cycle Duration MT Data Update Interval MODE_MT = 01 MODE_MT = 01 or 10, CHK_MT = 1 8 MODE_MT = 11 MODE_MT = 11 MODE_MT = 11 V() = 1 V ... VDD I() = 5 A V() = 0 V ... VDD - 1 V Vpu() = VDD - V(), I() = -5 A Vs()hi = VDD - V(), I() = 4 mA I() = 4 mA -85 20 0.125 1 256 -296 -120 0.8 150 4 250 30 75 650 -20.5 600 450 450 -30 65 Vt(hys) = Vt()hi - Vt()lo V() = 0... VDD - 1 V Vpu() = VDD - V(), I() = -5 A -100 0.8 150 -750 250 -300 -60 400 100 I() = 4 mA 4 Typ. Max. 450 60 2 mV mA V V mV A mV A Unit Error Message Input/Output: NERR Multiturn Interface: MTMA, MTSLI M01 Vt()hi M02 Vt()lo M03 Vt()hys M04 Ipd() M05 Vpd() M06 Ipu() M07 Vpu() M08 Vs()hi M09 Vs()lo M10 Isc()hi M11 Isc()lo M12 fclk() M13 fclk() M14 tcycle M15 tcycle 2 V V mV A mV A mV mV mV mA mA MHz MHz s ms iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 15/59 OPERATING REQUIREMENTS: I/O Interface Operating conditions: VDD = 5 V 10 %, Ta = -40...95(110) C, IBP calibrated for fosc = 8 MHz, reference point GNDA (GND for digital I/O pins), unless otherwise stated Item No. Symbol Parameter Conditions Min. Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Permissible Cycle Time: Example for 19-bit ST data from 3-track nonius calculation Permissible Clock Period Clock Signal Hi Level Duration Clock Signal Lo Level Duration Minimum Data Output Delay Maximum Data Output Delay: Example for 19-bit ST data from 3-track nonius calculation Maximum Data Output Delay: Example for 19-bit ST data from 3-track nonius calculation Maximum Data Output Delay: Example for 39-bit ST data from 3-track interpolation without synchronization Permissible Cycle Time: Example for 19-bit ST data from 3-track nonius calculation MODE_ST = 0x05...0x0B, 0x0D...0x0F, MA lohi until SLO lohi MODE_ST = 0x00...0x02, fclk(MA) = 10 MHz, UBL_x and SBL_x see I004 MODE_ST = 0x03...0x04, fclk(MA) = 10 MHz, UBL_x and SBL_x see I004 MODE_ST = 0x0C, fclk(MA) = 10 MHz, UBL_M 13 bit, UBL_N 13 bit, UBL_S 13 bit MODE_ST = 0x05...0x07, UBL_M = 13 bit, UBL_N + SBL_N = 7 bit, UBL_S + SBL_S = 7 bit tout selected in accordance to Table 58 tout selected in accordance to Table 50 250 25 25 11.25 Max. 2x tout tout tout ns ns ns s Unit SSI Protocol I001 TMAS I002 tMASh I003 tMASl I004 tcycle BiSS C Protocol (NBISS = 0x0) I005 TMAS I006 tMASh I007 tMASl I008 tbusy I009 tbusy 100 25 25 2x TMAS 5.3 tout ns ns ns s s I010 tbusy 10 s I011 tbusy 14 s I012 tcycle MODE_ST = 0x05...0x07, UBL_x and SBL_x see I004 11.25 s Figure 1: I/O Interface timing with SSI protocol Figure 2: I/O Interface timing with BiSS C protocol iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 16/59 CONFIGURATION PARAMETERS Analog Parameters (valid for all channels) CFGIBP: Bias Trimming (P. 28) CFGTA: Temperature Sensor Calib. (P. 28) DCPOS: Input Current Polarity (P. 23) ENF: Noise Filter Enable (P. 28) CVREF: VREF Source Selection (P. 23) REFVOS: Offset Reference Source (P. 24) RIN: Input Resistance (P. 23) TUIN: Input Voltage Divider (P. 23) UIN: Signal Mode (P. 23) Signal Conditioning x = M, S, N (for master, segment, nonius channel) ACOC_x: Signal Level Control: Current (P. 27) ACOR_x: Signal Level Control: Range (P. 27) ACOT_x: Signal Level Control: Op. Mode (P. 27) GFC_x: Gain Factor Cosine (P. 24) GR_x: Gain Range (P. 24) GFS_x: Gain Factor Sine (P. 24) MPS_x: Intermediate Voltage Sine (P. 25) MPC_x: Intermediate Voltage Cosine (P. 25) OFC_x: Offset Factor Cosine (P. 26) ORC_x: Offset Range Cosine (P. 25) OFS_x: Offset Factor Sine (P. 25) ORS_x: Offset Range Sine (P. 25) PH_x: S/C Phase Correction (P. 26) Operating Modes TRACMODE: Op. Mode Parameter (P. 21) CALMODE: Op. Mode Parameter (P. 21) BYP: Bypass Switch (P. 21) Sine-To-Digital Conversion MODE_ST: S/D Conversion Mode (P. 30) UBL_M: Bit Length Master (P. 29) UBL_N: Used Bit Length Nonius (P. 29) SBL_N: Synch. Bit Length Nonius (P. 29) UBL_S: Used Bit Length Segment (P. 29) SBL_S: Synch. Bit Length Segment (P. 29) FRQ_TH: Signal Frequency Monitoring (P. 32) SPO_N: Offset Nonius Track (P. 35) SPO_S: Offset Segment Track (P. 35) I/O Interface TOS: DL_ST: M2S: ESSI: GRAY_SCD: RSSI: DIR: Timeout (P. 36) ST Data Length (P. 36) MT Data Output (P. 39) Error Bit (P. 37) Data Format (P. 37) Ring Operation (P. 37) Inversion Of Code Direction (P. 37) I/O Interface With Extended Functions NBISS: Interface Protocol (P. 38) TOS: Timeout (S. 38) DL_ST: ST Data Length (P. 39) M2S: MT Data Output (P. 39) DIR: Inversion Of Code Direction (P. 39) GRAY_SCD: Data Format (P. 39) CID_SCD: CRC Start Value (P. 39) NC_BISS: Communication Disable (S. 39) ELC: Lifecounter (P. 40) Driver Settings DSC: Driver Short-Circuit Current (P. 41) DTRI: Driver Output Mode (P. 41) DSR: Driver Slew Rate (P. 41) Command And Status Register STATUS: Status Register (P. 43) MN_CMD: Implemented Commands (P. 42) AUTORES: Automatic Reset Function (S. 42) Error And Warning Bit CFGEW: Error And Warning Bit Config. (P. 44) S2ERR: Visibility For Warning Bit (P. 45) S2WRN: Visibility For Error Bit (P. 45) E2EPR: Diagnosis Memory Enable (P. 43) MT Interface MODE_MT: DL_MT: SBL_MT: LNT_MT: CHK_MT: GRAY_MT: MT Interface Operating Mode (P. 46) MT Data Length (P. 46) MT Synch. Bit Length (P. 47) Leading/Trailing Gear Box Assembly (P. 47) Period Counter Verification (P. 47) MT Interface Data Format (P. 47) MT Interface with Extended Functions MODE_MT: MT Interface Operating Mode (P. 46) GET_MT: Direct BiSS Communication Enable for MT Sensor via I/O Interface (P. 49) NCRC_MT: MT Interface CRC Verification (P. 49) SWC_MT: MT Interface CRC Polynomial (P. 49) Preset Function OFFS_ST: Position Offset for ST Data Output (P. 50) PRES_ST: Preset Value for ST Data Output (P. 50) OFFS_MT: Position Offset for MT Data Output (P. 50) PRES_MT: Preset Value for MT Data Output (P. 50) EEPROM Interface CFG_E2P: Config. Of External Memory (P. 52) CRC_E2P: EEPROM Data Check Sum (P. 52) PROT_E2P: Register Access Control (P. 53) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 17/59 REGISTER MAP (EEPROM) OVERVIEW Adr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 ORS_M(0) Bit 7 Bit 6 Bit 5 GFC_M Bit 4 Bit 3 Bit 2 Bit 1 GR_M Bit 0 Signal Conditioning Master Channel GFS_M(7:0) MPS_M(4:0) MPC_M(2:0) MPC_M(9:3) OFS_M(6:0) ORC_M OFS_M(10)* OFC_M(9:2) PH_M(6:0) PH_M(9)* ORS_M(1) GFS_M(10:8) MPS_M(9:5) OFC_M(1:0) OFS_M(9:7) OFC_M(10)* PH_M(8:7) RIN UIN BYP 1 ACOT_M(1) Signal Conditioning Master Channel and Analog Parameters 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F ACOT_M(0) 1 DCPOS REFVOS CVREF TUIN 0 ACOR_M(1:0) CFGTA(2:0) ENF(1:0) ACOC_M(4:0) CFGIBP(3:0) CFGTA(4:3) *) MSB and signum respectively. Table 5: Register layout iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 18/59 OVERVIEW Adr 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F ACOT_S(0) ACOR_S ORS_S(0) Bit 7 Bit 6 Bit 5 GFC_S Bit 4 Bit 3 Bit 2 Bit 1 GR_S Bit 0 Signal Conditioning Segment Channel GFS_S(7:0) MPS_S(4:0) MPC_S(2:0) MPC_S(9:3) OFS_S(6:0) ORC_S OFS_S(10)* OFC_S(9:2) PH_S(6:0) PH_S(9)* GFS_S(10:8) MPS_S(9:5) ORS_S(1) OFC_S(1:0) OFS_S(9:7) OFC_S(10)* PH_S(8:7) ACOC_S(4:0) ACOT_S(1) Signal Conditioning Nonius Channel 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F ACOT_N(0) ACOR_N OSR_N(0) GFC_N GFS_N(7:0) MPS_N(4:0) MPC_N(2:0) MPC_N(9:3) OFS_N(6:0) ORC_N OFS_N(10)* OFC_N(9:2) PH_N(6:0) PH_N(9)* GR_N GFS_N(10:8) MPS_N(9:5) OSR_N(1) OFC_N(1:0) OFS_N(9:7) OFC_N(10)* PH_N(8:7) ACOC_N(4:0) ACOT_N(1) *) MSB and signum respectively. Table 6: Register layout iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 19/59 OVERVIEW Adr 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 ... 0x74 0 0 E2EPR 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Digital Parameters SPO_N(2:0) UBL_S(1:0) UBL_N(2:0) MODE_ST(3:0) DL_MT(2:0) GRAY_SCD ELC CHK_MT SWC_MT ESSI DIR GET_MT FRQ_TH(1:0) 0 0 NC_BISS 0 OFFS_ST(7:0) OFFS_ST(15:8) OFFS_ST(23:16) OFFS_ST(31:24) OFFS_ST(38:32) OFFS_MT(7:0) OFFS_MT(15:8) OFFS_MT(23:16) SPO_S(7:0) SPO_S(12:8) SPO_N(10:3) UBL_M(3:0) SPO_N(12:11) SBL_S(2:0) UBL_S(3:2) SBL_N(2:0) UBL_N(3) DL_ST(4:0) RSSI NBISS M2S(1:0) DL_MT(3) MODE_MT(1:0) CFG_E2P(2:0) NCRC_MT GRAY_MT LNT_MT SBL_MT(1:0) CFGEW(7:0) 0 S2ERR S2WRN PROT_E2P(1:0) AUTORES(1:0) TRACMODE(1:0) DSR(1:0) DTRI(1:0) CALMODE(2:0) DSC(1:0) CID_SCD(3:0) 0 0 0 0 0 TOS(1:0) 1 CRC_E2P(9:2) CRC_E2P(1:0) PRES_ST(7:0) PRES_ST(15:8) PRES_ST(23:16) PRES_ST(31:24) PRES_ST(38:32) PRES_MT(7:0) PRES_MT(15:8) PRES_MT(23:16) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 20/59 OVERVIEW Adr 0x75 0x76 0x77 Bit 7 TH_WRN ACS_MAX CMD_EXE Bit 6 EPR_ERR AM_MIN AN_MIN Bit 5 FRQ_WDR AM_MAX AN_MAX Bit 4 FRQ_STUP ACM_MIN ACN_MIN Bit 3 NON_CTR ACM_MAX ACN_MAX Bit 2 MT_CTR CT_ERR AS_MIN Bit 1 MT_ERR RF_ERR AS_MAX Bit 0 MT_WRN TH_ERR ACS_MIN STATUS Register (with read access) COMMAND Register: MN_CMD (with write access) 0x77 0 0 0 0 0 MN_CMD(2:0) Device Identification (preset values after start-up without EEPROM) 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Hints 0 0 0 0x4D M 0x4E N Internal identifier (0x04 Y2) BANK_ACT* GRAY_SCD M2S(1:0) DL_MT(3) equivalent to address 0x4C equivalent to address 0x3E 0x69 i 0x43 C All registers can be written and read as long as no protection level has been set (see PROT_E2P). Addresses with gray face box are located in the external EEPROM *) Bank selection is active. BANK_ACT = 1, if CFG_E2P /= 000 Table 7: Register layout iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 21/59 OPERATING MODES and CALIBRATION PROCEDURES iC-MN supports a number of different calibration strategies, providing both digital and analog test signals to this end. The following tables give the various modes of operation. For the adjustment of the signal conditioning unit analog test signals are output in analog calibration modes ANA_x, with digital signals activated by digital calibration modes DIG_x, enabling the signal conditioning to be set across measurements of various duty cycles. The order of the procedure for both modes of calibration is described in the following chapter. Alternatively, with an active signal level controller iCMN can be calibrated in controller modes AAC_x, where the residual signal ripple is minimized. For this purpose the signal gain, offset and phase correction parameters must be set in such a way that the controller signal CGUCKx available at pin T0 are devoid of AC contents. In calibration modes TWIB and TEIB the temperature monitoring and bias reference source IBP can be adjusted. Here the temperature threshold is set to the required value for either warning or shutdown; the other value is determined by the fixed difference of the switching thresholds. As the VTTx measurement voltages and CGUCKx signals are only available via a buffer stage the buffer offset voltage must be taken into account if the temperature thresholds are to be adjusted with any accuracy. To this end the buffer offset voltage can be measured in calibration mode TBOS. A voltage is then applied to pin T1, with the buffer offset voltage being the difference between this and pin T0. Parameter Op. Mode TRACMODE CALMODE Normal 0 0 BYP* Output Signals Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0 Pin T1 Pin DIR Output of master track via line driver 0 0 - Table 8: Normal operating mode Parameter Output Signals Op. Mode TRACMODE CALMODE BYP* Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0 Pin T1 Pin DIR Signal calibration modes with VDCx intermediate voltages ANA_M 1 0 0 Calib. signals of master chan. SVDCM CVDCM 1 0 1 PSINM, NSINM, PCINM, NCINM SVDCM CVDCM ANA_S 2 0 0 Calib. signals of segment chan. SVDCS CVDCS 2 0 1 PSINS, NSINS, PCINS, NCINS SVDCS CVDCS ANA_N 3 0 0 Calib. signals of nonius chan. SVDCN CVDCN 3 0 1 PSINN, NSINN, PCINN, NCINN SVDCN CVDCN Signal calibration modes with AC noise evaluation (with active sine-square level controlling) AAC_M 1 4 Calib. signals of master chan. CGUCKM AAC_S 2 4 Calib. signals of segment chan. CGUCKS AAC_N 3 4 Calib. signals of nonius chan. CGUCKN Bias calibration, temperature-sensor calibration, and buffer offset measurement TWIB 0 5 Output of master track via line driver VTSw VTth IBP TEIB 0 6 Output of master track via line driver VTSe VTtherr IBP TBOS 0 7 Output of master track via line driver BUFFOUT BUFFIN Notes S/D conversion modes with a cyclic conversion, such as 0x08, 0x09, 0x0A, are not permitted during signal calibration. Cyclic BiSS data requests must also be avoided due to its trigger for sample-and-hold. Analog calibration signals are output via 5 k source impedance. The maximum permissible signal frequency is 2 kHz for a load of 200 pF (see Elec. Char. 709, 710) * Bypass function: inputs (without voltage divider) to outputs, ca. 7 k source impedance Table 9: Operating modes for analog signal calibration iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 22/59 Calibration Using Comparated Sine/Cosine Signals Parameter Output Signals Op. Mode TRACMODE CALMODE BYP* Pins PSOUT, NSOUT, PCOUT, NCOUT Pin T0 Signal calibration modes with comparated sine/cosine signals DIGO_M 1 1 Calib. signals of master chan. DIGOFFCOS DIGA_M 1 2 Calib. signals of master chan. 0 DIGP_M 1 3 Calib. signals of master chan. 0 DIGO_S 2 1 Calib. signals of segment chan. DIGOFFCOS DIGA_S 2 2 Calib. signals of segment chan. 0 DIGP_S 2 3 Calib. signals of segment chan. 0 DIGO_N 3 1 Calib. signals of nonius chan. DIGOFFCOS DIGA_N 3 2 Calib. signals of nonius chan. 0 DIGP_N 3 3 Calib. signals of nonius chan. 0 Pin T1 DIGOFFSIN DIGAMP DIGPHASE DIGOFFSIN DIGAMP DIGPHASE DIGOFFSIN DIGAMP DIGPHASE Pin DIR - Table 10: Operating modes for digital signal calibration Calibration Of Signal Offsets Fig. 3: The duty ratio is set accurately to 50 % using parameter OFS_x. This measurement requires a high resolution, for instance of 0.06 %, for calibrating the offset to 0.2 % with reference to the signal amplitude. The resulting interpolation error of 3 LSB (referred to a resolution of 13 bits) corresponds to an angle error of 0.11 degree (360 degree means one signal period). Fig. 4: The duty ratio is set accurately to 50 % using parameter OFC_x. degree 0.2 Calibration Of Signal Amplitudes And Phase Fig. 5: To calibrate the duty cycle to exactly 50 % the fine gain parameters GFC_x und GFS_x can balance the signal amplitudes. If a signal amplitude difference of 0.67 % remains after calibration, the interpolation error enlarges to approx. 4.5 LSB at 13 bit resolution. Fig. 6: Duty cycle calibration to exactly 50 % is carried out using parameter PH_x. A remaining phase error of 0.7 degree reduces the interpolation accuracy to 10 bit (equal to 8 LSB error at 13 bit resolution, respectively). degree 0.2 0.1 0.1 0 0 -0.1 -0.1 -0.2 0 90 180 270 360 -0.2 0 90 180 270 360 Figure 3: Mode DIGO_x: DIGOFFSIN at Pin T1. Figure 5: Mode DIGA_x: DIGAMP at Pin T1. degree 0.2 degree 0.4 0.1 0.2 0 0 -0.1 -0.2 -0.2 0 90 180 270 360 -0.4 0 90 180 270 360 Figure 4: Mode DIGO_x: DIGOFFCOS at Pin T0. Figure 6: Mode DIGP_x: DIGPHASE at Pin T1. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 23/59 SIGNAL CONDITIONING for MASTER-, SEGMENT- and NONIUS-Channel (x= M,S,N) DCPOS Code 0 1 Addr. 0x0A; bit 6 Polarity Isensor VREFin() Negative Positive 2.5 V 1.5 V Table 12: Input current polarity RIN Code 0 1 2 3 Addr. 0x0A; bit 2:1 Resistance 1.6 k 2.3 k 3.2 k 4.6 k Table 13: Input resistance with I mode Figure 7: Schematic of Input Stage The input stages for sine and cosine are instrumentation amplifiers and can process current and voltage signals; selection is made for all three tracks using UIN. Signal conditioning should be performed in the order given in the following. UIN Code 0 1 Addr. 0x0A; bit 0 Function I Mode: current inputs V Mode: voltage inputs Voltage Signals If the voltage signals are too large the input signal can be quartered by an internal divider. The voltage divider is referenced to the VREFin reference source which is set by DCPOS. In order to use the input voltage range of the input amplifier to its full capacity DCPOS should be set to 1 in voltage divider mode. TUIN Code 0 1 Addr. 0x0A; bit 3 Function Not active Voltage divider active Table 14: Input voltage divider Table 11: Signal mode Additionally, using CVREF the user can select whether VREFin is the reference potential generated internally or a voltage provided externally. CVREF Code 00 01 10 11 Note Addr. 0x0B; bit 4:3 Function Generated internally Reserved Internal VREFin() output to pin ACOS* External ref. voltage supplied to pin ACOS *) No load permitted, buffer required. Figure 8: Direction of current flow Current Signals For current signals internal reference VREFin is adapted to the input current polarity using DCPOS. The input resistance is set using RIN (1:0). When selecting the input resistance the average potentials SVDC and CVDC should be between 125 mV and 250 mV to obtain a reasonable offset calibration range. Table 15: VREF Source Selection All other settings are to be carried out for each individual track separately. A small x in the register name stands for (M)aster, (S)egment and (N)onius respectively. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 24/59 Gain Adjustment The gain is set in three stages. The gain range is first determined for sine and cosine using register GR_x (2:0). Register GFC_x (4:0) can then be used to finely adjust the gain of the cosine track. In the final stage of the process the amplitude of the sine track is adapted to suit the cosine track using register GFS_x (10:0). With differential input signals the overall sine gain of one track is thus calculated as GAINS_x = GR_x * GFS_x; the total cosine gain is then GAINC_x = GR_x * GFC_x. Offset Calibration When calibrating the offset the offset reference source must first be selected using REFVOS (1:0). This setting is valid for all three tracks. If VDC is selected as the offset reference SVDCx is the reference for the sine track and CVDCx for the cosine. The VDC reference enables the offset calibration to be automatically tracked dependent on the DC level of the input signal. If ACO is chosen as the offset reference the voltage at pin ACOx, divided into 1 /20 , acts as a reference. This enables the offset to be calibrated dependent on the supply voltage of the sensor. GR_M GR_S GR_N Code 0 1 2 3 4 5 6 7 Addr. 0x00; bit 2:0 Addr. 0x10; bit 2:0 Addr. 0x20; bit 2:0 Coarse gain 6.0 12.4 16.2 20.2 26.0 31.6 39.5 48.0 Table 16: Gain range sine/cosine GFC_M GFC_S GFC_N Code k 0x00 0x01 0x02 ... 0x1F 1 1.07 1.13 ... 6.25 Addr. 0x00; bit 7:3 Addr. 0x10; bit 7:3 Addr. 0x20; bit 7:3 Fine gain GFC = 6.25 31 k Figure 9: Principle offset calibration circuit with selectable reference sources. REFVOS Code Addr. 0x0A; bit 5:4 Type of source Feedback of pin ACO Reference V05 Reference V025 Tracked source VDC REFVOS = V(ACOx)/20 REFVOS = 0.5 V REFVOS = 0.25 V REFVOS = SVDCx, CVDCx Table 17: Gain factor cosine GFS_M GFS_S GFS_N Code k 0x000 0x001 0x002 ... 0x7FF Addr. 0x02; bit 2:0 Addr. 0x01; bit 7:0 Addr. 0x12; bit 2:0 Addr. 0x11; bit 7:0 Addr. 0x22; bit 2:0 Addr. 0x21; bit 7:0 Fine gain GFS = 6.25 1984 1 1.0009 1.0018 ... 6.6245 k 0 1 2 3 Table 19: Offset reference source Source VDC is to be used as reference for current inputs. The average potentials of sine (SVDCx) and cosine (CVDCx) are determined by: Table 18: Gain factor sine SVDCx = (1 - ks ) * V (PSi) + ks * V (NSi) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 25/59 and CVDCx = (1 - kc ) * V (PCi) + kc * V (NCi) Using MPS_x (9:0) and MPC_x (9:0) ks and kc should be configured in such a way that the AC fraction is minimal with both voltages. MPS_M MPS_S MPS_N Code 0x000 0x001 ... 0x3FF Addr. 0x03; bit 4:0 Addr. 0x02; bit 7:3 Addr. 0x13; bit 4:0 Addr. 0x12; bit 7:3 Addr. 0x23; bit 4:0 Addr. 0x22; bit 7:3 SVDC = (1 - ks ) * V (PSi) + ks * V (NSi) ks = 0.3333 ks = 0.3336 ... ks = 0.6666 ORC_M ORC_S ORC_N Code 0 1 2 3 Range maxVOSC_x = 3 * REFVOS maxVOSC_x = 6 * REFVOS maxVOSC_x = 18 * REFVOS maxVOSC_x = 36 * REFVOS Addr. 0x06; bit 5:4 Addr. 0x16; bit 5:4 Addr. 0x26; bit 5:4 Table 23: Offset range cosine The achievable angle accuracy following interpolation is affected by the internal signal strength and the offset calibration step width, depending on the set correction range and reference source. By way of example these dependencies are shown in the following table, for half and full scale signal levels (FS means 6 Vpp). Range x Source maxVOSC_x maxVOSS_x Cal. Step Width (LSB) Limitation Of Angle Accuracy @ 100 % (6 Vpp) @ 50 % (3 Vpp) none (>13 bit) none (>13 bit) none (>13 bit) none (>13 bit) 0.08, ca. 0.16, ca. 0.16, ca. 0.32, ca. 12 bit 11 bit 11 bit 10 bit Table 20: Intermediate voltage sine 3 x 0.25 V MPC_M MPC_S MPC_N Code 0x000 0x001 ... 0x3FF Addr. 0x04; bit 6:0 Addr. 0x03; bit 7:5 Addr. 0x14; bit 6:0 Addr. 0x13; bit 7:5 Addr. 0x24; bit 6:0 Addr. 0x23; bit 7:5 CVDC = (1 - kc ) * V (PCi) + kc * V (NCi) kc = 0.3333 kc = 0.3336 ... kc = 0.6666 6 x 0.25 V 6 x 0.5 V 18 x 0.5 V 750 mV 1.5 V 3V 9V 732 V 1465 V 4396 V 8789 V Table 24: Offset calibration and influence on angle accuracy The sine and cosine offsets are calibrated by a linear voltage divider using OFS_x (10:0) and OFC_x (10:0). OFS_M Addr. 0x06; bit 3:0 Addr. 0x05; bit 7:1 Addr. 0x16; bit 3:0 Addr. 0x15; bit 7:1 Addr. 0x26; bit 3:0 Addr. 0x25; bit 7:1 OFS_x = OffsS_x*maxVOSS_x OffsS_x = 0 OffsS_x = -0.0009 OffsS_x = -0.0019 ... OffsS_x = -1 OffsS_x = 0 OffsS_x = 0.0009 OffsS_x = 0.0019 ... OffsS_x = 1 Table 21: Intermediate voltage cosine The calibration range for the offset of sine and cosine is dependent on the source selected by REFVOS and is set using ORS_x (1:0) and ORC_x (1:0). The offset correction accuracy is influenced with the above. ORS_M ORS_S ORS_N Code 0 1 2 3 Range maxVOSS_x = 3 * REFVOS maxVOSS_x = 6 * REFVOS maxVOSS_x = 18 * REFVOS maxVOSS_x = 36 * REFVOS Addr. 0x05; bit 0 Addr. Addr. Addr. Addr. Addr. 0x04; 0x15; 0x14; 0x25; 0x24; bit 7 bit 0 bit 7 bit 0 bit 7 OFS_S OFS_N Code 0x000 0x001 0x002 ... 0x3FF 0x400 0x401 0x402 ... 0x7FF Table 22: Offset range sine Table 25: Offset voltage sine iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 26/59 OFC_M Addr. 0x08; bit 0 Addr. 0x07; bit 7:0 Addr. 0x06; bit 7:6 Addr. Addr. Addr. Addr. Addr. Addr. 0x18; 0x17; 0x16; 0x28; 0x27; 0x26; bit 0 bit 7:0 bit 7:6 bit 0 bit 7:0 bit 7:6 OFC_S Phase Correction The phase between sine and cosine is calibrated by PH_x (9:0). With a phase error of 2.5 or more the amplitude and offset must be readjusted for a track resolution accuracy of 13 bits. PH_M PH_S PH_N Code 0x000 0x001 ... 0x1FF 0x200 0x201 ... 0x3FF Addr. Addr. Addr. Addr. Addr. Addr. Function +0 + 0.0204 ... + 10.396 -0 - 0.0204 ... - 10.396 0x09; 0x08; 0x19; 0x18; 0x29; 0x28; bit 2:0 bit 7:1 bit 2:0 bit 7:1 bit 2:0 bit 7:1 OFC_N Code 0x000 0x001 0x002 ... 0x3FF 0x400 0x401 0x402 ... 0x7FF OFC_x = OffsC_x*maxVOSC_x OffsC_x = 0 OffsC_x = -0.0009 OffsC_x = -0.0019 ... OffsC_x = -1 OffsC_x = 0 OffsC_x = 0.0009 OffsC_x = 0.0019 ... OffsC_x = 1 Table 26: Offset voltage cosine Table 27: Sine/cosine phase correction iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 27/59 ANALOG PARAMETERS Signal Level Controller By tracking the sensor's power supply via the controlled current sources (outputs ACOM, ACOS and ACON) iC-MN can keep the sine/cosine track signals for the ensuing sine-to-digital converter constant regardless of temperature and aging effects. When adjusting the signal conditioning a constant current source is used in place of the controlled current source, the set current of which can be adjusted using ACOR_M(6:0) or ACOR_x(5:0) (x = S, N). This current must be so low as to leave enough reserve for temperature and aging effects and ensure that no unnecessary power dissipation is generated. However, the source current may not be too low so as to permit a better signal contrast and improved signal to noise ratio. Using this current the signal calibration can then be performed so that the sine/cosine signals at the sineto-digital converter have a (differential) value of 6 Vpp in their calibrated state. Once calibration has proved successful the signal level controller can be activated. There are three integrated signal level control units in iC-MN, all of which are powered by VACO. It is thus possible to regulate each track individually or, in optical systems with an LED, for example, all three tracks using the master signal level controller. If the control unit's working range is exceeded, an error is generated. ACOT_M(8:7) Code 00 01 10 11 Addr. 0x0D; bit 0 Addr. 0x0C; bit 7 Operating mode Quadratic regulation active* Sum regulation active Constant current source mode Not permitted ACOC_M(4:0) Addr. 0x0C; bit 4:0 Code Setpoint 0x00 0x01 ... 0x1E 0x1F 3.125% * Imax (ACOM) 6.25% * Imax (ACOM) ... 96.875% * Imax (ACOM) 100% * Imax (ACOM) Table 30: Current source setpoint, ACOM output ACOT_S(7:6) ACOT_N(7:6) Code 00 01 10 11 Addr. 0x1D; bit 0 Addr. 0x1C; bit 7 Addr. 0x2D; bit 0 Addr. 0x2C; bit 7 Operating mode Quadratic regulation active Sum regulation active Constant current source mode Not permitted Table 31: Controller op. mode, ACOS/ACON outputs ACOR_S(5) Addr. 0x1C; bit 5 ACOR_N(5) Addr. 0x2C; bit 5 Code Current range Imax (ACOS), Imax (ACON) 0 1 5 mA 10 mA Table 32: Current source range, ACOS/ACON outputs ACOC_S(4:0) Addr. 0x1C; bit 4:0 ACOC_N(4:0) Addr. 0x2C; bit 4:0 Code Setpoint 0x00 0x01 ... 0x1E 0x1F 3.125% * Imax (ACOS, ACON) 6.25% * Imax (ACOS, ACON) ... 96.875% * Imax (ACOS, ACON) 100% * Imax (ACOS, ACON) *) pQuadratic regulation of V()scq = (V (PSOUT - V (NSOUT ))2 + (V (PCOUT - V (NCOUT ))2 Table 28: Controller op. mode, ACOM output ACOR_M(6:5) Addr. 0x0C; bit 6:5 Code Current range Imax (ACOM) 00 01 10 11 5 mA 10 mA 25 mA 50 mA Table 33: Current source setpoint, ACOS/ACON output Table 29: Current source range, ACOM output iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 28/59 Bias Current Source The calibration of the bias current source in operation mode TWIB or TEIB is prerequisite for adherence to the given electrical characteristics and also instrumental in the determination of the chip timing (e.g. SCL clock frequency). For the calibration of source IBP to its target value of 200 A the voltage across the 5 k measurement resistor has to be adjusted to 1 V. CFGIBP Code k 0x0 0x1 ... 0xF Addr. 0x0D; bit 4:1 IBP 31 31-k required warning temperature Tw , temperature coefficients TCs and TCth (see Electrical Characteristics, Section C) and measurement value VTSw (Tcurr ) are entered into this calculation: VTth(T curr ) = VTS w (T curr ) + TCs * (Tw - T curr ) TCth 1 + 1+TCth*(T -T norm ) * (Tw - Tcurr ) curr 100.00 % 103.3 % ... 193.7 % The reference temperature Tnorm is 27 C. Activation threshold voltage VTth(Tcurr ) is provided for a high impedance measurement (10 M) at output pin T0 and must be set by programming CFGTA(4:0) to the calculated value. CFGTA Code k 0x00 0x01 ... 0x1F VTth 100 % 105 % ... 255 % Addr. 0x0E; bit 1:0 Addr. 0x0D; bit 7:5 100+5k 100 Table 34: Bias current source calibration Table 35: Calibration of temperature monitoring Figure 10: Measurement circuit Temperature Sensor As regards temperature two settings can be made; either a temperature threshold for an excessive temperature warning or an excessive temperature error can be set. The excessive temperature error and warning are coupled to one another (see Characteristics C07). Calibration of the excessive temperature warning in calibration mode TWIB is described by way of example. To set the required warning temperature Tw the temperature sensor voltage VTSw (Tcurr ) at which the warning is generated is first determined. Tcurr is the actual temperature. To this end a voltage ramp from VDD towards GND is applied to pin T1 until pin NERR indicates the error message. The necessary activation threshold voltage VTth(Tcurr ) is then calculated. The Signal Noise Filters iC-MN has a noise filter for both the analog output drivers and the sine-to-digital converter. These filters can be activated by ENF. ENF(0) Code 0 1 Addr. 0x0E; bit 1 Function Disabled Sin/Cos Output driver noise filter activated Table 36: Noise filter for the output drivers ENF(1) Code 0 1 Addr. 0x0E; bit 2 Function Disabled S/D Conversion noise filter activated Table 37: Noise filter for the sine-to-digital converter iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 29/59 SINE-TO-DIGITAL CONVERSION MODES iC-MN has two principle modes of operation. In nonius modes 2 or 3 tracks are combined by a nonius calculation with synchronization; in multiturn modes the up to 3 tracks are combined to form an absolute word via gear box code synchronization. The used and synchronization bit lengths (parameters UBL_x and SBL_x) are selectable for both operating modes; in multiturn modes it is also possible to output unsynchronized data from all tracks. With both principle operating modes iC-MN offers various sine-to-digital conversion modes. With a data request via the I/O interface this determines: * The sample time and thus the "age" of the output data * The necessary processing time prior to generation of the output data word. UBL_S UBL_N Code 0x00 ... 0x0D Internal Bit Lengths The used bit length is set for the master, segment and nonius tracks using registers UBL_M, UBL_S and UBL_N. From these used bits the internal singleturn data word is then generated, for which purpose synchronization bits are used. The bit lengths used for synchronization can be set separately via register SBL_S for the segment track and register SBL_N for the nonius track. Limitations governing the settable bit lengths are summarized in Table 41. UBL_M Code 0x00 0x01..0x03 0x04 ... 0x0D Addr. 0x3B; bit 5:2 Bit length master 0 not permitted 4 ... 13 Table 38: Bit length master Addr. 0x3C; bit 1:0 Addr. 0x3B; bit 7:6 Addr. 0x3D; bit 0 Addr. 0x3C; bit 7:5 Used bit length 0 ... 13 Table 39: Used bit length for segment and nonius SBL_S SBL_N Code 0x00 ... 0x04 Addr. 0x3C; bit 4:2 Addr. 0x3D; bit 3:1 Synchronization bit length 0 ... 4 Table 40: Synchronization segment and nonius Track Master Segment Nonius Count of bits processed UBL_M UBL_S+SBL_S UBL_N+SBL_N Possible bit count 0, 4..13 0, 4..13 0, 4..13 P Table 41: Possible bit counts for UBL_M and UBL_x+SBL_x iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 30/59 S/D CONVERSION with NONIUS CALCULATION For the nonius modes iC-MN has a flash counter which counts the zero crossings of the master track. When the system is started this flash counter is preloaded with the absolute period information which has been most recently calculated using the nonius and segment tracks (or only the nonius track). The output data word always is the flash counter value synchronized with the master track. Furthermore, it is possible to output synchronized singleturn and multiturn position data which can be set using the parameter MODE_MT (see page 46). MODE_ST Addr. 0x3D; bit 7:4 Operation modes with nonius calculation (Nonius Modes) Code 0x00 0x01 0x02 0x03 0x04 Description Data outp. following S/D conversion of master track Period verification disabled Frequency-dependent period verification Period verification enabled Data output following S/D conversion of all tracks Frequency-dependent period verification Period verification enabled Zero-delay data output: result of previously triggered S/D conversion Period verification disabled Frequency-dependent period verification Period verification enabled Zero-delay data output: last result of background S/D conversion (asynchronous) Period verification disabled Frequency-dependent period verification Period verification enabled Zero-delay data output: last result of S/D conversion triggered by pin T3 0x0B Notes Period verification enabled On changing parameter MODE_ST during operation command SOFT_RES should be issued. Modes 0x08, 0x09, 0x0A are not permitted during calibration via Op.Mode's ANA_x oder DIGx_x. Output Data Verification It is possible to verify the counted period when a nonius calculation has been completed. Possible settings include: 1. No verification of counted periods 2. Frequency-dependent verification of counted periods. Exceeding the maximum master track signal frequency set by FRQ_TH (see Table 46) disables the flash counter verification versus nonius calculation. If the limit is again undershot, future conversions are again verified. 3. Period verification versus nonius calculation is always enabled and executed with each conversion. Op. Mode Descriptions Of Nonius Modes 0x05 0x06 0x07 MODE_ST Codes 0x00, 0x01, 0x02 With this mode the processing time is largely determined by the conversion time of the master track. The conversion procedure is as follows: 1. A data readout request triggers the conversion of all selected tracks 2. Following conversion of the master track: synchronization with the internal flash counter and output of the synchronized postion value 3. During data readout: conversion of the remaining tracks and nonius calculation 4. Generation of NON_CTR with the next data readout cycle MODE_ST Codes 0x03, 0x04 The processing time is largely determined by the sum of the conversion time of the tracks for conversion. The conversion procedure is as follows: 1. A data readout triggers the complete conversion of the set tracks 2. Following conversion of the master track: synchronization with the internal flash counter 3. Following conversion of the remaining tracks: nonius calculation and generation of NON_CTR 0x08 0x09 0x0A Table 42: Nonius modes iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 31/59 4. Transmission of the synchronized position value. The transmitted NON_CTR counts as part of the current conversion. MODE_ST Codes 0x05, 0x06, 0x7 The processing time is low as "old" data is transmitted, the time of sampling is, however, known (NB: The data from the first readout is invalid following a SOFT_RES). The conversion procedure is as follows: 1. With a data readout: immediate transmission of the data from the last readout cycle including the relevant NON_CTR 2. With a data readout: start of a new conversion and providing of data for the next data readout cycle. NON_CTR is output directly at the NERR pin. MODE_ST Codes 0x08, 0x09, 0xA The processing time is low and the time of sampling not precisely known. The conversion procedure is as follows: 1. Regardless of the data readout: background conversion permanent Principle PPR And Bit Length Dependencies With a nonius system with three tracks UBL_M must be set so that it is at least as large as the maximum value of MAX(UBL_S+SBL_S, UBL_N+SBL_N). If only two tracks are used, UBL_S and SBL_S must be set to zero. UBL_M must then at least match the maximal value of MAX(UBL_N+SBL_N). The necessary number of signal periods per revolution for the individual tracks is then determined by the selected used bit lengths: Track Master Segment Nonius Required signal periods 2UBL_S+UBL_N 2UBL_S+UBL_N - 2UBL_N 2UBL_S+UBL_N - 1 2. With a data readout: transmission of current data. Each NON_CTR is output directly at the NERR pin. In data transmission a NON_CTR error is only signaled when the error occurs during the relevant nonius calculation. MODE_ST Code 0x0B This mode can be used in systems in which sampling must be synchronized to a frequency determined externally and independent of the data readout cycles. The conversion procedure is as follows: 1. A conversion with nonius synchronization is triggered via pin T3. NON_CTR is output directly at the NERR pin. 2. With a data readout the most recent conversion data triggered by pin T3 is transmitted including the relevant NON_CTR. The following tables show the possible settings and required number of signal periods. The total physical angle resolution in nonius mode is obtained from the sum of UBL_M+UBL_S+UBL_N. At the same time the bit lengths set for synchronization determine a limit up to which a nonius calculation is possible. This limit is given in Table 45 as the maximum tolerable phase deviation which may occur between the segment and master track or nonius and master track (with reference to the electrical 360 period of the master signal). Physical resolution a ) UBL_S UBL_N Master Segm. Nonius min b ) max 2 2 16 12 15 2+2+4 2+2+13 3 2 32 28 31 2+3+5 2+3+13 3 3 64 56 63 3+3+5 3+3+13 4 3 128 120 127 3+4+6 3+4+13 4 4 256 240 255 4+4+6 4+4+13 5 4 512 496 511 4+5+7 4+5+13 5 5 1024 992 1023 5+5+7 5+5+13 6 5 2048 2016 2047 5+6+8 5+6+13 6 6 4096 4032 4095 6+6+8 6+6+13 a ) For configuration of the output data length, see Table 51 b ) For the minimum data length SBL_x = 0x02 is assumed Bits/Track Signal periods/Turn Table 43: Settings for 3-track nonius mode Bits/Track Signal periods/Turn Physical resolution a ) UBL_N Master Nonius min b ) max 4 16 15 4+6 4+13 5 32 31 5+7 5+13 6 64 63 6+8 6+13 a ) For configuration of the output data length, see Table 51 b ) For the minimum data length SBL_x = 0x02 is assumed Table 44: Settings for 2-track nonius mode iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 32/59 UBL_N/ UBL_S 2 SBL_N/ SBL_S 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 Permissible Max. Phase Deviation [given in degree per signal period of 360] +/- 22.5 +/- 33.75 +/- 39.38 +/- 11.25 +/- 16.88 +/- 19.69 +/- 5.63 +/- 8.44 +/- 9.84 +/- 2.81 +/- 4.22 +/- 4.92 +/- 1.41 +/- 2.11 +/- 2.46 Digital Frequency Monitoring iC-MN features an integrated frequency monitoring circuit for the master track. A signal frequency warning threshold can be configured by FRQ_TH. FRQ_TH Code 00 01 10 11 Addr. 0x43; bit 7:6 Warning Threshold 7.625 kHz 31.25 kHz 62.5 kHz 125 kHz 3 4 5 6 Table 46: Signal frequency monitoring FRQ_TH is used by the frequency-dependent period verification feature available for nonius modes (see MODE_ST = 0x01, 0x03, 0x06 and 0x09). The following applies to all modes with nonius synchronization: if the frequency of the master track is too high at power on, FRQ_STUP and FRQ_WDR remain set until the period verification was successful below the frequency warning threshold. In nonius modes without an enabled period verification it must be observed that FRQ_STUP remains permanently set and can only be reset by SOFT_RES when the warning threshold is undershot. Table 45: Tolerable phase deviation for the master versus the nonius or segment track (with reference to 360, electrical) The synchronization principle is summarized in Figure 11, where represents the digitized angle of the relevant track. Figure 11: Principle of nonius mode synchronization iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 33/59 S/D CONVERSION with MULTITURN SYNCHRONIZATION In multiturn modes the output data word always matches the current converted and synchronized track data. For 1 to 3 selected tracks parameters SBL_S and SBL_N adjust the gear box synchronization, whereas the selected used bit lengths (UBL_x) determine the reduction ratio required for the multiturn gear box: Gear reduction Synchronization Master track Singleturn 2UBL_M Segment track Master track 2UBL_S 2UBL_N Nonius track Segment track One limitation in multiturn mode is that neither an external multiturn can be configured nor counted multiturn data output. Parameters MODE_MT and M2S must be set to 0. Figure 12 shows the synchronization principle, where represents the digitized angle of the relevant track. Op. Mode Descriptions Of Multiturn Modes MODE_ST Code 0x0C The processing time is largely determined by the sum of the conversion time of the configured tracks. Procedure of conversion: 1. A data readout request triggers the complete conversion of the set tracks 2. Gear box synchronization 3. Transmission of the output data MODE_ST Code 0x0D The processing time is low as "old" data is transmitted, the time of sampling is, however, known. The conversion procedure is as follows: 1. With a data readout: immediate transmission of the data from the last readout cycle 2. With a data readout: start of a new conversion and providing of data for the next readout cycle. NB: The data from the first readout is invalid following a SOFT_RES. MODE_ST Code 0x0E The processing time is low and the time of sampling not precisely known. The conversion procedure is as follows: Figure 12: Principle of multiturn synchronisation MODE_ST Addr. 0x3D; bit 7:4 Operation modes with multiturn synchronization (MT Modes) Code 0x0C Description Data output following S/D conversion of all tracks with MT synchronization configured via SBL_x Data output: result of previously triggered S/D conversion with MT synchronization configured via SBL_x Data output: last result of background S/D conversion (asynchronous) with MT synchronization configured via SBL_x Data output: last result of S/D conversion triggered by pin T3 with MT synchronization configured via SBL_x On changing parameter MODE_ST during operation command SOFT_RES should be issued. 1. Regardless of the data readout: background conversion permanent 2. With a data readout: transmission of current data. MODE_ST Code 0x0F This mode can be used in systems which require that asynchronous sampling is independent of the data readout timing. The conversion procedure is as follows: 1. A conversion is triggered via pin T3, if applicable with gear box code synchronization. 2. With a data readout the most recent output data triggered by pin T3 is transmitted. 0x0D 0x0E 0x0F Notes Table 47: Multiturn modes iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 34/59 S/D CONVERSION with DIRECT OUTPUT iC-MN functions as a simultaneous sampling, 3channel sine-to-digital converter when the multiturn modes are selected with deactivated synchronization. When SBL_S = 0 and SBL_N = 0 no track synchronization takes place; the data from all three tracks is queued up for output without any further processing. Op. Mode Descriptions Of Direct Output Modes MODE_ST Code 0x0C The processing time is largely determined by the sum of the conversion time of the configured tracks. The conversion procedure is as follows: 1. A data readout request triggers the complete conversion of the set tracks 2. Transmission of the output data MODE_ST Code 0x0D The processing time is low as "old" data is transmitted, the time of sampling is, however, known (NB: The data from the first readout is invalid following a SOFT_RES). The conversion procedure is as follows: Figure 13: Principle of simultaneous sampling, 3channel S/D conversion with direct data output MODE_ST Addr. 0x3D; bit 7:4 Direct output via MT modes with deactivated synchronization Code 0x0C Description Data output following S/D conversion of all tracks; synchronization disabled (SBL_x = 0) Data output: result of previously triggered S/D conversion; synchronization disabled (SBL_x = 0) Data output: last result of background S/D conversion (asynchronous); synchronization disabled (SBL_x = 0) Data output: last result of S/D conversion triggered by pin T3; synchronization disabled (SBL_x = 0) On changing parameter MODE_ST during operation command SOFT_RES should be issued. 1. With a data readout: immediate transmission of the data from the last readout cycle 2. With a data readout: start of a new conversion and providing of data for the next readout cycle. MODE_ST Code 0x0E The processing time is low and the time of sampling not precisely known. The conversion procedure is as follows: 1. Regardless of the data readout: background conversion permanent 0x0D 0x0E 0x0F Notes 2. With a data readout: transmission of current data. MODE_ST Code 0x0F This mode can be used especially for resolver systems, in which 1 to 3 channels need to be sampled in synchronism with a specific carrier frequency. An external trigger signal supplied to pin T3 takes over the sampling control and thus decouples it from the data readout timing. The conversion procedure is as follows: 1. A conversion is triggered by pin T3 2. With a data readout the most recent output data triggered by pin T3 is transmitted. Table 48: MT modes used for direct output iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 35/59 TRACK OFFSET CALIBRATION Depending on the track resolution the offset values of the nonius and segment tracks (POV = Phase-OffsetValue) must be justified to the left in the SPO_N and SPO_S registers. These offsets are added to the conversion result of each track prior to synchronization and are instrumental in calibrating the track. SPO_N Addr. 0x3B; bit 1:0 Addr. 0x3A; bit 7:0 Addr. 0x39; bit 7:5 Addr. 0x39; bit 4:0 Addr. 0x38; bit 7:0 Track Offset SPO_S 0x0000 ... 0x1FFF datalength defined by UBL_x+SBL_x Table 49: Track offsets for nonius and segment SPO_x register: MSB POV_x LSB POV_x 0 0 0 S: ADR 0x39, bit 4 N: ADR 0x3B, bit 1 S: ADR 0x38, bit 0 N: ADR 0x39, bit 5 Figure 14: SPO_x (x=S,N) Note: For nonius synchronization (see MODE_ST) it is important that the used tracks within the 2UBL_S+UBL_N master track periods have a shared zero crossing once. With SPO_S or SPO_N the segment and nonius tracks can be shifted to the master track accordingly. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 36/59 I/O INTERFACE Protocol iC-MN can transmit position data according to the SSI protocol where both data length and error messaging are configurable. The selected mode of operation for sine-to-digital conversion can limit the permissible SSI clock frequency (see Operating Conditions on page 15). The highest possible SSI clock frequency of 4 MHz is permissible for converter modes with an immediate data output. TOS Code 00 01 10 11 Notes Addr. 0x4C; bit 1:0 Timeout tout Internal clock counts typ. typ. typ. typ. 16 s 8 s 2 s 1 s 31-32 15-16 3-4 1-2 4 fosc One clock count is equal to (see Char. A01) Table 50: Timeout Figure 15: Example of SSI line signals Output Data Length For singleturn data lengths (DL_ST) which are less than 13 bits the SSI data word is zero filled. The optional error bit is always the final bit of the data word. If enabled by M2S, multiturn data is always transmitted upfront the singleturn data. The format option Gray or binary code covers the MT and ST data word in its entirety; filled in zeros and the error bit remain untouched. The output bit count is determined by parameters DL_ST, M2S and ESSI: max(13, DL_ST+ESSI) + MT bits Example: DL_ST = 0 (8 Bit); ESSI = 1. Result: 8 bits of data + 4 zeros + 1 error bit are transmitted = 13 bits of data. DL_ST Code 0x00 ... 0x05 ... 0x11 Addr. 0x3E; bit 4:0 Bit count 8 bit plus zeroes (+1 error bit)* ... 13 bit (+1 error bit)* ... 25 bit (+1 error bit)* Bit counts listed below are valid only for multiturn synchronization mode (s.P. 30 ff.) 26 bit (+1 error bit)* ... 33 bit (+1 error bit)* 39 bit (+1 error bit)* *) When enabled by ESSI = 1 0x12 ... 0x19 0x1A Notes Table 51: ST Data length M2S Code 00 01 10 11 Addr. 0x3F; bit 2:1 Function no output MT data output of lowest 4 bits MT data output of lowest 8 bits Complete output, MT bit count following DL_MT Table 52: MT Data output iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 37/59 Output Options RSSI Code 0 ESSI Code 0 1 Addr. 0x3F; bit 5 Error bit output Not included Error bit enabled 1 Notes Addr. 0x3F; bit 4 Ring operation Normal output If the clock count exceeds the data length, zero bits are supplied. Ring operation When enabling RSSI with the BiSS C protocol, pin SLI reads in data to be output via SLO. Table 53: Error bit GRAY_SCD Addr. 0x3F; bit 7 Code Data format 0 1 Binary coded Gray coded Table 55: Ring operation The behavior of the output data depending on the sense of rotation can be altered using pin DIR or via register DIR. Both signals are EXOR-gated and switch output data from increasing to decreasing values or vice versa. DIR Code 0 1 Addr. 0x3D; bit 6 Code direction Not inverted Inverted Table 54: Data format (covers MT and ST data) Table 56: Code direction up/down iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 38/59 I/O INTERFACE with EXTENDED FUNCTIONS Protocol For the fast and safe transmission of converter data iCMN's serial I/O interface has a BiSS C protocol which enables bidirectional register communication without changing the permanent cyclic data output. In order to simplify master implementation at the control unit end this protocol does not utilize multicycle data. Alternatively, an advanced SSI protocol can be selected which permits unidirectional register communication for the transferral of parameters from the master to the slave iC-MN. NBISS Code 0 1 1 Addr. 0x3F; bit 3 Protocol BiSS C protocol (NC_BiSS = 0, RSSI = 1) Advanced SSI protocol (NC_BiSS = 0) SSI protocol (NC_BiSS = 1) Table 57: Interface protocol TOS Code 00 01 10 11 Notes Addr. 0x4C; bit 1:0 Timeout tout Internal clock counts typ. typ. typ. typ. 16 s 8 s 2 s 1 s 31-32 15-16 3-4 1-2 4 fosc One clock count is equal to (see Char. A01) Table 58: Timeout Figure 16: Example of line signals for BiSS C protocol Figure 17: Example of line signals for Advanced SSI protocol iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 39/59 Output Data Length The output bit count is derived from the parameters DL_ST, M2S and DL_MT. In accordance with the selected protocol two additional bits for the error and warning messages are always transmitted. The output bit length for singleturn data can be set independent of the internal converter resolution. For bit lengths which exceed the internal word length the data following the LSB is zero filled. If enabled by M2S multiturn data is always transmitted before singleturn data. DL_ST Code 0x00 ... 0x05 ... 0x11 Addr. 0x3E; bit 4:0 Bit count 8 bit +2 bit for E/W ... 13 bit +2 bit for E/W ... 25 bit +2 bit for E/W Bit counts listed below are valid only for multiturn synchronization mode (see P. 30) 26 bit +2 bit for E/W ... 33 bit +2 bit for E/W 39 bit +2 bit for E/W The code direction of the output data word can be altered using pin DIR or register DIR. Both signals are EXOR-gated and together comprise the internal direction of rotation signal. DIR Code 0 1 Addr. 0x3D; bit 6 Direction of rotation Not inverted Inverted Table 62: Inversion of code direction For reasons of data security iC-MN provides fixed CRC polynomials (see Table 63). The CRC start value can be freely selected, thus enabling a PLC to clearly allocate data to the source (for safety applications). Register communication can be optionally blocked by parameter NC_BiSS. Data Channel SCD CDM, CDS CRC HEX Code 0x43 0x13 Polynomial x6 +x1 +x0 x4 +x1 +x0 Calculation Start Value see CID_SCD 0x0 0x12 ... 0x19 0x1A Table 63: BiSS CRC polynomials CID_SCD Code 0x00 ... 0x0F Addr. 0x4C; bit 7:4 CRC start value SCD CID_SCD Table 59: ST Data length M2S Code 00 01 10 11 Addr. 0x3F; bit 2:1 Function No output MT data output of lowest 4 bits MT data output of lowest 8 bits Complete output, MT bit count following DL_MT Table 64: CRC start value for SCD NC_BISS Code 0 1 Addr. 0x43; bit 2 Function BiSS C register communication enabled Communication disable (no execution of commands, no access to RAM or EEPROM If the device setup and a set communication disable NC_BiSS are to be stored to the EEPROM, the preset function can be triggered at pin PRES. Table 60: MT Data output Output Options The Gray or binary code format option covers the singlecycle word in its entirety (MT and ST data); only filled in zeros and the error and warning bits remain unaltered. GRAY_SCD Addr. 0x3F; bit 7 Code Data format 0 1 Binary coded Gray coded Notes Table 65: Communication disable Table 61: Data format (covers MT and ST data) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 40/59 Safety Application Settings It is possible to transmit a life counter value in the sensor data for safety applications. When the life counter is activated, a 6-bit counter value is transmitted in the sensor data which is incremented with each new sensor data readout. The life counter has a range of 1 to 64. ELC Code 0 1 Addr. 0x3F; bit 6 Function (only with BiSS C protocol) Life counter not active Life counter enabled Table 66: Life counter Figure 18: Example of line signals for BiSS C protocol with life counter Busy Register iC-MN has a 16-bit busy register. If, for example, two identically configured iC-MNs are connected up to the BiSS master as slaves in a chain, with the help of the busy register an internal clock jitter can be avoided which could lead to different data conversion times for the two slaves. Should the busy register not be sufficient, i.e. should iC-MN need longer to convert data than the subsequent slave, iC-MN generates the start bit and marks the data it has output as faulty. This ensures that the data of the ensuing slave is not lost. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 41/59 CONFIGURATION OF DIGITAL DRIVER OUTPUTS The digital outputs SLO and NSLO can be used as either a push-pull, lowside or highside driver. The mode of operation is determined by DTRI. The driving capability is set via the short-circuit current parameter. In order to meet RS422 specifications a short-circuit current of 50 mA should be selected as well as to reduce the internal power dissipation. The driving capability can be reduced when external line drivers are used. In order to reduce crosstalk and to improve EMC the slew rate can be selected to suit the line length. If the edge steepness is reduced to 300 ns the maximum permissible transmission frequency is limited to ca. 300 kHz if RS422 specifications are to be adhered to. DTRI Code 00 01 10 11 Addr. 0x48; bit 3:2 Operating mode Push-pull operation Highside driver mode (P channel open drain) Lowside driver mode (N channel open drain) Not permitted DSC Code 00 01 10 11 Addr. 0x48; bit 1:0 Short-circuit current 50 mA 20 mA 4 mA 1.2 mA Table 68: Driver short-circuit current DSR Code 00 01 10 11 Addr. 0x48; bit 5:4 Slew rate Permissible transmission frequency 10 ns 30 ns 100 ns 300 ns 10 MHz max. 3 MHz max. 1 MHz max. 300 kHz max. Table 69: Driver slew-rate Table 67: Driver output mode iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 42/59 COMMAND and STATUS REGISTERS Execution Of Internal Commands The command register at address 0x77 can be accessed fully independent of the internal state of operation. Depending on the data value written to this register the execution of an implemented command is triggered. MN_CMD Code 0x0 Addr. 0x77; bit 2:0 Command Description SOFT_RES W 10 11 command can be used for SSI encoders to later enable parameterization, for example. Execution Of Protocol Commands iC-MN supports selected BiSS C protocol commands: CMD Selected address (IDS > 0x00) Execute SOFT_PRES Execute CRC_CHECK Broadcast address (IDS = 0x00) - 0x1 0x2 0x3 0x4 WRITE_CONF SOFT_PRES CRC_CHECK TOG_BISS Soft reset (new startup using internal config. data) Transfers internal config. data to the EEPROM Calls preset routine CRC verification of the internal config. data Temporal toggle of interface protocol: BiSS C SSI Table 71: Implemented protocol commands Automatic Reset Function AUTORES can be used to set whether the command SOFT_RES is automatically generated or not if the error AM_MIN occurs. AUTORES Code 00 01 10 11 Addr. 0x44; bit 1:0 Function No automatic reset SOFT_RES after error AM_MIN, timeout 8 ms SOFT_RES after error AM_MIN, timeout 16 ms SOFT_RES after error AM_MIN, timeout 32 ms ...0xF No function Table 70: Implemented commands The command SOFT_RES resets internal state machines, counters, and the status registers. The configuration RAM is not reset here. During the command execution a write access to the configuration RAM is still possible, whereas the external EEPROM is not accessible. If the device is in nonius mode (see page 30), the first conversion is used to determine the period and the result stored as an initial value for the period fraction of the internal flash counter. If an external multiturn device is configured (MODE_MT = 00), its data is read in and stored as the initial value for the multiturn data fraction of the internal flash counter. With WRITE_CONF the internal configuration is stored to the EEPROM. The CRC (CRC_E2P) is automatically updated and written to address 0x4E or 0x4F. For a description of the preset routine initiated by SOFT_PRES see page 50. CRC_CHECK starts a CRC verification of the internal configuration RAM. During the check the internal data bus may not be accessed. Should the check not confirm the configuration data as error free, status bit EPR_ERR is set. Command TOG_BISS only causes the communication protocol to switch temporarily (BiSS SSI, or SSI BiSS). RAM parameter NBISS is not altered here. The Table 72: Automatic reset function For as long as the amplitude of the master track is too low or the AM_MIN error is set, SOFT_RES is active. When AM_MIN is no longer set, the timeout configured using AUTORES expires. It is only after this that SOFT_RES is reset and the device subsequently returns to normal operation. Should an AM_MIN error occur while a command or the preset function is being carried out, SOFT_RES is only implemented once the command has been terminated. The behavior of the I/O interface with an active SOFT_RES depends on the protocol selected. For BiSS C a zero is returned as a data value and the error and warning bits are set; for SSI the last data value to be output is repeated (the error bit is set if configured via SSIE). In both cases the error state is indicated at pin NERR by a low signal. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 43/59 Status Register The status register is reached by a read access to addresses 0x75 to 0x77. In the event of an error the relevant bit is set and maintained until the status register is read out or the command SOFT_RES is performed (with the exception of status bits EPR_ERR and CMD_EXE). The status register can be accessed independent of the internal state of operation. STATUS Bit Name 7 6 TH_WRN EPR_ERR Addr. 0x75; bit 7:0 Description of status message R STATUS Bit Name 7 6 5 4 3 2 1 0 CMD_EXE CMD_CNV AN_Min AN_Max ACN_Min ACN_Max AS_Min AS_Max ACS_Min Notes Addr. 0x77; bit 7:0 Description of status message Command execution in progress, or iC-MN in startup phase Signal error: poor level (nonius track) Signal error: clipping (nonius track) Control error: range at min. limit Control error: range at max. limit Signal error: poor level (segment track) Signal error: clipping (segment track) Control error: range at min. limit Error indication logic: 1 = true, 0 = false R ROM has been recognized, EPR_ERR remains set even after SOFT_RES. CMD_CNV and CMD_EXE are signaled on the same status bit and not stored, as opposed to the other status bits. CMD_CNV is set on the initialization of a command which requires the internal converter. CMD_EXE is set on commands which employ the internal data bus. 5 4 3 2 1 FQ_WDR FQ_STUP NON_CTR MT_CTR MT_ERR Excessive temperature warning Configuration error on startup: - No EEPROM (flag EPR_NO set) - Invalid check sum (flag EPR_NV set) Excessive signal frequency on master track*: on current readout request Excessive signal frequency on master track*: during startup Period counter consistency error: counted period calculated Nonius position Multiturn data consistency error: counted multiturn external MT data Multiturn communication error: - Error bit set - CRC error - No start bit - General communication error Multiturn data indicates warning message (BiSS warning bit set) *) Relevant for nonius synchronization modes (MODE_ST = 0x00 to 0x0B); the warning threshold can be set using parameter FRQ_TH; Error indication logic: 1 = true, 0 = false Table 75: Status register 0x77 Non-Volatile Diagnosis Memory By enabling E2EPR all status messages can be stored to the external EEPROM the first time they occur (physical EEPROM addresses 0x75 to 0x77). On a system startup iC-MN reads in the status messages already stored in the EEPROM. As soon as an error message occurs which has not been noted in the external memory the corresponding status register bit is transfered to the EEPROM. This way a "cumulative" error register is compiled in which all messages are stored which occur during operation. Only the current errors can be read out via the status register (BiSS addresses 0x75 to 0x77). The cumulative errors which are stored at EEPROM addresses 0x75 to 0x77 can only be read out via BiSS with CFG_E2P > 000 and PROT_E2P = 00 to bank 1, address 0x35-0x37 (see page 52 ff. for memory map). Note: Once configuration has been completed and before the system is delivered the data at the EEPROM addresses 0x75 to 0x77 should be initialized with zeroes. E2EPR Code 0 1 Addr. 0x41; bit 7 Description Disabled EEPROM savings of cumulative status messages enabled 0 MT_WRN Notes Table 73: Status register 0x75 STATUS Bit Name 7 6 5 4 3 2 1 0 ACS_Max AM_Min AM_Max ACM_Min ACM_Max CT_ERR RF_ERR TH_ERR Notes Addr. 0x76; bit 7:0 Description of status message Control error: range at max. limit Signal error: poor level (master track) Signal error: clipping (master track) Control error: range at min. limit Control error: range at max. limit Readout cycle repetition to short* Excessive SSI clock frequency: conversion data not valid when latching data for output. Excessive temperature error *) Relevant for nonius synchronization modes MODE_ST = 0x00 to 0x07 (calculation routines must end before a new request is received) Error indication logic: 1 = true, 0 = false R Table 74: Status register 0x76 EPR_ERR indicates that no EEPROM was found on system startup (EPR_NO) or that a CRC error was recognized for the internal setup (EPR_NV). If no EEP- Table 76: Diagnosis memory enable iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 44/59 ERROR AND WARNING BIT For the error and warning bit output the logic is always low active; a logic zero displays an active error or warning message. With the exception of an external system error message (read in via I/O pin NERR and assigned to EXT_ERR) all error codes mentioned in the following are stored in the status register should the corresponding error event occur. The allocation of error messages to the error and warning bit is either fixed or can be varied with the CFGEW parameter. The following tables explain the fixed and optional visibility. Fixed Allocation Of Error Messages Visibility via error bit Conditions * None CFGEW Bit 7 6 5 featuring open-drain alarm outputs a wired-or bus logic can be installed. EXT_ERR Code 0 1 Description No external error External component indicating an error to pin NERR Table 79: External error message Adr 0x42, bit(7:0) Visibility for error bit Ax_MAX, Ax_MIN EXT_ERR TH_ERR Enables additional functions, please refer to the description given below. Visibility for warning bit FQ_WDR Ax_MAX and Ax_MIN ACx_MAX and ACx_MIN TH_WRN MT_WRN x = M, S, N Encoding of bit 7...0: 0 = message enabled, 1 = message disabled Message EPR_NV* EPR_NO CMD_CNV** CT_ERR RF_ERR MT_ERR MT_CTR NON_CTR FQ_STUP Notes * * * Visible when NBISS = 1 Visible when MODE_MT = 01, 10 Visible when MODE_ST set for nonius synch. Bit 4 3 2 1 0 Notes *) Reset by command SOFT_RES **) CMD_CNV is also visible for warning bit. Table 77: Fixed allocation of messages for error bit indication Variable Allocation Of Error Messages Visibility via error bit Visibility via warning bit n/a n/a n/a n/a n/a = configurable via CFGEW x = M, S, N n/a n/a Table 80: Error and warning bit configuration The visibility of the temperature error can be configured on the error bit by CFGEW(5) = 0. The occurrence of a temperature error then causes: 1. The setpoint of the signal level controller to be reduced to the lowest setting 2. The analog output voltages to switch to VDD/2 at outputs PSOUT, NSOUT, PCOUT and NCOUT 3. The RS422 output driving capability to be limited to 20 mA. The following must also be taken into account: * Error messages which are signaled via the error bit of the serial I/O interface are also indicated by a low signal at the NERR pin * Nonius synchronization errors (NON_CTR) are indicated directly at the NERR pin Message MT_WRN TH_WRN FQ_WDR ACx_MAX ACx_MIN Ax_MAX Ax_MIN TH_ERR EXT_ERR Notes Table 78: Variable allocation of error messages for error/warning bit indication EXT_ERR can only be configured to the error bit and is not latched by the status register. It permits iC-MN to signal an error state of further ICs to the PLC, when the messaging IC pulls down the NERR pin. With devices iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 45/59 * Temperature and signal level errors are indicated directly at the NERR pin. These errors are only signaled via the error bit if they are active at the point when data is accepted into the output shift register. of the error bit and the NERR pin can be influenced by S2ERR. S2WRN Code 0 1 Addr. 0x43; bit 2 Visibility for warning bit Current messages configured to the warning bit As above, or-gated with latched status messages which are configured to the warning bit All errors which occur during operation are stored in the status register regardless of the configuration of the error/warning bit (see page 43). Visibility Of Latched Status Messages Parameter S2WRN enables status messages configured to the warning bit using CFGEW and stored in the status register to be output to the warning bit. In this instance the warning bit is set until the relevant status register is read out. Parallel to S2WRN the behavior S2ERR Code 0 1 Table 81: Visibility for warning bit Addr. 0x43; bit 3 Visibility for error bit and NERR Current messages configured to the error bit As above, or-gated with latched status messages which are configured to the error bit Table 82: Visibility for error bit (and NERR pin) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 46/59 MT INTERFACE In nonius modes iC-MN can connect to an external multiturn sensor via the serial MT interface. Following synchronization of the MT data with the ST data the multiturn period counter is set to its initial position. Each further revolution is then logged by the internal period counter. Even when the MT interface is not employed, the internal 24-bit multiturn period counter can be configured to complement singleturn position data output by a counted multiturn position (see M2S). Additionally, the MT interface can be configured as a parallel two-pin interface to read in a single bit multiturn position accompanied by a synchronization bit. In this way coverage of the absolute singleturn position can be doubled if additional sensors provide 180 and 90 degree sector information. MODE_MT Addr. 0x40; bit 4:3 Code Function 00* 10* 11* Multiturn position counted internally Serial MT interface active (SSI) Parallel MT interface active (2-bit mode): Pin MTMA is input for 180 and pin MTSLI input for 90 sector information *) NCRC_MT = 0 required If MODE_MT is altered during operation, command SOFT_RES must be issued (see page 42). 18 0 27 0 18 0 27 0 90 90 0 ST MSB-1 ST MSB ideal 2 bit synchronisation SBL_MT=0x1 MT LSB -1 MT LSB multiturn data output MT LSB -1 MT LSB multiturn data output MT LSB -1 MT LSB multiturn data output -1 -1 /ST ideal 1 bit synchronisation leading SBL_MT=0x0 LNT_MT=1 +1 +1 Figure 19: Principle of MT synchronization for 1 bit and 2 bit synchronization signals Notes Table 83: MT Interface operation mode Configuration Of Data Lengths The bit length of the internal MT counter and of the multiturn data word is set using parameter DL_MT. For synchronization purposes the synchronization bit length must be set by SBL_MT. Synchronization occurs between the external multiturn data read in and the period information counted internally. At synchronization bit lengths > 1 bit synchronization can occur automatically within the relevant phase tolerances. With a single synchronization bit (SBL_MT = 00) no automatic synchronization can take place. Here, iC-MN cannot recognize whether the external multiturn sensor provides leading or trailing position data (what may vary depending on gear box assembly). This must be set manually by parameter LNT_MT. Figure 19 shows the principle of MT synchronization for ideal signals (without indication of synchronization tolerance limits). It shows 2 bit and 1 bit synchronization for leading and trailing signals. With a synchronization bit length of two or more bits iC-MN ignores parameter LNT_MT selecting for leading or trailing MT data. Synchronization bit lengths of 3 bit or 4 bit enlarge further the synchronization tolerance between multiturn and singleturn (see Table 85). DL_MT Code 0x00 ... 0x0C 0x0D 0x0E 0x0F Notes Table 84: MT data length (and counter depth) trailing SBL_MT=0x0 LNT_MT=0 Addr. 0x3E; bit 7:5 Multiturn bit count* 8 ... 20 24 1 4 *) Does not include synchronization bits of the external MT sensor. 0 iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 47/59 SBL_MT Code 00 01 10 11 Addr. 0x41; bit 1:0 MT synchronization bit Synchronization range length (ST resolution) 1 bit 2 bit 3 bit 4 bit 90 90 135 157.5 startup sequence with 16 ms timeout further readouts are attempted and MT_ERR remains permanently set. Table 85: MT synchronization bit length LNT_MT Code 0 1 Addr. 0x41; bit 2 Function (single sync. bit, SBL_MT = 0x00) Trailing Leading read external multiturn mt-error-counter ++ yes serial-communication error? yes mt_error-counter < 4 no no set MT_ERR Table 86: Leading/trailing gear box assembly Via CHK_MT the device can be configured so that the counted multiturn period is verified every 8 ms. An error in the multiturn check (the comparison of the counted multiturn period and the external multiturn position data) is signaled via the error bit (MT_CTR is set in the status register, see page 43). CHK_MT Code 0 1 Addr. 0x40; bit 6 Function Verification disabled Cyclic verification each 8 ms CHK_MT? yes sync to flashcounter proceed with startup-sequence proceed with startup-sequence no further multiturn-readouts started Figure 20: Error handling during start up phase normal operation: ready for sensordata-requests Table 87: Period counter verification GRAY_MT Code 0 1 Addr. 0x41; bit 3 Data format Binary coded Gray coded start timer timer == 8 ms? yes read external multiturn sync to flashcounter and compare to counted multiturn-value no serial communication error? Table 88: MT Interface data format no compare-error? yes yes Error Handling If a communication error appears when reading in external multiturn data during the startup phase (such as pin MTSLI reading a permanent logic 0 or the external MT sensor not responding), the first conversion and request for the external multiturn data are repeated up to three times (see Figure 20). If the error persists after a fourth attempted readin, the device goes into normal operating mode. Conversion requests for the singleturn position data are possible, but MT_ERR remains permanently set. The error handling in normal operating mode when the multiturn data verification is activated is shown in Figure 21. If there is an error in communication no set MT_CTR set MT_ERR Figure 21: Error handling during normal operation with cyclic period counter verification Figure 22: Line signals of the serial MT interface MODE_MT = 0x10 (SSI) iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 48/59 MT Interface with 2-bit mode In this mode pin MTMA functions as an additional input, besides pin MTSLI. The inputs now expect digital signals phase shifted by 90, whereas MTMA reads the single bit period information, and MTSLI the shifted synchronization bit. The following figure explains the principle and the table below gives the necessary settings. calculated nonius position max max calculated nonius position max max sector 0 sector 1 external 2 bit sector signals gray coded MTSLI MTMA master analog sensorinterface segment sector 0 0 sector 1 360 /rev . resulting dataword 2*max nonius 2 bit sector code (gray coded) 0 360 /rev . MTMA /rev . MTMA 90 13 5 18 0 22 5 27 0 31 5 0 Figure 23: Principle of 2-bit mode 45 0 /rev Parameter MODE_MT = 11 DL_MT = 0x0E SBL_MT = 00 LNT_MT = 0 or 1 GRAY_MT = 1 M2S = 11 Description MT interface op. mode: 2-bit mode MT data length: 1 bit Synchronization bit length: 1 bit Depending on MTMA signal: leading or trailing MT data format: Gray coded Enable for MT plus ST data output Figure 24: Position of switch points in reference to the parameter LNT_MT A typical application example where the 2-bit mode can be used for, is a magnetic angle encoder scanning the pole wheel by MR sensors. A nonius coded wheel of 16, 15 and 12 pole pairs yields 32, 30 and 24 sine periods per turn on iC-MN's analog inputs. The nonius calculation would not produce absolute angle position data over a single revolution since the maximum singleturn value is achieved twice. The distinction as to which half of the revolution the axis is in can only be made using section sensors, two Hall sensors for example, whose digital outputs are connected up directly to MTMA and MTSLI. Furthermore, the 2-bit mode can be used also with systems based on a 2 track nonius calculation. Table 89: Required settings for 2-bit mode The required position of the multiturn and synchronization bit depends on parameter LNT_MT. Figure 24 shows the required signal positions with leading respectively trailing operation. The green arrows are indicating the permissible relative position tolerances. leading MTSLI 0 360 MTSLI LNT_MT=1 iC-MN multiturninterface LNT_MT=0 trailing iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 49/59 MT INTERFACE with EXTENDED FUNCTIONS The serial multiturn interface can be operated in the BiSS C protocol which enables multiturn sensor error messages to be evaluated (via the error and warning bits, each of which are low active) and communication to be monitored (evaluation of the CRC bits, see Figure 25). The error behavior of the multiturn interface has already been described in Figures 20 and 21; only a set error bit (low) or a CRC error are now also classified as a communication error. MODE_MT Addr. 0x40; bit 4:3 Code Function 00 01 Notes Internal multiturn period counting BiSS C protocol If MODE_MT is altered during operation, command SOFT_RES must be issued (see page 42). SWC_MT Code 0 1 Addr. 0x41; bit 6 CRC polynomial (HEX) 0x43 0x25 Table 91: MT Interface CRC polynomial NCRC_MT Code 0* 1 Note Addr. 0x41; bit 4 Function CRC verification active Disabled *) Only permitted with MODE_MT = 01. Table 92: MT Interface CRC verification Table 90: MT Interface operation mode Figure 25: Example of the MT interface line signals with BiSS C protocol Direct Communication To Multiturn Sensor Making use of the BiSS Interface bus capabilities, iCMN can connect the external multiturn sensor to the BiSS master controller when GET_MT is enabled. To this end pin MA receiving the BiSS master's clock signal is fed through to pin MTMA and the MTSLI pin is activated in place of the SLI pin. Upon enabling this mode the singlecycle timeout must have elapsed and an additional init command carried out by the BiSS master, before it can run the first register communication. Example: external multiturn sensor built with iC-MN is connected to the MT interface of a first iC-MN, preparing the singleturn data. With GET_MT enabled, the external multiturn can then be addressed via BiSS ID 0 and the singleturn via BiSS ID 1. This temporal chain operation eases device parameterization during encoder manufacturing. GET_MT Code 0 1 Addr. 0x41; bit 5 Function Disabled MT sensor communication enabled Table 93: Direct BiSS communication enable for MT sensor via I/O Interface iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 50/59 PRESET FUNCTION The preset function sets the output position data to a predefined position value and is initiated by a high flank at pin PRES or by calling the SOFT_PRES command (writing 0x02 to the command register, see Table 70). If an external EEPROM is available the preset values are read in from the preset registers. A preset value of zero is otherwise assumed. The current position is determined. Correction factors for the output (OFFS_ST, OFFS_MT) are calculated and stored in the internal RAM. With an EEPROM available the entire contents of the RAM are written to said EEPROM, thus storing the OFFS_ST and OFFS_MT data. Note: Command SOFT_PRES blocks iC-MN's internal RAM for accesses over a certain time. For the output the OFFS_ST and OFFS_MT values are subtracted from the internal synchronized result with each conversion (Note: In MODE_ST = 0x05-0x07 and 0x0D the sensor data is designated faulty after the first readout. The readout data is equivalent to the correction factor.) OFFS_ST Addr. 0x34; bit 6:0 Addr. Addr. Addr. Addr. 0x00000 Figure 26; see Figure 27 for multiturn synchronization operating mode. In the PRES_MT register the multiturn preset values are always justified to the right with the LSB (starting at address 0x55, bit 0). OFFS_MT Addr. 0x37; bit 7:0 Addr. 0x36; bit 7:0 Addr. 0x35; bit 7:0 Multiturn output offset 0x000 ... 0xFFF Table 96: Position offset for MT data output PRES_MT Addr. 0x57; bit 7:0 Addr. 0x56; bit 7:0 Addr. 0x55; bit 7:0 0x000 ... 0xFFF Preset register multiturn (EEPROM only) 0x33; 0x32; 0x31; 0x30; bit 7:0 bit 7:0 bit 7:0 bit 7:0 physical resolution: Table 97: Preset value for MT data output up to 12 bit period-information UBL_S+UBL_N up to 13 bit master-information UBL_M MSB period LSB period MSB master LSB master ... 0x7FFFF Singleturn output offset PRES_ST register: 0 0 0 MSB ST_DW LSB ST_DW 0 0 0 0 0 Table 94: Position offset for ST data output ADR 0x54 bit 6 ADR 0x53 bit 3 ADR 0x53 bit 2 ADR 0x51 bit 6 PRES_ST Addr. 0x54; bit 6:0 Addr. Addr. Addr. Addr. 0x53; 0x52; 0x51; 0x50; bit 7:0 bit 7:0 bit 7:0 bit 7:0 datalength defined by DL_ST Figure 26: PRES_ST with nonius synchronization mode up to 39 bit preset-information MSB left aligned 0x00000 ... 0x7FFFF Preset register singleturn (EEPROM only, see text) PRES_ST register: MSB ST_DW datalength defined by DL_ST LSB ST_DW 0 0 0 Table 95: Preset value for ST data output The position of the preset value for the singleturn data word (ST_DW) in preset register PRES_ST varies depending on the converter mode (MODE_ST see Table 42). For nonius synchronization operating mode see ADR 0x54 bit 6 ADR 0x50 bit 0 Figure 27: PRES_ST with multiturn synchronization mode iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 51/59 STARTUP BEHAVIOR Figure 28 shows the startup behavior of iC-MN. After turning on the power supply (power-on reset) iC-MN reads the configuration data from the EEPROM. If the data can be read without error, a timeout of 8 ms is allowed to elapse. If the multiturn interface has been configured for an external sensor, the device waits for a longer timeout of 16 ms to elapse. The multiturn data is then read in and the first conversion performed in order to determine the absolute position (see page 47). iC-MN then goes into normal operation. startup If an error occurs while the EEPROM data is being read (a CRC error or communication error with the EEPROM), the current readin process is canceled and restarted. Following a third failed attempt the readin procedure is ended and the internal iC-MN configuration registers (addresses 0x00 to 0x4D) initialized with a zero. In doing so, NBISS = 0 selects for the BiSS C protocol for the I/O interface enabling BiSS C register communication. If an attempt to read sensor data is made iC-MN would reply an 8-bit zero value with set error and warning bits (sequence: start bit 1x high, position 8x zero, error/warning 2x zero, CRC 6x high followed by zero bits when the clock signal is continued). Following successful configuration using the I/O interface command SOFT_RES must be issued in order to switch iC-MN to normal operation (see page 42). read EEPROM (max 3 times on error) EEPROM ok? serial-interface active for configuration (no sensor data request possible) MODE_MT = 00 yes no 8 ms timeout 16 ms timeout via command SOFT_RES MODE_ST: sync_mode is nonius? no yes yes MODE_MT = 00 no command execution normal operation: ready for sensor data requests first conversion to get initial period information multiturn-startup Figure 28: Startup behavior iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 52/59 EEPROM INTERFACE The serial EEPROM interface consists of the two pins SCL and SDA and enables read and write access to a serial EEPROM (such as a 24C02 with 128 bytes, 5 V type with a 3.3 V function). The data in the EEPROM is secured by a CRC to the addresses 0x4E and 0x4F. Application Hints To protect the EEPROM against a reversed power supply voltage it can be connected to the integrated supply switch (pins VDDA and GNDA). The EEPROM specifications and absolute maximum ratings should comply to the pin voltages of VDDA, SCL and SDA during startup and operation. A protective circuit may be advisable depending on the EEPROM model. For EEPROM selection the following minimal requirements must be fulfilled: (e. g. Atmel AT24C01B, 128x8) CFG_E2P Adr 0x40; Bit 2:0 Banks per area (64 bytes each) CONF EDS USER EEPROM, Typ 1 9 1 25 17 5 1 kbit, C01 up 2 kbit, C02 up 4 kbit, C04 up 8 kbit, C08 up 8 kbit, C08 up 16 kbit, C016 up 16 kbit, C016 up 16 kbit, C016 up Code Bytes For SSI applications: 000* 128 2 001 256 3 1 For BiSS applications with EDS: 010 512 3 4 011 1024 3 4 100 1024 3 12 101 2048 3 4 110 2048 3 12 111 2048 3 24 Notes *) direct addressing mode Table 99: Configuration of external memory Direct Addressing The registers can be accessed via the I/O interface and direct addressing (for CFG_E2P = 000). In accordance with the BiSS protocol the number of bytes addressed is restricted to 128. Accessing addresses 0x00 to 0x4F reads or writes to iC-MN's internal RAM register. The data from this special address area can only be transmitted to the EEPROM by the command WRITE_CONF. The registers for addresses 0x50 to 0x70, 0x78 to 0x7B and 0x7D to 0x7F are in the EEPROM and can be accessed byte-wise by a BiSS register access for read or write. The addresses missing in the above are located in iCMN: the status register from 0x75 to 0x77 (read only), the MN_CMD register at 0x77 (write only), and the I/O interface parameters CID_SCD and TOS at address 0x7C. The latter has no access limitations and can always be read and written to (content is mirrored to 0x4C). Bank-Wise Addressing iC-MN also supports bank-wise addressing (for CFG_E2P = 000) according to the BiSS Interface C Protocol Description. In this mode of configuration iCMN divides the internal address sections into banks of 64 bytes each. The address sections visible via the I/O interface recognizes a "dynamic" section (addresses 0x00 to 0x3F) and a "static" section which is permanently visible (addresses 0x40 to 0x7F). The static address section is always independent of the bank currently selected. Figure 29 illustrates how the banks selected by BANKSEL are addressed. * Operation from 3.3 V to 5 V, I2 C-Interface * Minimal 1024 bit, 128x8 CRC_E2P(1:0) Addr. 0x4F; bit 7:6 CRC_E2P(9:2) Addr. 0x4E; bit 7:0 Code Description 0x000 ... 0x3FF CRC formed by CRC polynomial 0x409 Table 98: EEPROM Data Check Sum Memory Map And Register Access Depending on the EEPROM size different bank assignments can be configured using CFG_E2P. There are three areas, placed one after the other, which are designated for this purpose in the memory: 1. CONF: iC-MN configuration data 2. EDS : Electronic Data Sheet 3. USER: OEM data, free user area iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 53/59 iC-MN internal linear addressspace divided into n banks of size 64 byte address-space visible via BiSS (CFG_E2P > 000) bank n-1 (e.g. CFG_E2P > 101; n=32) bank 3 bank 2 bank 1 ADR ADR 0x00 0x00 bank 0 0x3F 0x40 0x7F 0x80 0x3F 0x40 0xBF 0xC0 BANKSEL EDSBANK profile ID 0xFF serial number SLAVE-registers STATUS 0x7F ... BiSS-ID Figure 29: Principle of bank-wise memory addressing Register access can be restricted via PROT_E2P (see Table 100). PROT_E2P = 10 selects safety level 2, a shipping mode with limited access. Shipping 2 can be set back to level 1 (shipping 1), for which purpose the content of address 0x43 must be written anew. PROT_E2P(1:0) Code 00 01 10 11 Mode Configuration Mode, free access Configuration Mode, limited access Shipping Mode 1, reset to RP1 is possible Shipping Mode 2, reset is not possible Addr. 0x43; bit 1:0 Access Limitation (see Figure 30 and 31) RP0 RP1 RP2 RP2 PROT_E2P(1:0) Addr. 0x43; bit 1:0 Range RPL* CONF EDS RP0 RP1 RP2 Note r/w STATUS n/a r/w for others n/a r/w r/w r only .. selects . USER r/w r/w r/w * Register Protection Level Table 101: Register Read/Write Protection Levels (n/a: iC-MN refuses access to those register addresses.) Figure 30 shows the static memory area and Figure 31 the area which can be altered by BANKSEL. The BiSS register access limitations which are generated by parameter PROT_E2P are marked "R/W" for read/write access and "R" for read only. The original site of data returned by access to the BiSS register is designated by "RAM" for iC-MN's internal RAM, by "E2P" for the EEPROM and by "INT" for those of iC-MN's internal registers which cannot be preloaded on startup. Table 100: Register Access Control Sections CONF, EDS and USER are protected at different levels in shipping mode for read and write access. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 54/59 static part: BiSS addresses 0x3F-0x7F registerprotectionlevel data mapped to address RP1 RP2 location internal R/W INT 0x081 0x082 0x083 0x084 0x087 0x088 SLAVE-registers 0x0AF 0x0B0 reserved STATUS STATUS STATUS/MN_CMD 0x0B4 internal 0x078 BISS-ID 0x04C ... 0x07F ... R/W R R/W R INT E2P RAM E2P ... ... ... R E2P addressing scheme bank address 0x40 0x41 0x42 0x43 0x44 0x47 0x48 0x6F 0x70 0x74 0x75 0x76 0x77 0x78 0x7C 0x7F ... ... ... ... ... content BANKSEL EDSBANK profile ID serial number 0-31 R/W Figure 30: User view: BiSS memory access 0x40 to 0x7F, content independent of BANKSEL; CFG_E2P = 000 bank switched part: BiSS addresses 0x00-0x3F registerprotectionlevel data mapped to address RP1 RP2 location 0x000 ... 0x03F 0x040 0x04C ... 0x04F 0x050 preset-values free STATUS accumulated (see E2EPR for details) 0x057 0x075 0x076 0x077 0x078 0x04C 0x07F 0x080 0x081 0x0AF 0x0B0 ... 0x0BF 0x0C0 0x0FF ... 0x7C0 0x7FF ... ... ... R or R/W ... R R/W E2P ... ... ... n/a E2P ... ... R/W n/a RAM R/W n/a R/W 0x3F 0x00 0x0C 0x0F 0x10 1 0x17 0x35 0x36 0x37 0x38 0x3C 0x3F 0x00 0x01 2 0x2F 0x30 0x3F 0x00 3 ... 0x3F 0x00 31 0x3F ... ... ... ... ... ... ... ... ... ... ... ... addressing scheme bank address content 0x00 0 parameter values with CRC n/a R R/W RAM BiSS-ID reserved EDSBANK, profile ID, serial number, SLAVEregisters reserved Figure 31: User view: BiSS memory access 0x00 to 0x3F, content switchable with BANKSEL; CFG_E2P = 000 iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 55/59 APPLICATION NOTES: Configuration As BiSS C-Slave Including EDS (Electronic Data Sheet) Preconditions: 1. CFG_E2P <> b000. The bank switch function must be activated. 2. EDSBANK = 0x03. No other values possible. Addressing via BiSS: Bank: 2, Adr: 0x01 or direct to EEPROM: Adr: 0x081 3. Setting of profile ID according to the following tables; Addressing via BiSS: Bank: 2, Adr: 0x02-0x03 or direct to EEPROM: Adr: 0x082-0x083 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 0-12 0x00-0x0B (Nonius) 0x0C-0x0F (Multiturn) 0 0 0 0x04 (12) 0x00 0x00 (0) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 12 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 12-12 0x00-0x0B (Nonius) 0 0 0 0x04 (12) 0x04 (12) 0x03 0x0C (12) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 12 Table 105: Setup for BiSS profile 12-12 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 12-24 0x00-0x0B (Nonius) 0 0 0 0x10 (24) 0x04 (12) 0x03 0x0C (12) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 24 Table 102: Setup for BiSS profile 0-12 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 0-24 0x00-0x0B (Nonius) 0x0C-0x0F (Multiturn) 0 0 0 0x10 (24) 0x00 0x00 (0) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 24 Table 106: Setup for BiSS profile 12-24 Table 103: Setup for BiSS profile 0-24 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 0-24++ 0x00-0x0B (Nonius) 0 0 0 0x11(25) 0x00 0x00 (0) 0x19 (25) = 0x00 UBL_M=13, UBL_N=6 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 12-24++ 0x00-0x0B (Nonius) 0 0 0 0x11(25) 0x04 (12) 0x03 0x0C (12) 0x19 (25) = 0x00 UBL_M=13, UBL_S=6, UBL_N=6 Table 107: Setup for BiSS profile 12-24++ 0x0C-0x0F (Multiturn) > 0x10 (24) < 0x18 (32) UBL_M+UBL_S+UBL_N UBL_S=6, UBL_M+UBL_S+UBL_N = DL_ST; UBL_M+UBL_S+UBL_N > 24 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 24-12 0x00-0x0B (Nonius) 0 0 0 0x04 (12) 0x0D (24) 0x03 0x18 (24) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 12 Table 104: Setup for BiSS profile 0-24++ Table 108: Setup for BiSS profile 24-12 iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 56/59 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 24-24 0x00-0x0B (Nonius) 0 0 0 0x10 (24) 0x0D (24) 0x03 0x18 (24) UBL_M+UBL_S+UBL_N = 0x00 UBL_M+UBL_S+UBL_N 24 Remarks to iC-MN with EDS: 1. CFG_E2P = b000 (i.e. bank switch function has been activated.) 2. EDSBANK must be set 0x03 (no other values are possible) Addressing via BiSS: Bank: 2, Adr: 0x01 or direct to EEPROM: Adr: 0x081 3. Set profile ID. Addressierung via BiSS: Bank: 2, Adr: 0x020x03 or direct to EEPROM: Adr: 0x082-0x083 Table 109: Setup for BiSS profile 24-24 BiSS Profile MODE_ST NBISS ELC GRAY_SCD DL_ST DL_MT M2S R_MT R_ST SBL_x Notes 24-24++ 0x00-0x0B (Nonius) 0 0 0 0x11(25) 0x0D (24) 0x03 0x18 (24) 0x19 (25) = 0x00 UBL_M=13, UBL_S=6, UBL_N=6 Table 110: Setup for BiSS profile 24-24++ iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 57/59 APPLICATION NOTES: PLC Operation PLC Operation There are PLCs with a remote sense supply which require longer for the voltage regulation to settle. At the same time the PLC inputs can have high-impedance resistances versus an internal, negative supply voltage which define the input potential for open inputs. In this instance iC-MN's reverse polarity protection feature can be activated as the outputs are tristate during the start phase and the resistances in the PLC determine the pin potential. During the start phase neither the supply VDD nor the output pins, which are also monitored, must fall to below ground potential (pin GND); otherwise the device is not configured and the outputs remain permanently set to tristate. In order to ensure that iC-MN starts with the PLCs mentioned above pull-up resistors can be used in the encoder. Values of 100 k are usually sufficient; it is, however, recommended that PLC specifications be specifically referred to here. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 58/59 DESIGN REVIEW: Notes On Chip Functions iC-MN Y2 No. Function, Parameter/Code Description and Application Hints No exclusions known at time of printing. Table 111: Notes on chip functions regarding iC-MN chip releas Y2 iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. 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In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-MN 25-BIT NONIUS ENCODER WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION Rev D1, Page 59/59 ORDERING INFORMATION Type iC-MN Evaluation Board Package 48-pin QFN 7x7 mm Size 140mm x 100mm Order Designation iC-MN QFN48 iC-MN EVAL MN1D For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com Appointed local distributors: http://www.ichaus.com/sales_partners |
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