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TE7753/TE7754 DATA SHEET
TE7753/TE7754
SUPER I/O EXPANDER
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[Outline] TE7753 and TE7754 are peripheral devices connected to a microprocessor, or general-purpose interface devices each having nine 8-bit parallel data input/output ports. Two port I/O setting modes, soft mode and hard mode, can be selected. Switching the modes eases the connection to an 86-series or 68-series CPU. [Characteristics] 1. 2. 3. 4. 5. Equipped with nine 8-bit parallel I/O ports Allowing I/O setting in bit units (port 8 only) Interface designed for connections with various types of CPUs High drive current (IOL = 12 mA: Port 9 only) Choice of two modes Soft mode : I/O setting is enabled for nine ports by software instructions from the CPU. Hard mode : I/O setting is enabled for six ports by hardware setting of pins IOS2 to IOS0. 6. Space merit (body size 14 mm x 14 mm) 7. State of ports after resetting Soft mode : All ports are in input state. Hard mode : TE7753: Output ports are in High state. TE7754: Output ports are in Low state. 8. CMOS, 5 V (single supply voltage)
Rev.1.00
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[Contents]
TE7753/TE7754
[Outline] ..................................................................................................................................................1 [Characteristics].......................................................................................................................................1 [Contents] ...............................................................................................................................................2 [Block Diagram] .......................................................................................................................................3 [Pin Assignments] ....................................................................................................................................4 [Description of Pins] .................................................................................................................................5 [CPU Interface] ........................................................................................................................................7 [Description of Operation] .........................................................................................................................8 www..com 1. Soft mode and hard mode ................................................................................................................8 2. Setting each port for input or output using CR .................................................................................. 12 [Absolute maximum ratings].................................................................................................................... 13 [Recommended operation conditions] ..................................................................................................... 13 [DC characteristics]................................................................................................................................ 14 [Input/output pin capacity]....................................................................................................................... 14 [AC characteristics]................................................................................................................................ 15 [Reset input conditions] .......................................................................................................................... 22 [Outside dimensions].............................................................................................................................. 23 [Notations] 1. Voltage levels are indicated differently for input and output signals. Voltage level VDD VSS Input signal 1 0 Output signal H L
2. A signal with the enable level being negative logic is indicated with its name preceded by # as shown below: Examples: #CS, #RD 3. The value indicated in a register is the initial value after resetting.
Rev.1.00
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[Block Diagram]
TE7753/TE7754
CR0
8
I/O Port 1
P17 ~ 10
8 D7 ~ 0
Data Bus Buffer
4 P23 ~ 20
I/O Port 2 CR1
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4
P27 ~ 24
A3 A2 A1 A0
8
Adress Decoder I/O Port 3
P37 ~ 30
8 8 #RESET #CS #RD/R#W #WR/#MEN
Control Logic I/O Port 4
P47 ~ 40
4 P53 ~ 50
CR2 I/O Port 5
4 P57 ~ 54 IOS2 IOS1 IOS0
I/O Port 6
8 P67 ~ 60
MS
Mode Selector
8
I/O Port 7
P77 ~ 70
8
P80 P81 P82 P83 P84 P85 P86 P87
CR3
I/O Port 8
8
I/O Port 9
P97 ~ 90
Rev.1.00
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[Pin Assignments] NO. I/O SYMBOL 1 VDD 2 B P81 3 B P82 4 B P83 5 B P84 6 B P85 7 B P86 8 B P87 9 B P90 10 B P91 www..com 11 B P92 12 B P93 13 B P94 14 B P95 15 B P96 16 B P97 17 B P10 18 B P11 19 B P12 20 B P13 21 B P14 22 B P15 23 B P16 24 B P17 25 VDD 26 VSS 27 B P20 28 B P21 29 B P22 30 B P23 31 B P24 32 B P25 33 B P26 34 B P27 35 B P30 36 B P31 37 B P32 38 B P33 39 B P34 40 B P35 41 B P36 42 B P37 43 B P40 44 B P41 45 B P42 46 B P43 47 B P44 48 B P45 49 B P46 50 VSS I : Input O : Output B : Both input and output NOTES NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O B B B B B B B B B I I I I I I I I I I I I B B B B B B B B B B B B B B B B B B B B B B B B B -
TE7753/TE7754
SYMBOL VDD P47 D0 D1 D2 D3 D4 D5 D6 D7 #RESET #CS #RD #WR A0 A1 A2 A3 lOS0 lOS1 lOS2 MS P50 P51 VDD VSS P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 VSS NOTES
Rev.1.00
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[Description of Pins] Pin name VDD VSS No. 1,25, 51,75 26,50, 76, 100 53-60 B
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TE7753/TE7754
Description Connect all pints to the power supply. Connect all pins to the ground.
I/O -
Pin function POWER SUPPLY GROUND
DATA BUS 8-bit bidirectional pins used for data communication with the CPU. The #CS, #RD, and #WR signals control the opening and closing the bus signal and data direction. For communication with the CPU, this signal is used to select nine ports and four command registers. Initialization pulse input pin. Initialization is performed when a level-0 signal is input. CMOS Schmitt trigger input When a level-0 signal is input to this pin, the data bus is released so that data communication can be performed with the CPU. When a level-0 signal is input while MS is 0, data is read from each port. When MS is 1, #RD is used in combination with the #WR signal. When a level-1 signal is input, data is read. When a level-0 signal is input, data is written. When a level-0 signal is input while MS is 0, data is written to command register of each port. When MS is 1, this signal becomes an R#W signal enable signal. This signal is used to select the mode of interfacing with the connected CPU. For more information, refer to "CPU Interface. " In soft mode, set all pins to input of 0. In hard mode, these three input pins can be used to select input/output combinations of each port. For more information, refer to 1, "Soft mode and hard mode," of "Description of Operation."
D7-0
A3-0
65-68 I
ADDRESS INPUT
#RESET
61 I
RESET
#CS
62 I
CHIP SELECT
#RD
63
READ/READ WRITE SELECT I
#WR
64 I
WRITE/M ENABLE
MS
72 I
MODE SELECT
IOS2-0
69-71
INPUT OUTPUT SELECT I
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Pin name P17-10 No. 17-24 I/O Pin function PORT
TE7753/TE7754
Description Port 1 8-bit general-purpose input/output port In hard mode, this port is always an input port. IOL=4mA Port 2 8-bit general-purpose input/output port In soft mode, input or output can be performed in units of 4 bits. IOL=4mA Port 3 8-bit general-purpose input/output port IOL=4mA Port 4 8-bit general-purpose input/output port IOL=4mA Port 5 8-bit general-purpose input/output port In soft mode, input or output can be performed in units of 4 bits. IOL=4mA Port 6 8-bit general-purpose input/output port IOL=4mA Port 7 8-bit general-purpose input/output port IOL=4mA Port 8 8-bit general-purpose input/output port In either mode, input or output can be performed in units of 4 bits. IOL=4mA Port 9 8-bit general-purpose input/output port In hard mode, this port is always an output port. IOL=12mA
P27-20
27-34
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P37-30
35-42
P47-40
43-49, 52 73,74 77-82 B
P57-50
P67-60
83-90
P77-70
91-98
P87-80
2-8,99
P97-90
9-16
Rev.1.00
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[CPU Interface]
TE7753/TE7754
The TE7753 and TE7754 each support the two CPU interface modes shown below. The MS pin is used to select the mode. [Relationship between CPU and select signal] Operation Read Write
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MS="0" #RD #WR
MS="1" R#W #MEN
The data sheet given here uses the signal names (#RD and #WR) applicable when MS is 0. For MS being 1, read them for the corresponding signal names shown above.
Rev.1.00
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[Description of Operation] 1. Soft mode and hard mode
TE7753/TE7754
The MS pin is used to select the mode of interfacing with the connected CPU. When MS is 0, separate pins are used for read and write signals (mainly for the 86 series). When MS is 1, a single pin is used for both read and write signals and another pin is used for the enable signal (mainly for the 68 series). The IOS2 to IOS0 pins are used to select the soft or hard mode. A port after resetting is in input state in soft mode and "H" output state in hard mode ("H" output with the TE7753 and "L" output with the TE7754). Mode selection Soft mode Hard mode IOS2 0 IOS1 0 Other than the above IOS0 0
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The TE7753 and TE7754 each can read port-output data through the CPU bus (D7-0). Read it by specifying the address (A3-0) while the port is in the output state. [Soft mode] The input and output of each port can be programmed by writing software commands to the command registers (CR) CR3-0 from the CPU. By writing output data in advance to each port before writing to the CR, data is output immediately after the port is set for output by the CR. IOS2"0", IOS1"0", IOS0"0" Port No 1 2 3 4 5 6 7 8 9 CR used CR1 Nibble input/output NG OK NG NG OK NG NG OK NG Bit input/output NG NG NG NG NG NG NG OK NG
CR2 CR3 CR0 CR3
Rev.1.00
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[Description of Registers]
TE7753/TE7754
In soft mode, CR is used to set a port for input or output. To set a port for output, write 0 to the register. To set it for input, write 1 to the register. The values indicated in each register are the initial values after resetting. CR0 1 1 1 1 1 1 1 1 CR1 1 1 1 1 CR2 1 1 1 1 CR3 P50-53 P60-67 P54-57 P40-47 D4 1 P70-77 D1 1 P90-97
D0 D1 D2 www..com D3 D4 D5 D6 D7
P80 P81 P82 P83 P84 P85 P86 P87
D0 D1 D3 D4
P20-23 P30-37 P24-27 P10-17
D0 D1 D3 D4
When MS is 0 [Read mode] MS 0 0 0 0 0 0 0 0 0 #CS 0 0 0 0 0 0 0 0 0 #RD 0 0 0 0 0 0 0 0 0 #WR 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 Operation Port1DataBus Port2DataBus Port3DataBus Port4DataBus Port5DataBus Port6DataBus Port7DataBus Port8DataBus Port9DataBus Input CPU operation
[Write mode] MS 0 0 0 0 0 0 0 0 0 0 0 0 0 #CS 0 0 0 0 0 0 0 0 0 0 0 0 0 #RD 1 1 1 1 1 1 1 1 1 1 1 1 1 #WR 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 Operation DataBusPort1 DataBusPort2 DataBusPort3 DataBusPort4 DataBusPort5 DataBusPort6 DataBusPort7 DataBusPort8 DataBusPort9 DataBusCR0 DataBusCR1 DataBusCR2 DataBusCR3 Output CPU operation
Rev.1.00
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When MS is 1 [Read mode] MS 1 1 1 1 1 1
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TE7753/TE7754
#CS 0 0 0 0 0 0 0 0 0
#RD 1 1 1 1 1 1 1 1 1
#WR 0 0 0 0 0 0 0 0 0
A3 0 0 0 0 0 0 0 0 1
A2 0 0 0 0 1 1 1 1 0
A1 0 0 1 1 0 0 1 1 0
A0 0 1 0 1 0 1 0 1 0
Operation Port1DataBus Port2DataBus Port3DataBus Port4DataBus Port5DataBus Port6DataBus Port7DataBus Port8DataBus Port9DataBus
CPU operation
Input
1 1 1
[Write mode] MS 1 1 1 1 1 1 1 1 1 1 1 1 1 #CS 0 0 0 0 0 0 0 0 0 0 0 0 0 #RD 0 0 0 0 0 0 0 0 0 0 0 0 0 #WR 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 Operation DataBusPort1 DataBusPort2 DataBusPort3 DataBusPort4 DataBusPort5 DataBusPort6 DataBusPort7 DataBusPort8 DataBusPort9 DataBusCR0 DataBusCR1 DataBusCR2 DataBusCR3 CPU operation
Output
Rev.1.00
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[Hard mode]
TE7753/TE7754
Use IOS2 to IOS0 in advance to set ports 2 to 7 for input or output. However, set only port 8 in the same way as in soft mode; write an 8-bit command to CR0 to set each bit for input or output. IOS2, IOS1, IOS0 Setting other than all 0 Port No 1
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CR used Always input IOS2 IOS1 IOS0 CR0 Always output
Nibble input/output NG NG NG NG NG NG NG OK NG
Bit input/output NG NG NG NG NG NG NG OK NG
2 3 4 5 6 7 8 9
In hard mode, each port is set for input or output by IOS2, IOS1, and IOS0. IOS0 0 0 0 1 1 1 1 0 IOS1 0 1 1 0 0 1 1 0 IOS2 1 0 1 0 1 0 1 0 PORT1 I I I I I I I PORT2 O I I I I I I PORT3 O O I I I I I PORT4 O O O I I I I PORT5 O O O O I I I PORT6 O O O O O I I PORT7 O O O O O O I PORT9 O O O O O O O
Soft mode
Rev.1.00
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2. Setting Each Port for Input or Output Using CR
TE7753/TE7754
The following two procedures are available for setting each port for input or output using CR:
Procedure (1)
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Procedure (2)
CPU Reset.
CPU Reset.
All ports are in the input state.
All ports are in the input state.
Select the CR by specifying the address. Set each port Select the output port by specifying the address. Write output data to the output port. for input or output.
Output port: "H" output with TE7753 "L" output with TE7754
Select the CR by specifying the address. Set each port for input or output.
Select the output port by specifying the address. Write output data to the output port.
Output
Output
Rev.1.00
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[Absolute Maximum Ratings]
TE7753/TE7754
The maximum ratings are the threshold values that must not be exceeded even momentarily. In other words, as long as the device is used within the range defined by the maximum ratings, no permanent damage is given to the device. However, this does not guarantee normal theoretical operation. Item Supply voltage Input voltage Output www..com voltage Operating ambient temperature Storage ambient temperature Symbol VDD VI VO TOP TST Rating -0.5 ~ +6.0 -0.5 ~ VDD+0.5 -0.5 ~ VDD+0.5 -40 ~ +85 -65 ~ +150 Unit V V V C C
[Recommended Operation Conditions] The recommended operation conditions indicate the values with which normal logic operation of the device is guaranteed. In other words, it is guaranteed that the electrical characteristics (DC and AC characteristics) are satisfied as long as the device is used within the scope of the recommended operation conditions. Item Supply voltage Operating ambient temperature Symbol VDD TA Min. 4.50 0 Max. 5.50 70 Pin V C
Rev.1.00
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[AC Characteristics] Specifications Min. 2.3 VSS VDD-0.4 VDD-0.4 VSS VSS
TE7753/TE7754
Item Supply current Level-1 input voltage Level-0 input voltage Level-H output voltage
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Symbol IDDS VIH VIL VOH VOL
Condition Stopped state (*1) TTL level standard TTL level standard IOH=-2mA IOH=-4mA IOL=4mA
Unit mA V V V V
Max. 0.1 VDD 0.7 VDD VDD 0.4 0.4
IOL=12mA *1 Voltage applied to input pin: Fixed to 0 V, VDD. Item Level-1 threshold voltage Level-0 threshold voltage Hysteresis width Symbol VT+ VTVT+-V TMin. 2.8 1.1 1.3
Level-L output voltage
Max. 3.8 1.8 2.0
Unit V
[Input/Output Pin Capacity] Item Input pin Output pin Input/output pin Symbol CIN COUT CII/O Specifications Up to 20 Up to 20 Up to 20 Unit PF
Rev.1.00
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[AC Characteristics]
TE7753/TE7754
Load characteristics are specified as 85 pF for an input/output pin and an output pin. 1. Writing to or reading from a port [When MS is 0]
P 1 7 ~ 10(input) P 97 ~ 90 (*1)
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A3 ~ 0 #CS
#RD
T1 T2 T3 T4 T5
D 7 ~ 0 (output)
T6
T7
Timing No. T1
Reference signal #RD
Applicable signal P17 ~ 10 : : P97 ~ 90 A3 ~ 0 #CS #RD P17 ~ 10 : : P97 ~ 90 A3 ~ 0 #CS D7 ~ 0 D7 ~ 0
Type S
Min. 0
Max. -
Unit
T2 T3 T4
#RD #RD #RD
S W H
0 55 0
-
ns
T5 T6 T7
#RD #RD #RD
H D H
0 5
40 20
Type specification : S: Setup H: Hold D: Delay W: Width *1 "P17 ~ 10" in the applicable signal column includes all of ports 1 to 9. : : P97 ~ 90
Rev.1.00
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TE7753/TE7754
D7 ~ 0(input)
A3 ~ 0 #C S
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#W R
T12 T11 T14 T15 T13
P 1 7 ~ 10(output)
: :
P 97 ~ 90
T16
Timing No. T11 T12 T13 T14 T15 T16
Reference signal #WR #WR #WR #WR #WR #WR A3 ~ 0 #CS D7 ~ 0 D7 ~ 0 #WR A3 ~ 0 #CS
Applicable signal
Type S S H W H D
Min. 3 6 0 25 0 -
Max. 30
Unit
ns
P17 ~ 10 : : P97 ~ 90
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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Soft mode #WR
TE7753/TE7754
P 17 ~ 10
: :
(Input - > output)
P 97 ~ 90 (Output -> input) P co ~ w w w . D a t a S h e e t 4 U .1 7 m 1 0
: :
T 21
P 97 ~ 90
T22
Hard mode
IOS2 ~ 0 P 17 ~ 10
: :
(Input - > output)
P97 ~ 90 ( O u t p u t - >n p u t ) P 17 ~ 10
: :
T2 3
P97 ~ 90
T24
Timing No. T21
Reference signal #WR P17 : : P97 P17 : : P97 P17 : : P97 P17 : : P97
Applicable signal ~ 10
Type D
Min. -
Max. 30
Unit
T22
#WR
~ 90 ~ 10
D
-
25
~ 90 ~ 10 D 15
T23
IOS2 ~ 0
ns
T24
IOS2 ~ 0
~ 90 ~ 10
D
-
10
~ 90
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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[When MS is 1] D7 ~ 0>
P17 ~ 10(Input) P 97 ~ 90
T1
TE7753/TE7754
T4
A3 ~ 0 #C S
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T2
T5
#RD
T 31 T3 2
#W R
T3
D7 ~ 0(Output)
T6 T7
Timing No. T31 T32
Reference signal #WR #WR #RD #RD
Applicable signal
Type S H
Min. 5 5
Max. -
Unit ns
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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< D7 ~ 0 ->port>
TE7753/TE7754
P17 ~ 10(Input) P 97 ~ 90
T 12 T13
A3 ~ 0 #C S
T 11 T15
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#RD
T4 1 T4 2
#W R
T14
D7 ~ 0(Output)
T16
Timing No. T41 T42
Reference signal #WR #WR #RD #RD
Applicable signal
Type S H
Min. 5 5
Max. -
Unit ns
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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Soft mode
TE7753/TE7754
#R D
#W R
T 51 T 52
P17 ~ 10
: :
( I n p u t -> o u t p u t )
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T 21
( O u t p u t -> i n p u t ) P17 ~ 10
: :
P9 7 ~ 9 0
T22
Hard mode
IOS2 ~ 0 P 17 ~ 10
: :
(Input ->output)
T2 3
P 97 ~ 90 ( O u t p u t -> i n p u t ) P 17 ~ 10
: :
P 97 ~ 90
T24
Timing No. T51 T52
Reference signal #WR #WR #RD #RD
Applicable signal
Type S H
Min. 5 5
Max. -
Unit ns
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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2. Reset Timing
TE7753/TE7754
#R E S E T
P 17 ~ 10(Input)
w w w . D a t a S h eP 94 U~ c9 0m et 7 . o
T 61
: :
Timing No. T61
Reference signal #RESET
Applicable signal P17 ~ 10 : : P97 ~ 90
Type D
Min. -
Max. 25
Unit
ns
Type specification : S: Setup H: Hold D: Delay W: Width
Rev.1.00
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[Reset Input Conditions] The TE7753/TE7754 reset input conditions are as follows:
T AW
TE7753/TE7754
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Characteristics Reset width
Symbol TAW
Min. 20
Max. -
Unit ns
Rev.1.00
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[Outside Dimensions] 100-pin plastic QFP (unit: mm)
TE7753/TE7754
16.0
14.0
0.2SQ
0.2SQ
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75 76
51 50
100 1 1.00 0.22
+0.05 -0.04
25
26
0.50
0.80 M
1.40
0.05
1.0
0.20
1.60max
0.08
S
0.50
0.20 0 . 1 7 -0.07
+0.03
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TE7753/TE7754
m em o
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Rev.1.00
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TE7753/TE7754
m em o
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TE7753/TE7754
NOTES 1) Tokyo Electron Device Limited does not assume any responsibility for any circuitry described other than the circuitry embodied in its product, nor represents that circuitry described herein is free from patent or copyright infringement or other rights of third parties which may result from its use. 2) Tokyo Electron Device Limited reserves the right to make changes without further notice to any products herein. TEL shall not be liable for any claim or action by third parties alleging an infringement of the intellectual property rights, such as the patent, utility models right, mask works right and copyright, where alleged liability of Users arises by reason of using "this device" in combination with other products, or of any derivative products integrating "this device".
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ASIA and EUROPE TOKYO ELECTRON DEVICE LIMITED TOP Marketing Group 1, Higashi-Kata-Chou, Tsuzuki-ku, Yokohama-City, Kanagawa 224-0045 JAPAN U.S.A. TEL:+81-45-474-7035 FAX:+81-45-474-5624 E-mail:top-e@teldevice.co.jp Your Local Contact
U.S. and CANADA TOKYO ELECTRON AMERICA INC. 2953 Bunker Hill Lane, Suite 201 Santa Clara, CA 95054 TEL: +1-408-919-4772 E-mail: top@scl.telusa.com
(c) Toyko Electron Device Limited 2000 All rights reserved
Printed in JAPAN November 2000
Rev.1.00
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